Commit Graph

63102 Commits

Author SHA1 Message Date
Benjamin Kramer 5bc180c14f X86: Turn fp selects into mask operations.
double test(double a, double b, double c, double d) { return a<b ? c : d; }

before:
_test:
	ucomisd	%xmm0, %xmm1
	ja	LBB0_2
	movaps	%xmm3, %xmm2
LBB0_2:
	movaps	%xmm2, %xmm0

after:
_test:
	cmpltsd	%xmm1, %xmm0
	andpd	%xmm0, %xmm2
	andnpd	%xmm3, %xmm0
	orpd	%xmm2, %xmm0

Small speedup on Benchmarks/SmallPT

llvm-svn: 187706
2013-08-04 12:05:16 +00:00
Elena Demikhovsky cd46691728 AVX-512 set: added VEXTRACTPS instruction
llvm-svn: 187705
2013-08-04 10:46:07 +00:00
Tim Northover ecc018c7b7 X86: correct tail return address calculation
Due to the weird and wondeful usual arithmetic conversions, some
calculations involving negative values were getting performed in
uint32_t and then promoted to int64_t, which is really not a good
idea.

Patch by Katsuhiro Ueno.

llvm-svn: 187703
2013-08-04 09:35:57 +00:00
Benjamin Kramer 1df3a1f678 AsmParser: Store MacroLikeBodies on the side so they don't get leaked.
llvm-svn: 187702
2013-08-04 09:06:29 +00:00
Reed Kotler 30cedf65ef Clean up code for Mips16 large frame handling.
llvm-svn: 187701
2013-08-04 01:13:25 +00:00
Benjamin Kramer 72d45cc846 PPCAsmParser: Stop leaking names.
Store them in a place that gets cleaned up properly.

llvm-svn: 187700
2013-08-03 22:43:29 +00:00
Benjamin Kramer 097e09abba MachObjectFile: Don't leak on error.
llvm-svn: 187698
2013-08-03 22:16:37 +00:00
Benjamin Kramer 23632bd466 ARMAsmParser: Plug a leak.
Using an object to do the cleanup may look like overkill, but it's safer and nicer than putting deletes everywhere.

llvm-svn: 187696
2013-08-03 22:16:24 +00:00
Benjamin Kramer dcfd5b525a Stop leaking register infos in the disassemblers.
llvm-svn: 187695
2013-08-03 22:16:16 +00:00
Hal Finkel b176acb6b7 Fix PPC64 64-bit GPR inline asm constraint matching
Internally, the PowerPC backend names the 32-bit GPRs R[0-9]+, and names the
64-bit parent GPRs X[0-9]+. When matching inline assembly constraints with
explicit register names, on PPC64 when an i64 MVT has been requested, we need
to follow gcc's convention of using r[0-9]+ to refer to the 64-bit (parent)
registers.

At some point, we'll probably want to arrange things so that the generic code
in TargetLowering uses the AsmName fields declared in *RegisterInfo.td in order
to match these inline asm register constraints. If we do that, this change can
be reverted.

llvm-svn: 187693
2013-08-03 12:25:10 +00:00
Matt Arsenault 2f9cce2cd6 Minor address space code simplification.
Remove assertion that the verifier should catch.

llvm-svn: 187692
2013-08-03 01:03:12 +00:00
Peter Collingbourne abca2ecaab Add a AttributeSetImpl::dump function.
This is for the benefit of those of us with inferior debuggers which
do not permit member function calls on value types.

llvm-svn: 187685
2013-08-02 22:34:30 +00:00
Peter Collingbourne bd6c7459bb Make one of the AttributeSet ctors maintain the invariant that the
attribute list is ordered by index.

Differential Revision: http://llvm-reviews.chandlerc.com/D1265

llvm-svn: 187682
2013-08-02 22:29:40 +00:00
Hans Wennborg b8f3420d1e Option parsing: recognize the special -- token
Everything that comes after -- should be treated as a filename. This
enables passing in filenames that would otherwise be conflated with
command-line options.

This is especially important for clang-cl which supports options
starting with /, which are easily conflatable with Unix-style
path names.

Differential Revision: http://llvm-reviews.chandlerc.com/D1274

llvm-svn: 187675
2013-08-02 21:20:27 +00:00
Joey Gouly fcf6778172 Add a missing 'return' statement.
llvm-svn: 187671
2013-08-02 20:50:01 +00:00
Akira Hatanaka 7be35cb1bf [mips] Expand vector truncating stores and extending loads.
llvm-svn: 187667
2013-08-02 19:23:33 +00:00
Joey Gouly 5d0564d2e6 [ARMv8] Add an assembler warning for the deprecated 'setend' instruction.
llvm-svn: 187666
2013-08-02 19:18:12 +00:00
Nadav Rotem 5defea90e6 SLPVectorizer: Fix PR16777. PHInodes may use multiple extracted values that come from different blocks.
Thanks Alexey Samsonov.

llvm-svn: 187663
2013-08-02 18:40:24 +00:00
Renato Golin 0178a25fc5 Fixes ARM LNT bot from SLP change in O3
This patch fixes the multiple breakages on ARM test-suite after the SLP
vectorizer was introduced by default on O3. The problem was an illegal
vector type on ARMTTI::getCmpSelInstrCost() <3 x i1> which is not simple.

The guard protects this code from breaking (cause of the problems) but
doesn't fix the issue that is generating the odd vector in the first
place, which also needs to be investigated.

llvm-svn: 187658
2013-08-02 17:10:04 +00:00
Carlo Kok 4382da983a Bugfix for making the DWARF debug strings and labels to code emitted as secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB (with fix for 64bits msvc)
llvm-svn: 187656
2013-08-02 16:14:15 +00:00
Duncan Sands 3194fca45f Pacify GCC, which worries about falling off the end of the switch.
llvm-svn: 187649
2013-08-02 09:37:20 +00:00
Alexey Samsonov 9096968de5 Fix dereferencing end iterator in SimplifyCFG. Patch by Ye Mei.
llvm-svn: 187646
2013-08-02 08:06:43 +00:00
NAKAMURA Takumi 6fda3b4b86 Revert r187597, "Bugfix for making the DWARF debug strings and labels to code emitted as secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB."
It broke x86_64-win32 builder in llvm/test/DebugInfo.

llvm-svn: 187642
2013-08-02 03:46:05 +00:00
Eric Christopher cdc78961d3 Temporarily revert "Debug Info Finder|Verifier: handle DbgLoc attached to
instructions." in an attempt to bring back some bots.

This reverts commit r187609.

llvm-svn: 187638
2013-08-02 00:49:44 +00:00
Matt Arsenault 1c349ef7e8 Teach InstructionSimplify about pointer address spaces
llvm-svn: 187635
2013-08-02 00:10:44 +00:00
Akira Hatanaka 21f334372e [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,
remove lines that are setting DecoderNamespace for pseudo atomic instructions.

No intended functionality change.

llvm-svn: 187632
2013-08-01 23:14:16 +00:00
Matt Arsenault 87dc60761f Teach getOrEnforceKnownAlignment about address spaces
llvm-svn: 187629
2013-08-01 22:42:18 +00:00
Nadav Rotem e4e6e9ed47 Move the optlevel check to the frontend.
llvm-svn: 187628
2013-08-01 22:41:58 +00:00
Bill Wendling a5c536e1ee Use function attributes to indicate that we don't want to realign the stack.
Function attributes are the future! So just query whether we want to realign the
stack directly from the function instead of through a random target options
structure.

llvm-svn: 187618
2013-08-01 21:42:05 +00:00
Daniel Malea a3d4245a72 Fixed the Intel-syntax X86 disassembler to respect the (existing) option for hexadecimal immediates, to match AT&T syntax. This also brings a new option for C-vs-MASM-style hex.
Patch by Richard Mitton
Reviewed: http://llvm-reviews.chandlerc.com/D1243

llvm-svn: 187614
2013-08-01 21:18:16 +00:00
Reed Kotler 83f879ddb2 Fix some issues with Mips16 floating when certain intrinsics are present.
This is actually an LLVM bug in the way it generates signatures for these
when soft float is enabled. For example, floor ends up having the signature
of int64(int64). The signature part is not the same as where the actual
parameter types are recorded, and those ARE of course int64(int64) when
soft float is enabled. (Yes, Mips16 hard float uses soft float but with
different runtime rounes but then has to interoperate with Mips32 using
normal floating point). This logic will eventually be moved to the 
Mips16HardFloat pass so it's not worth sorting out these issues in LLVM
since nobody but Mips16 cares about these signatures, as far as I know,
and even I won't eventually either.

llvm-svn: 187613
2013-08-01 21:17:53 +00:00
Manman Ren 4c065e779c Debug Info Finder|Verifier: handle DbgLoc attached to instructions.
Also remove checking of llvm.dbg.sp since it is not used in generating dwarf.

Current state of Finder:
DebugInfoFinder tries to list all debug info MDNodes used in a module. To
list debug info MDNodes used by an instruction, DebugInfoFinder provides
processDeclare, processValue and processLocation to handle DbgDeclareInst,
DbgValueInst and DbgLoc attached to instructions. processModule will go
through all DICompileUnits in llvm.dbg.cu and list debug info MDNodes
used by the CUs.

TODO:
1> Finder has a list of CUs, SPs, Types, Scopes and global variables. We
need to add a list of variables that are used by DbgDeclareInst and
DbgValueInst.
2> MDString fields should be null or isa<MDString> and MDNode fields should be
null or isa<MDNode>. We currently use empty string or int 0 to represent null.
3> Go though Verify functions and make sure that they check field types.
4> Clean up existing testing cases to remove llvm.dbg.sp and make sure each
testing case has a llvm.dbg.cu.

llvm-svn: 187609
2013-08-01 20:52:39 +00:00
David Blaikie a1ae0e6ecb DebugInfo: Emit definitions for types with no members.
The absence of members was a poor/incorrect proxy for "is definition".

llvm-svn: 187607
2013-08-01 20:30:22 +00:00
Carlo Kok afcc62024e Bugfix for making the DWARF debug strings and labels to code emitted as secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB.
fixes Bug 16249 - LLVM generates broken debug info on Windows 

llvm-svn: 187597
2013-08-01 18:38:14 +00:00
Nadav Rotem 9153b3871d Only enable SLP-vectorization on O3 builds.
llvm-svn: 187595
2013-08-01 18:28:15 +00:00
Tom Stellard 0344cdfe39 R600: Add 64-bit float load/store support
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions

Tom Stellard:
  - Mark vec2 operations as expand.  The addition of a vec2 register
    class made them all legal.

Patch by: Dmitry Cherkassov

Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
2013-08-01 15:23:42 +00:00
Tom Stellard 53698938a4 R600: Use 64-bit alignment for 64-bit kernel arguments
llvm-svn: 187581
2013-08-01 15:23:31 +00:00
Tom Stellard 98f675a994 R600/SI: Custom lower i64 ZERO_EXTEND
llvm-svn: 187580
2013-08-01 15:23:26 +00:00
Elena Demikhovsky b1266b5447 EVEX and compressed displacement encoding for AVX512
llvm-svn: 187576
2013-08-01 13:34:06 +00:00
Richard Sandiford fd7f4ae6d4 [SystemZ] Reuse CC results for integer comparisons with zero
This also fixes a bug in the predication of LR to LOCR: I'd forgotten
that with these in-place instruction builds, the implicit operands need
to be added manually.  I think this was latent until now, but is tested
by int-cmp-45.c.  It also adds a CC valid mask to STOC, again tested by
int-cmp-45.c.

llvm-svn: 187573
2013-08-01 10:39:40 +00:00
Richard Sandiford a075708abe [SystemZ] Prefer comparisons with zero
Convert >= 1 to > 0, etc.  Using comparison with zero isn't a win on its own,
but it exposes more opportunities for CC reuse (the next patch).

llvm-svn: 187571
2013-08-01 10:29:45 +00:00
Vladimir Medic d3dade29f5 Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested.
llvm-svn: 187569
2013-08-01 09:25:27 +00:00
Tim Northover 40e9efd725 AArch64: add initial NEON support
Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

llvm-svn: 187567
2013-08-01 09:20:35 +00:00
Robert Lytton 4be00f8ad1 XCore target: Fix Vararg handling
llvm-svn: 187565
2013-08-01 08:29:44 +00:00
Robert Lytton 4e60a3f4e3 XCore target: Add byval handling
llvm-svn: 187563
2013-08-01 08:18:55 +00:00
Robert Lytton b4787a159d Xcore target
Fix emitArrayBound() calling OutStreamer.Emit*() multiple times when trying to print a single line

llvm-svn: 187562
2013-08-01 07:52:05 +00:00
Reed Kotler 302ae6b002 Fix some misc. issues with Mips16 fp stubs.
1) They should never be inlined.
2) A naming inconsistency with gcc mips16
3) Stubs should not have the global attribute

llvm-svn: 187555
2013-08-01 02:26:31 +00:00
Reed Kotler fd132b99bb Add an omitted IsCall=1.
llvm-svn: 187553
2013-08-01 00:59:06 +00:00
Hans Wennborg 5fdcf86861 Option parsing: add support for alias arguments.
This makes option aliases more powerful by enabling them to
pass along arguments to the option they're aliasing.

For example, if we have a joined option "-foo=", we can now
specify a flag option "-bar" to be an alias of that, with the
argument "baz".

This is especially useful for the cl.exe compatible clang driver,
where many options are aliases. For example, this patch enables
us to alias "/Ox" to "-O3" (-O is a joined option), and "/WX" to
"-Werror" (again, -W is a joined option).

Differential Revision: http://llvm-reviews.chandlerc.com/D1245

llvm-svn: 187537
2013-07-31 22:44:41 +00:00
Nadav Rotem 25f15358d2 80-col
llvm-svn: 187535
2013-07-31 22:17:45 +00:00
Kevin Enderby 78f9572f39 Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match.  Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.

rdar://14214063

llvm-svn: 187530
2013-07-31 21:05:30 +00:00
Tom Stellard ca69a53bae Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.

llvm-svn: 187526
2013-07-31 20:43:27 +00:00
Tom Stellard 4dd41845ec Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
This reverts commit 3f1de26cb5cc0543a6a1d71259a7a39d97139051.

llvm-svn: 187524
2013-07-31 20:43:03 +00:00
Vincent Lejeune 220db748b0 R600: Do not mergevector after a vector reg is used
If we merge vector when a vector is used, it will generate an artificial
antidependency that can prevent 2 tex/vtx instructions to use the same
clause and thus generate extra clauses that reduce performance.

There is no test case as such situation is really hard to predict.

llvm-svn: 187516
2013-07-31 19:32:12 +00:00
Vincent Lejeune bb3f931123 R600: Avoid more than 4 literals in the same instruction group at scheduling
llvm-svn: 187515
2013-07-31 19:32:07 +00:00
Vincent Lejeune df18804e26 R600: Non vector only instruction can be scheduled on trans unit
llvm-svn: 187514
2013-07-31 19:31:56 +00:00
Vincent Lejeune 21de8baa15 R600: Don't mix LDS and non-LDS instructions in the same group
There are a lot of restrictions on instruction groups that contain
LDS instructions, so for now we will be conservative and not packetize
anything else with them.

llvm-svn: 187513
2013-07-31 19:31:41 +00:00
Vincent Lejeune 79afe17e99 R600: Use SchedModel enum for is{Trans,Vector}Only functions
llvm-svn: 187512
2013-07-31 19:31:35 +00:00
Vincent Lejeune 0c5ed2b437 R600: Remove predicated_break inst
We were using two instructions for similar purpose : break and
predicated break. Only predicated_break was emitted and it was
lowered at R600ControlFlowFinalizer to JUMP;CF_BREAK;POP.
This commit simplify the situation by making AMDILCFGStructurizer
emit IF_PREDICATE;BREAK;ENDIF; instead of predicated_break (which
is now removed).

There is no functionality change.

llvm-svn: 187510
2013-07-31 19:31:14 +00:00
Matt Arsenault 24b49c411c Reject bitcasts between address spaces with different sizes
llvm-svn: 187506
2013-07-31 17:49:08 +00:00
Richard Sandiford 791bea4182 [SystemZ] Implement isLegalAddressingMode()
The loop optimizers were assuming that scales > 1 were OK.  I think this
is actually a bug in TargetLoweringBase::isLegalAddressingMode(),
since it seems to be trying to reject anything that isn't r+i or r+r,
but it has no default case for scales other than 0, 1 or 2.  Implementing
the hook for z means that z can no longer test any change there though.

llvm-svn: 187497
2013-07-31 12:58:26 +00:00
Richard Sandiford ee8343822e [SystemZ] Be more careful about inverting CC masks (conditional loads)
Extend r187495 to conditional loads.  I split this out because the
easiest way seemed to be to force a particular operand order in
SystemZISelDAGToDAG.cpp.

llvm-svn: 187496
2013-07-31 12:38:08 +00:00
Richard Sandiford 3d768e334b [SystemZ] Be more careful about inverting CC masks
System z branches have a mask to select which of the 4 CC values should
cause the branch to be taken.  We can invert a branch by inverting the mask.
However, not all instructions can produce all 4 CC values, so inverting
the branch like this can lead to some oddities.  For example, integer
comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater).
If an integer EQ is reversed to NE before instruction selection,
the branch will test for 1 or 2.  If instead the branch is reversed
after instruction selection (by inverting the mask), it will test for
1, 2 or 3.  Both are correct, but the second isn't really canonical.
This patch therefore keeps track of which CC values are possible
and uses this when inverting a mask.

Although this is mostly cosmestic, it fixes undefined behavior
for the CIJNLH in branch-08.ll.  Another fix would have been
to mask out bit 0 when generating the fused compare and branch,
but the point of this patch is that we shouldn't need to do that
in the first place.

The patch also makes it easier to reuse CC results from other instructions.

llvm-svn: 187495
2013-07-31 12:30:20 +00:00
Richard Sandiford 8a757bba10 [SystemZ] Move compare-and-branch generation even later
r187116 moved compare-and-branch generation from the instruction-selection
pass to the peephole optimizer (via optimizeCompare).  It turns out that even
this is a bit too early.  Fused compare-and-branch instructions don't
interact well with predication, where a CC result is needed.  They also
make it harder to reuse the CC side-effects of earlier instructions
(not yet implemented, but the subject of a later patch).

Another problem was that the AnalyzeBranch family of routines weren't
handling compares and branches, so we weren't able to reverse the fused
form in cases where we would reverse a separate branch.  This could have
been fixed by extending AnalyzeBranch, but given the other problems,
I've instead moved the fusing to the long-branch pass, which is also
responsible for the opposite transformation: splitting out-of-range
compares and branches into separate compares and long branches.

I've added a test for the AnalyzeBranch problem.  A test for the
predication problem is included in the next patch, which fixes a bug
in the choice of CC mask.

llvm-svn: 187494
2013-07-31 12:11:07 +00:00
Elena Demikhovsky b0a75431ad Fixed assertion in Extract128BitVector()
llvm-svn: 187493
2013-07-31 12:03:08 +00:00
Richard Sandiford 6a06ba36ba [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()
r186399 aggressively used the RISBG instruction for immediate ANDs,
both because it can handle some values that AND IMMEDIATE can't,
and because it allows the destination register to be different from
the source.  I realized later while implementing the distinct-ops
support that it would be better to leave the choice up to
convertToThreeAddress() instead.  The AND IMMEDIATE form is shorter
and is less likely to be cracked.

This is a problem for 32-bit ANDs because we assume that all 32-bit
operations will leave the high word untouched, whereas RISBG used in
this way will either clear the high word or copy it from the source
register.  The patch uses the z196 instruction RISBLG for this instead.

This means that z10 will be restricted to NILL, NILH and NILF for
32-bit ANDs, but I think that should be OK for now.  Although we're
using z10 as the base architecture, the optimization work is going
to be focused more on z196 and zEC12.

llvm-svn: 187492
2013-07-31 11:36:35 +00:00
Elena Demikhovsky 67b05fc0b3 Added INSERT and EXTRACT intructions from AVX-512 ISA.
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.

llvm-svn: 187491
2013-07-31 11:35:14 +00:00
Richard Sandiford 6cf80b3ec0 [SystemZ] Add RISBLG and RISBHG instruction definitions
The next patch will make use of RISBLG for codegen.

llvm-svn: 187490
2013-07-31 11:17:35 +00:00
Richard Trieu 8dc432314e Add parentheses to silence gcc warning.
llvm-svn: 187482
2013-07-31 04:07:28 +00:00
Craig Topper 62cb2bc837 Increment arg_count inside the loop in printInline. Patch by Joe Matarazzo.
llvm-svn: 187477
2013-07-31 03:22:07 +00:00
Craig Topper efd67d4612 Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
Patch by Richard Mitton.

llvm-svn: 187476
2013-07-31 02:47:52 +00:00
Andrew Trick c3bc8b8de6 Fix a severe compile time problem when forming large SCEV expressions.
This fix is very lightweight. The same fix already existed for AddRec
but was missing for NAry expressions.

This is obviously an improvement and I'm unsure how to test compile
time problems.

Patch by Xiaoyi Guo!

llvm-svn: 187475
2013-07-31 02:43:40 +00:00
Craig Topper 75a5ba7ed0 Remove trailing whitespace and some tab characters.
llvm-svn: 187472
2013-07-31 02:00:15 +00:00
Craig Topper 6e8cd80def Fixed incorrect disassembly for MOV16o16a when using Intel syntax.
Patch by Richard Mitton.

llvm-svn: 187471
2013-07-31 01:50:26 +00:00
Eric Christopher e6656ac870 Fix crashing on invalid inline asm with matching constraints.
For a testcase like the following:

 typedef unsigned long uint64_t;

 typedef struct {
   uint64_t lo;
   uint64_t hi;
 } blob128_t;

 void add_128_to_128(const blob128_t *in, blob128_t *res) {
   asm ("PAND %1, %0" : "+Q"(*res) : "Q"(*in));
 }

where we'll fail to allocate the register for the output constraint,
our matching input constraint will not find a register to match,
and could try to search past the end of the current operands array.

On the idea that we'd like to attempt to keep compilation going
to find more errors in the module, change the error cases when
we're visiting inline asm IR to return immediately and avoid
trying to create a node in the DAG. This leaves us with only
a single error message per inline asm instruction, but allows us
to safely keep going in the general case.

llvm-svn: 187470
2013-07-31 01:26:24 +00:00
Akira Hatanaka d6445686a9 [mips] Rename instruction DANDi to ANDi64.
No functionality change.

llvm-svn: 187469
2013-07-31 00:57:41 +00:00
Akira Hatanaka f8fff213d5 [mips] Define instruction itineraries IIArith and IILogic.
No functionality change.

llvm-svn: 187468
2013-07-31 00:55:34 +00:00
Matt Arsenault 065ced9bed Fix ptr vector inconsistency in CreatePointerCast
One form would accept a vector of pointers, and the other did not.
Make both accept vectors of pointers, and add an assertion
for the number of elements.

llvm-svn: 187464
2013-07-31 00:17:33 +00:00
Rafael Espindola 107b74c6c3 Fix windows' implementation of status when a file doesn't exist.
The unix one was returning no_such_file_or_directory, but the windows one
was return success.

Update the one one caller that was depending on the old behavior.

llvm-svn: 187463
2013-07-31 00:10:25 +00:00
Owen Anderson c7be519dc0 Preserve fast-math flags when folding (fsub x, (fneg y)) to (fadd x, y).
llvm-svn: 187462
2013-07-30 23:53:17 +00:00
Eric Christopher 029af15086 Reflow this to be easier to read.
llvm-svn: 187459
2013-07-30 22:50:44 +00:00
Matt Arsenault 130e0ef6f4 Respect address space sizes in isEliminableCastPair.
This avoids constant folding bitcast/ptrtoint/inttoptr combinations
that have illegal bitcasts between differently sized address spaces.

llvm-svn: 187455
2013-07-30 22:27:10 +00:00
Matt Arsenault b4019ae13c Revert "Remove isCastable since nothing uses it now"
Apparently dragonegg uses it.

llvm-svn: 187454
2013-07-30 22:02:14 +00:00
Matt Arsenault f63dfbb198 Remove isCastable since nothing uses it now
llvm-svn: 187448
2013-07-30 21:11:17 +00:00
David Majnemer b7d5409ad2 isKnownToBeAPowerOfTwo: Strengthen isKnownToBeAPowerOfTwo's analysis on add instructions
Call into ComputeMaskedBits to figure out which bits are set on both add
operands and determine if the value is a power-of-two-or-zero or not.

llvm-svn: 187445
2013-07-30 21:01:36 +00:00
Matt Arsenault cacbb2377a Change behavior of calling bitcasted alias functions.
It will now only convert the arguments / return value and call
the underlying function if the types are able to be bitcasted.
This avoids using fp<->int conversions that would occur before.

llvm-svn: 187444
2013-07-30 20:45:05 +00:00
Akira Hatanaka 8f69d7f0c0 [mips] Delete instruction format for "bal".
llvm-svn: 187443
2013-07-30 20:42:19 +00:00
Rafael Espindola a5932afef0 Implement getUniqueID for directories on windows.
llvm-svn: 187441
2013-07-30 20:25:53 +00:00
Akira Hatanaka 5973e8371a [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that
turns "bal" into "bgezal".

llvm-svn: 187440
2013-07-30 20:24:24 +00:00
Rafael Espindola 62b418e2de Remove dead code.
llvm-svn: 187439
2013-07-30 20:02:18 +00:00
Andrew Trick c7934b3e37 Down-scale slot index distance to save bits.
llvm-svn: 187438
2013-07-30 19:59:19 +00:00
Andrew Trick 9c17eab761 MI Sched: Track live-thru registers.
When registers must be live throughout the scheduling region, increase
the limit for the register class. Once we exceed the original limit,
they will be spilled, and there's no point further reducing pressure.

This isn't a perfect heuristics but avoids a situation where the
scheduler could become trapped by trying to achieve the impossible.

llvm-svn: 187436
2013-07-30 19:59:12 +00:00
Andrew Trick d9761776bc MI Sched fix: assert "Disconnected LRG within the scheduling region."
llvm-svn: 187435
2013-07-30 19:59:08 +00:00
Venkatraman Govindaraju fee76fac2f [Sparc] Rewrite MBB's live-in registers for leaf functions. Also, add
register i7 as a live-in if current function's return address is taken.

This revision fixes PR16269.

llvm-svn: 187433
2013-07-30 19:53:10 +00:00
Rui Ueyama a2222b573b Implement TokenizeWindowsCommandLine.
This is a follow up patch for r187390 to implement the parser for the
Windows-style command line. This should follow the rule as described
at http://msdn.microsoft.com/en-us/library/windows/desktop/17w5ykft(v=vs.85).aspx

Differential Revision: http://llvm-reviews.chandlerc.com/D1235

llvm-svn: 187430
2013-07-30 19:03:20 +00:00
Tom Stellard aa313d0a74 R600/SI: Expand vector fp <-> int conversions
llvm-svn: 187421
2013-07-30 14:31:03 +00:00
Vladimir Medic 643b398786 This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
llvm-svn: 187410
2013-07-30 10:12:14 +00:00
Saleem Abdulrasool 0c2ee5a2cb [ARM] check bitwidth in PerformORCombine
When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the
bitwidth of the second operands to both ands match before comparing the negation
of the values.

Split the check of the value of the second operands to the ands.  Move the cast
and variable declaration slightly higher to make it slightly easier to follow.

Bug-Id: 16700
Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
llvm-svn: 187404
2013-07-30 04:43:08 +00:00
Venkatraman Govindaraju fdcc498a25 [Sparc] Use call's debugloc for the unimp instruction.
llvm-svn: 187402
2013-07-30 02:26:29 +00:00
Bill Schmidt 0cf702fa61 [PowerPC] Skeletal FastISel support for 64-bit PowerPC ELF.
This is the first of many upcoming patches for PowerPC fast
instruction selection support.  This patch implements the minimum
necessary for a functional (but extremely limited) FastISel pass.  It
allows the table-generated portions of the selector to be created and
used, but in most cases selection will fall back to the DAG selector.
None of the block terminator instructions are implemented yet, and
most interesting instructions require some special handling.
Therefore there aren't any new test cases with this patch.  There will
be quite a few tests coming with future patches.

This patch adds the make/CMake support for the new code (including
tablegen -gen-fast-isel) and creates the FastISel object for PPC64 ELF
only.  It instantiates the necessary virtual functions
(TargetSelectInstruction, TargetMaterializeConstant,
TargetMaterializeAlloca, tryToFoldLoadIntoMI, and FastLowerArguments),
but of these, only TargetMaterializeConstant contains any useful
implementation.  This is present since the table-generated code
requires the ability to materialize integer constants for some
instructions.

This patch has been tested by building and running the
projects/test-suite code with -O0.  All tests passed with the
exception of a couple of long-running tests that time out using -O0
code generation.

llvm-svn: 187399
2013-07-30 00:50:39 +00:00