Commit Graph

63102 Commits

Author SHA1 Message Date
Justin Holewinski 8b24e1e4fb [NVPTX] We dont have any target specific flags yet for generating symbol references, so get rid of the default-only switch statement. Fixes an MSVC warning.
llvm-svn: 187829
2013-08-06 23:06:42 +00:00
Akira Hatanaka c7e3998e45 [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of
instructions defined in MipsInstrInfo.td as codegen-only instructions.

llvm-svn: 187828
2013-08-06 23:01:10 +00:00
Bill Wendling 58f8cef83b Change the linkage of these global values to 'internal'.
The globals being generated here were given the 'private' linkage type. However,
this caused them to end up in different sections with the wrong prefix. E.g.,
they would be in the __TEXT,__const section with an 'L' prefix instead of an 'l'
(lowercase ell) prefix.

The problem is that the linker will eat a literal label with 'L'. If a weak
symbol is then placed into the __TEXT,__const section near that literal, then it
cannot distinguish between the literal and the weak symbol.

Part of the problems here was introduced because the address sanitizer converted
some C strings into constant initializers with trailing nuls. (Thus putting them
in the __const section with the wrong prefix.) The others were variables that
the address sanitizer created but simply had the wrong linkage type.

llvm-svn: 187827
2013-08-06 22:52:42 +00:00
Reid Kleckner d78273f4fd Remove some std stream usage from Support and TableGen
LLVM's coding standards recommend raw_ostream and MemoryBuffer for
reading and writing text.

This has the side effect of allowing clang to compile more of Support
and TableGen in the Microsoft C++ ABI.

llvm-svn: 187826
2013-08-06 22:51:21 +00:00
Arnold Schwaighofer a7cd6bf3bb LoopVectorize: Allow vectorization of loops with lifetime markers
Patch by Marc Jessome!

llvm-svn: 187825
2013-08-06 22:37:52 +00:00
Akira Hatanaka e2a39e7532 [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.

llvm-svn: 187824
2013-08-06 22:35:29 +00:00
Akira Hatanaka 34a32c0b87 [mips] Replace usages of register classes with register operands. Also, remove
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.

llvm-svn: 187821
2013-08-06 22:20:40 +00:00
Manman Ren b75e0c92f3 Debug Info Finder|Verifier: handle DbgLoc attached to instructions.
Also remove checking of llvm.dbg.sp since it is not used in generating dwarf.

Current state of Finder:
DebugInfoFinder tries to list all debug info MDNodes used in a module. To
list debug info MDNodes used by an instruction, DebugInfoFinder provides
processDeclare, processValue and processLocation to handle DbgDeclareInst,
DbgValueInst and DbgLoc attached to instructions. processModule will go
through all DICompileUnits in llvm.dbg.cu and list debug info MDNodes
used by the CUs.

TODO:
1> Finder has a list of CUs, SPs, Types, Scopes and global variables. We
need to add a list of variables that are used by DbgDeclareInst and
DbgValueInst.
2> MDString fields should be null or isa<MDString> and MDNode fields should be
null or isa<MDNode>. We currently use empty string or int 0 to represent null.
3> Go though Verify functions and make sure that they check field types.
4> Clean up existing testing cases to remove llvm.dbg.sp and make sure each
testing case has a llvm.dbg.cu.

Re-apply r187609 with fix to pass ocaml binding. vmcore.ml generates a debug
location with scope being metadata !{}, in verifier we treat this as a null
scope.

llvm-svn: 187812
2013-08-06 19:38:43 +00:00
Jakub Staszak 27da123d66 Adjust file to the coding standard.
llvm-svn: 187808
2013-08-06 17:03:42 +00:00
Hal Finkel 11b9e452f6 Add PPC64 mulli pattern
The PPC backend had been missing a pattern to generate mulli for 64-bit
multiples. We had been generating it only for 32-bit multiplies. Unfortunately,
generating li + mulld unnecessarily increases register pressure.

llvm-svn: 187807
2013-08-06 17:03:03 +00:00
Jakub Staszak 340c780dd6 Remove extraneous semicolon.
llvm-svn: 187806
2013-08-06 16:40:40 +00:00
Mihai Popa c34bf73ebb This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)

llvm-svn: 187804
2013-08-06 16:07:46 +00:00
Mihai Popa 8f49a45c68 Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc instead of apsr_nzcv)
llvm-svn: 187803
2013-08-06 15:52:36 +00:00
Justin Holewinski debe686f05 [NVPTX] Add missing patterns for i1 [s,u]int_to_fp
llvm-svn: 187800
2013-08-06 14:13:34 +00:00
Justin Holewinski 871ec93909 [NVPTX] Fix bug in stack code generation causes by MC conversion
We do use a very small set of physical registers, so account for
them in the virtual register encoding between MachineInstr and MC

llvm-svn: 187799
2013-08-06 14:13:31 +00:00
Justin Holewinski a2a63d28df [NVPTX] Start conversion to MC infrastructure
This change converts the NVPTX target to use the MC infrastructure
instead of directly emitting MachineInstr instances. This brings
the target more up-to-date with LLVM TOT, and should fix PR15175
and PR15958 (libNVPTXInstPrinter is empty) as a side-effect.

llvm-svn: 187798
2013-08-06 14:13:27 +00:00
Tim Northover cc2e903bda ARM: implement allowTruncateForTailCall
Now that it's in place, it seems silly not to let ARM make use of the extra
tail call opportunities.

llvm-svn: 187795
2013-08-06 13:58:03 +00:00
Alexey Samsonov 3211e61b6d Store compile unit corresponding to each chain of inlined debug info entries. No functionality change.
llvm-svn: 187792
2013-08-06 10:49:15 +00:00
Alexey Samsonov c2e008734b Add LLVM-style RTTI to DIContext/DWARFContext classes
llvm-svn: 187790
2013-08-06 10:32:39 +00:00
Tim Northover a4415854db Refactor isInTailCallPosition handling
This change came about primarily because of two issues in the existing code.
Niether of:

define i64 @test1(i64 %val) {
  %in = trunc i64 %val to i32
  tail call i32 @ret32(i32 returned %in)
  ret i64 %val
}

define i64 @test2(i64 %val) {
  tail call i32 @ret32(i32 returned undef)
  ret i32 42
}

should be tail calls, and the function sameNoopInput is responsible. The main
problem is that it is completely symmetric in the "tail call" and "ret" value,
but in reality different things are allowed on each side.

For these cases:
1. Any truncation should lead to a larger value being generated by "tail call"
   than needed by "ret".
2. Undef should only be allowed as a source for ret, not as a result of the
   call.

Along the way I noticed that a mismatch between what this function treats as a
valid truncation and what the backends see can lead to invalid calls as well
(see x86-32 test case).

This patch refactors the code so that instead of being based primarily on
values which it recurses into when necessary, it starts by inspecting the type
and considers each fundamental slot that the backend will see in turn. For
example, given a pathological function that returned {{}, {{}, i32, {}}, i32}
we would consider each "real" i32 in turn, and ask if it passes through
unchanged. This is much closer to what the backend sees as a result of
ComputeValueVTs.

Aside from the bug fixes, this eliminates the recursion that's going on and, I
believe, makes the bulk of the code significantly easier to understand. The
trade-off is the nasty iterators needed to find the real types inside a
returned value.

llvm-svn: 187787
2013-08-06 09:12:35 +00:00
Serge Pavlov 71044cbe16 Unbreak Debug build on Windows
llvm-svn: 187786
2013-08-06 08:44:18 +00:00
Craig Topper cf969eadaf Simplify vector lane handling math a bit. No functional change intended.
llvm-svn: 187783
2013-08-06 07:23:12 +00:00
Craig Topper 7418ff460c Simplify math a little bit.
llvm-svn: 187781
2013-08-06 06:54:25 +00:00
NAKAMURA Takumi aaf66c7357 Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.

llvm-svn: 187780
2013-08-06 06:38:37 +00:00
Craig Topper 9bc00b65b6 Replace EVT with MVT in isHorizontalBinOp as it is only called with legal types.
llvm-svn: 187779
2013-08-06 06:05:05 +00:00
NAKAMURA Takumi e359e85649 AsmPrinter/CMakeLists.txt: Add explicit dependency to intrinsics_gen here.
llvm-svn: 187778
2013-08-06 05:56:39 +00:00
NAKAMURA Takumi 752f1ec651 Option/CMakeLists.txt: Don't use target_link_libraries. LLVMBuild knows dependencies.
llvm-svn: 187777
2013-08-06 05:56:32 +00:00
Craig Topper 47d7c5c8fe Simplify code slightly. No functional change.
llvm-svn: 187771
2013-08-06 04:12:40 +00:00
Tom Stellard aa664d9b92 Factor FlattenCFG out from SimplifyCFG
Patch by: Mei Ye

llvm-svn: 187764
2013-08-06 02:43:45 +00:00
Eric Christopher f7d848d0b9 Allow 4 as a valid debug info version.
llvm-svn: 187763
2013-08-06 01:38:27 +00:00
Matt Arsenault ff7dc7248e Fix missing -*- C++ -*-s
llvm-svn: 187758
2013-08-06 00:16:21 +00:00
Eric Christopher 0062f2edc0 Recommit previous cleanup with a fix for c++98 ambiguity.
llvm-svn: 187752
2013-08-05 22:32:28 +00:00
Tom Stellard 28d06de6f6 R600: Implement TargetLowering::getVectorIdxTy()
We use MVT::i32 for the vector index type, because we use 32-bit
operations to caculate offsets when dynamically indexing vectors.

llvm-svn: 187749
2013-08-05 22:22:07 +00:00
Tom Stellard d42c594960 TargetLowering: Add getVectorIdxTy() function v2
This virtual function can be implemented by targets to specify the type
to use for the index operand of INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT,
INSERT_SUBVECTOR, EXTRACT_SUBVECTOR.  The default implementation returns
the result from TargetLowering::getPointerTy()

The previous code was using TargetLowering::getPointerTy() for vector
indices, because this is guaranteed to be legal on all targets.  However,
using TargetLowering::getPointerTy() can be a problem for targets with
pointer sizes that differ across address spaces.  On such targets,
when vectors need to be loaded or stored to an address space other than the
default 'zero' address space (which is the address space assumed by
TargetLowering::getPointerTy()), having an index that
is a different size than the pointer can lead to inefficient
pointer calculations, (e.g. 64-bit adds for a 32-bit address space).

There is no intended functionality change with this patch.

llvm-svn: 187748
2013-08-05 22:22:01 +00:00
Eric Christopher 432c99af0b Revert "Use existing builtin hashing functions to make this routine more"
This reverts commit r187745.

llvm-svn: 187747
2013-08-05 22:07:30 +00:00
Eric Christopher d728355a1c Use existing builtin hashing functions to make this routine more
simple.

llvm-svn: 187745
2013-08-05 22:00:50 +00:00
Eric Christopher 0369ad7053 Change parent hashing algorithm to be non-recursive and elaborate
greatly on many comments in the code.

llvm-svn: 187742
2013-08-05 21:40:57 +00:00
Peter Collingbourne bace606657 Introduce an optimisation for special case lists with large numbers of literal entries.
Our internal regex implementation does not cope with large numbers
of anchors very efficiently.  Given a ~3600-entry special case list,
regex compilation can take on the order of seconds.  This patch solves
the problem for the special case of patterns matching literal global
names (i.e. patterns with no regex metacharacters).  Rather than
forming regexes from literal global name patterns, add them to
a StringSet which is checked before matching against the regex.
This reduces regex compilation time by an order of roughly thousands
when reading the aforementioned special case list, according to a
completely unscientific study.

No test cases.  I figure that any new tests for this code should
check that regex metacharacters are properly recognised.  However,
I could not find any documentation which documents the fact that the
syntax of global names in special case lists is based on regexes.
The extent to which regex syntax is supported in special case lists
should probably be decided on/documented before writing tests.

Differential Revision: http://llvm-reviews.chandlerc.com/D1150

llvm-svn: 187732
2013-08-05 17:48:04 +00:00
Peter Collingbourne fe8cd75971 Introduce Regex::isLiteralERE function.
This will be used to implement an optimisation for literal entries
in special case lists.

Differential Revision: http://llvm-reviews.chandlerc.com/D1278

llvm-svn: 187731
2013-08-05 17:47:59 +00:00
Aaron Ballman 5b4634576e Silencing an MSVC11 type conversion warning.
llvm-svn: 187727
2013-08-05 13:47:03 +00:00
Alexey Samsonov f52b717db3 80-cols
llvm-svn: 187725
2013-08-05 13:19:49 +00:00
Elena Demikhovsky 62d19c8bdf LLVM Interpreter: This patch implements vector support for cast operations (zext, sext, uitofp, sitofp, trunc, fpext, fptosi, fptrunc, bitcast) and shift operations (shl, ashr, lshr) for integer and floating point data types.
Added tests.

Done by Yuri Veselov (mailto:Yuri.Veselov@intel.com).

llvm-svn: 187724
2013-08-05 12:17:06 +00:00
Richard Sandiford c212125d27 [SystemZ] Use BRCT and BRCTG to eliminate add-&-compare sequences
This patch just uses a peephole test for "add; compare; branch" sequences
within a single block.  The IR optimizers already convert loops to
decrement-and-branch-on-nonzero form in some cases, so even this
simplistic test triggers many times during a clang bootstrap and
projects/test-suite run.  It looks like there are still cases where we
need to more strongly prefer branches on nonzero though.  E.g. I saw a
case where a loop that started out with a check for 0 ended up with a
check for -1.  I'll try to look at that sometime.

I ended up adding the Reference class because MachineInstr::readsRegister()
doesn't check for subregisters (by design, as far as I could tell).

llvm-svn: 187723
2013-08-05 11:23:46 +00:00
Benjamin Kramer 483b9fbddb Don't leak passes if added outside of the area determined by Started/Stopped flags.
llvm-svn: 187722
2013-08-05 11:11:11 +00:00
Richard Sandiford 9795d8e611 [SystemZ] Add definitions for BRCT and BRCTG
llvm-svn: 187721
2013-08-05 11:07:38 +00:00
Richard Sandiford b49a3ab262 [SystemZ] Use LOAD AND TEST to eliminate comparisons against zero
llvm-svn: 187720
2013-08-05 11:03:20 +00:00
Richard Sandiford c62c64a038 [SystemZ] Add LOAD AND TEST instructions
Just the definitions and MC support.  The next patch uses them for codegen.

llvm-svn: 187719
2013-08-05 11:00:53 +00:00
Richard Sandiford bdbb8af7e6 [SystemZ] Split out comparison elimination into a separate pass
Perhaps predictably, doing comparison elimination on the fly during
SystemZLongBranch turned out to be a bad idea.  The next patches make
use of LOAD AND TEST and BRANCH ON COUNT, both of which require
changes to earlier instructions.

No functionality change intended.

llvm-svn: 187718
2013-08-05 10:58:53 +00:00
Elena Demikhovsky 40864b690b AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types.
Added intrinsics and tests.

llvm-svn: 187717
2013-08-05 08:52:21 +00:00
Reed Kotler 9c285b300d Add the saving of S2. This is needed for some of the floating point
helper functions. This can be optimized out later when the remaining
parts of the helper function work is moved into the Mips16HardFloat pass.
For now it forces us to use the 32 bit save/restore instructions instead
of the 16 bit ones.

llvm-svn: 187712
2013-08-04 23:56:53 +00:00