416886793f
[mips][microMIPS] Implement movep instruction
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Differential Revision: http://reviews.llvm.org/D7465
llvm-svn: 228703
2015-02-10 16:36:20 +00:00
e76eb41c21
[mips][microMIPS] Add disassembler tests for 16-bit instructions BREAK16 and SDBBP16
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Differential Revision: http://reviews.llvm.org/D7443
llvm-svn: 228687
2015-02-10 13:20:51 +00:00
d68d424abf
[mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16
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Differential Revision: http://reviews.llvm.org/D7436
llvm-svn: 228683
2015-02-10 12:41:13 +00:00
e10a02ecf0
[mips][microMIPS] Implement LWGP instruction
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Differential Revision: http://reviews.llvm.org/D6650
llvm-svn: 227325
2015-01-28 17:27:26 +00:00
5cfebdde2b
[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B
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Implement microMIPS 16-bit unconditional branch instruction B.
Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1
Differential Revision: http://reviews.llvm.org/D3514
llvm-svn: 226657
2015-01-21 12:39:30 +00:00
2c6d73207e
[mips][microMIPS] Implement ADDIUPC instruction
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Differential Revision: http://reviews.llvm.org/D6582
llvm-svn: 226656
2015-01-21 12:10:11 +00:00
0d49117769
Reverted revision 226577.
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llvm-svn: 226595
2015-01-20 19:29:28 +00:00
45f7f9c1ab
[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B
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Implement microMIPS 16-bit unconditional branch instruction B.
Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1
Differential Revision: http://reviews.llvm.org/D3514
llvm-svn: 226577
2015-01-20 16:45:27 +00:00
9761e96b01
[mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions
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Differential Revision: http://reviews.llvm.org/D5271
llvm-svn: 225627
2015-01-12 12:03:34 +00:00
ab6d1cce3e
[mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions
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Differential Revision: http://reviews.llvm.org/D5204
llvm-svn: 224785
2014-12-23 19:55:34 +00:00
12c6982b3b
[mips][microMIPS] Implement LWSP and SWSP instructions
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Differential Revision: http://reviews.llvm.org/D6416
llvm-svn: 224771
2014-12-23 16:16:33 +00:00
2deca34803
[mips][microMIPS] Implement SWP and LWP instructions
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Differential Revision: http://reviews.llvm.org/D5667
llvm-svn: 224338
2014-12-16 14:59:10 +00:00
b682ddf33a
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.
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llvm-svn: 223006
2014-12-01 11:12:04 +00:00
c7e220f6e0
[mips][microMIPS] Implement NOP aliases
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This patch implements microMIPS 16-bit (MOVE16 $0, $0) and
32-bit (SLL $0, $0, 0) NOP aliases.
http://reviews.llvm.org/D6440
llvm-svn: 222953
2014-11-29 13:29:24 +00:00
aa2b9278fe
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5
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Differential Revision: http://reviews.llvm.org/D6419
llvm-svn: 222887
2014-11-27 14:41:44 +00:00
315e7eca1b
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16
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Differential Revision: http://reviews.llvm.org/D6405
llvm-svn: 222847
2014-11-26 18:56:38 +00:00
ea22c4cfbb
[mips][microMIPS] Implement disassembler support for 16-bit instructions
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With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.
Differential Revision: http://reviews.llvm.org/D6149
llvm-svn: 222648
2014-11-24 13:29:59 +00:00
a4c4b5fc01
[mips][micromips] Implement SWM32 and LWM32 instructions
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Differential Revision: http://reviews.llvm.org/D5519
llvm-svn: 222367
2014-11-19 16:44:02 +00:00
55bb542856
[mips][microMIPS] Add disassembler tests for new microMIPS 32-bit
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instructions: LWXS, BGEZALS, BLTZALS, BEQZC, BNEZC, JALS and JALRS.
http://reviews.llvm.org/D5413
llvm-svn: 222349
2014-11-19 11:49:57 +00:00
7d63392da9
LL and SC decoder method fix.
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llvm-svn: 199316
2014-01-15 13:17:33 +00:00
d4cb61cf0e
Added support for LWU microMIPS instruction.
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llvm-svn: 199315
2014-01-15 13:01:18 +00:00
ccb70caa13
Support for microMIPS trap instruction with immediate operands.
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llvm-svn: 194569
2013-11-13 13:15:03 +00:00
c18b6d1083
Support for microMIPS trap instructions 1.
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llvm-svn: 194205
2013-11-07 14:35:24 +00:00
8a80aa76c8
Support for microMIPS branch instructions.
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llvm-svn: 193992
2013-11-04 14:53:22 +00:00
507e084a18
Support for microMIPS jump instructions
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llvm-svn: 193623
2013-10-29 16:38:59 +00:00
fc26cfcde7
Fixed bug when generating Load Upper Immediate microMIPS instruction.
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llvm-svn: 190746
2013-09-14 07:35:41 +00:00
3671a5441a
Support for microMIPS DIV instructions.
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llvm-svn: 190745
2013-09-14 07:15:21 +00:00
ab85278137
Support for misc microMIPS instructions.
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llvm-svn: 190744
2013-09-14 06:49:25 +00:00
b936da159e
This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
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llvm-svn: 190154
2013-09-06 13:08:00 +00:00
457ba56b05
This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
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llvm-svn: 190152
2013-09-06 12:53:21 +00:00
e0fbb44a48
This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
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llvm-svn: 190148
2013-09-06 12:41:17 +00:00
dde3d582a2
This patch adds support for microMIPS disassembler and disassembler make check tests.
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llvm-svn: 190144
2013-09-06 12:30:36 +00:00
Zoran Jovanovic