Commit Graph

36 Commits

Author SHA1 Message Date
Chris Lattner 03a102bff3 Generalize a previous change, fixing PR8855 - an valid large immediate
rejected by the mc assembler.

llvm-svn: 122557
2010-12-25 21:36:35 +00:00
Kevin Enderby 87bc591fc5 Allow a slash, '/', as a prefix separator for X86. rdar://8741045
llvm-svn: 121320
2010-12-08 23:57:59 +00:00
Chris Lattner 7e8a99b1c3 fix PR8686, accepting a 'b' suffix at the end of all the setcc
instructions.  I choose to handle this with an asmparser hack,
though it could be handled by changing all the instruction definitions
to allow be "setneb" instead of "setne".  The asm parser hack is
better in this case, because we want the disassembler to produce
setne, not setneb.

llvm-svn: 120260
2010-11-28 20:23:50 +00:00
Rafael Espindola eab0800695 Implement the data16 prefix.
llvm-svn: 120224
2010-11-27 20:29:45 +00:00
Rafael Espindola af9a7a3e92 Testcase for r120017.
llvm-svn: 120099
2010-11-24 18:03:57 +00:00
Chris Lattner b4cd1819fa implement PR8524, apparently mainline gas accepts movq as an alias for movd
when transfering between i64 gprs and mmx regs.

llvm-svn: 119931
2010-11-21 08:18:57 +00:00
Chris Lattner 87cf7f787e accept lret as an alias for lretl, fixing the reopened part of PR8592
llvm-svn: 118916
2010-11-12 18:54:56 +00:00
Chris Lattner 5b013b102d implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.
llvm-svn: 118903
2010-11-12 17:41:20 +00:00
Chris Lattner 0530c024b6 implement aliases for div/idiv that have an explicit A register operand,
implementing rdar://8431864

llvm-svn: 118364
2010-11-06 22:41:18 +00:00
Chris Lattner 9654e108d7 add aliases for movs between seg registers and mem. There are multiple
different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous.  Since they all do the same thing, gas just picks the
one with the shortest encoding.  Follow its lead here.

This implements rdar://8208615

llvm-svn: 118362
2010-11-06 22:35:34 +00:00
Chris Lattner ca7801e472 go to great lengths to work around a GAS bug my previous patch
exposed:

GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.

Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).

As such, switch the canonical form of this instruction to "pi" instead
of "ip".  This makes the code generator and disassembler generate pi,
avoiding the gas bug.

llvm-svn: 118356
2010-11-06 21:37:06 +00:00
Chris Lattner 64f91b9825 rework the rotate-by-1 instructions to be defined like the
shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1.  It turns out that a bunch of these rotate
instructions were completely broken because they used 1 
instead of $1.

This fixes assembly mismatches on "rclb	$1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.

llvm-svn: 118355
2010-11-06 21:23:40 +00:00
Chris Lattner 05031e7f1a change the fp comparison instructions to not have %st0 explicitly
listed in its asm string, for consistency with the other similar
instructions.

llvm-svn: 118354
2010-11-06 20:55:09 +00:00
Chris Lattner fab9413b01 correct suffix matching to search for s/l/t suffixes on
floating point stack instructions instead of looking for b/w/l/q.

This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.

This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp	(%rax)

it also causes us to correctly reject fistp and fist, which addresses
PR8528:

t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^

Thanks to Ismail Donmez for tracking down the issue here!

llvm-svn: 118346
2010-11-06 18:28:02 +00:00
Chris Lattner 1acd6b1edc "mov[zs]x (mem), GR16" are not ambiguous: the mem
must be 8 bits.  Support this memory form.

llvm-svn: 117902
2010-11-01 05:41:10 +00:00
Chris Lattner dd3b09c234 Implement enough of the missing instalias support to get
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
2010-11-01 05:34:34 +00:00
Chris Lattner 178f4bb62d make the asm matcher emitter reject instructions that have comments
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
2010-11-01 04:44:29 +00:00
Chris Lattner 4d9f157203 fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
for shl.  Caught by inspection.

llvm-svn: 117820
2010-10-30 18:13:10 +00:00
Chris Lattner e490b5c29e add a test for the ud2a alias.
llvm-svn: 117803
2010-10-30 17:01:25 +00:00
Kevin Enderby 5e7cb5fc27 Added the x86 instruction ud2b (2nd official undefined instruction).
llvm-svn: 117485
2010-10-27 20:46:49 +00:00
Kevin Enderby 9ad2166899 Yet another tweak to X86 instructions to add ud2a as an alias to ud2
(still to add ud2b).

llvm-svn: 117435
2010-10-27 03:01:02 +00:00
Kevin Enderby 20b021c970 Another tweak to X86 instructions to add the missing flex instruction (without
the wait prefix).

llvm-svn: 117434
2010-10-27 02:53:04 +00:00
Kevin Enderby a1917c7555 Tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
2010-10-27 02:32:19 +00:00
Kevin Enderby ba985d9dd5 Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
2010-10-27 00:59:28 +00:00
Andrew Trick edd006c1c3 Reverting r117031 to cleanup valgrind errors.
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.

llvm-svn: 117087
2010-10-22 03:58:29 +00:00
Kevin Enderby 0138a05557 More tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).

llvm-svn: 117031
2010-10-21 17:16:46 +00:00
Kevin Enderby 49843c0162 Added a few tweaks to the Intel Descriptor-table support instructions to allow
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .

llvm-svn: 116773
2010-10-19 00:01:44 +00:00
Kevin Enderby b9783dd9bc Added a handful of x86-32 instructions that were missing so that llvm-mc would
be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.

llvm-svn: 116716
2010-10-18 17:04:36 +00:00
Chris Lattner 13111b08fb Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
gross hack (having the asmmatcher handle the alias).

llvm-svn: 115685
2010-10-05 21:09:45 +00:00
Eli Friedman bb48e26732 Add 3DNowA instructions.
llvm-svn: 115477
2010-10-03 20:23:13 +00:00
Chris Lattner d3593c3a8e the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
llvm-svn: 115473
2010-10-03 19:09:13 +00:00
Chris Lattner b44b202d66 add support for the prefetch/prefetchw instructions, move femms into
the right file.  The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.

llvm-svn: 115468
2010-10-03 18:42:30 +00:00
Chris Lattner 3a0a620c2e what the heck, add support for the rest of the 3dNow! binary operations.
llvm-svn: 115467
2010-10-03 18:24:18 +00:00
Chris Lattner 45270db916 Implement support for the bizarre 3DNow! encoding (which is unlike anything
else in X86), and add support for pavgusb.  This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.

If someone else is interested in banging out the rest of the 3DNow! 
instructions, it should be quite easy now.

llvm-svn: 115466
2010-10-03 18:08:05 +00:00
Chris Lattner 4756bbeba0 fix a regression introduced in r115243, in which the instruction
backing int_x86_ssse3_pshuf_w got removed.  This caused PR8280.

llvm-svn: 115422
2010-10-02 21:32:15 +00:00
Chris Lattner 4ca7bb52d0 move X86 subdir up a level
llvm-svn: 115292
2010-10-01 04:32:20 +00:00