8a37bbebfd
Add support for ARM Neon VREV instructions.
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Patch by Anton Korzh, with some modifications from me.
llvm-svn: 77101
2009-07-26 00:39:34 +00:00
2de9510572
add the most expedient hack to fix PR4619, along with a testcase.
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Thanks to Rafael for the great example.
llvm-svn: 77083
2009-07-25 17:57:37 +00:00
534d66a426
When attempting to sign-extend an addrec by interpreting
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the step value as unsigned, the start value and the addrec
itself still need to be treated as signed.
llvm-svn: 77078
2009-07-25 16:03:30 +00:00
fcfbc7bb2c
remove this test. It is currently failing because we now emit the string
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on darwin with ".cstring" instead of ".section __TEXT,__cstring". They
are the same and the former is better. Remove this because this is no longer
magic pixie dust in the frontend.
llvm-svn: 77055
2009-07-25 07:31:51 +00:00
62ef6a7f1c
Teach ScalarEvolution to make use of no-overflow flags when
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analyzing add recurrences.
llvm-svn: 77034
2009-07-25 01:22:26 +00:00
3b5791f982
I've lost my mind. PR4572 has not been fixed.
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llvm-svn: 77031
2009-07-25 01:11:46 +00:00
f3a1fce8ae
Change Thumb2 jumptable codegen to one that uses two level jumps:
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Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2 ]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
2009-07-25 00:33:29 +00:00
8c8e88bd39
Remove a duplicated test.
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llvm-svn: 77020
2009-07-25 00:24:40 +00:00
01740ab57b
Forgot this test earlier.
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llvm-svn: 77007
2009-07-24 22:42:45 +00:00
aee0e1f48c
Fix these tests.
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llvm-svn: 77006
2009-07-24 22:42:22 +00:00
5c9cdb3e3a
Fix assert assembling zero-argument constant GEP.
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There's still a strict-aliasing violation here, but I don't feel like
dealing with that right now...
llvm-svn: 77005
2009-07-24 21:56:17 +00:00
fae639c9ad
Move insertps tests to sse41 combo test file, convert to filecheck
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format and add an extract/insert test.
llvm-svn: 76994
2009-07-24 19:24:26 +00:00
3990850a7d
Convert a test to FileCheck.
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llvm-svn: 76954
2009-07-24 06:01:46 +00:00
26aff56462
Remove SectionKind::Small*. This was only used on mips, and is apparently
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a sad mistake that is regretted. :)
llvm-svn: 76935
2009-07-24 03:11:51 +00:00
fc39e417a8
Add tests for handling of globals and tls on the XCore. These currently fail
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but pass when run against r76652.
llvm-svn: 76923
2009-07-24 00:38:20 +00:00
17151155ed
Remove the IA-64 backend.
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llvm-svn: 76920
2009-07-24 00:30:09 +00:00
dc99f07113
Thumb2 does not allow the use of "pc" register as part of the load / store address.
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llvm-svn: 76909
2009-07-23 23:09:51 +00:00
d2919a1773
Fix up ARM constant island pass for Thumb2.
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Also fixed up code to fully use the SoImm field for ADR on ARM mode.
llvm-svn: 76890
2009-07-23 18:27:47 +00:00
dcb9f483bf
FileCheck'ize and expand LDA testcases.
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llvm-svn: 76880
2009-07-23 15:56:53 +00:00
7413f07b9d
testcase for PR4590
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llvm-svn: 76868
2009-07-23 06:07:59 +00:00
7152d39d6d
merge vector-casts-0.ll into vector-casts.ll
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llvm-svn: 76864
2009-07-23 05:33:39 +00:00
7d55541e56
Make some existing optimizations that would only trigger on scalars
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also apply to vectors. This allows us to compile this:
#include <emmintrin.h>
__m128i a(__m128 a, __m128 b) { return a==a & b==b; }
__m128i b(__m128 a, __m128 b) { return a!=a | b!=b; }
to:
_a:
cmpordps %xmm1, %xmm0
ret
_b:
cmpunordps %xmm1, %xmm0
ret
with clang instead of to a ton of horrible code.
llvm-svn: 76863
2009-07-23 05:32:17 +00:00
b4ff7de8bd
convert a test to filecheck format. This fixes an endemic problem
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with negative tests: this test wasn't checking what it thought it was
because it was grepping .bc, not .ll.
llvm-svn: 76861
2009-07-23 05:27:48 +00:00
4a3affbdcf
rename test
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llvm-svn: 76860
2009-07-23 05:25:12 +00:00
dc13b7c637
merge one more sse41 test into sse41.ll
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llvm-svn: 76853
2009-07-23 04:49:39 +00:00
70d5783535
merge another sse41 test into sse41.ll
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llvm-svn: 76852
2009-07-23 04:43:48 +00:00
08fc6e6e40
merge sse41-pmovx.ll into sse41.ll
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llvm-svn: 76850
2009-07-23 04:39:09 +00:00
b9cdd3153c
change a test to run in filecheck style. Rename it to be a general
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dumping ground of various SSE4.1 tests, since filecheck can reasonably
handle them all in one file. Generalize it to check x86-64 stuff as
well since it has a different ABI (a convenient way to test both the
reg and mem forms of these instructions).
llvm-svn: 76848
2009-07-23 04:33:02 +00:00
b1b77ca862
Support insertps via the intrinsic and add a couple of simple
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testcases to make sure it's being generated.
llvm-svn: 76843
2009-07-23 02:22:41 +00:00
327cb795a1
Add test for pinsrd and pinsrb instructions.
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llvm-svn: 76840
2009-07-23 01:58:04 +00:00
e059ba6ed2
Derive MDNode from MetadataBase instead of Constant. Emit MDNodes into METADATA_BLOCK in bitcode file.
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llvm-svn: 76834
2009-07-23 01:07:34 +00:00
b215100c7c
Revert r75663 (and r76805), as it is causing regressions on powerpc.
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llvm-svn: 76823
2009-07-23 00:09:46 +00:00
824ab40381
x86 isel tweak: use lea (%reg,%reg) instead of lea (,%reg,2).
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llvm-svn: 76817
2009-07-22 23:26:55 +00:00
902dfff8b6
Rename the new unsigned and signed keywords to nuw and nsw,
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which stand for no-unsigned-wrap and no-signed-wrap.
llvm-svn: 76810
2009-07-22 22:44:56 +00:00
cdbef5f2c0
Add -march=ppc32 lines so that this test doesn't ever default to ppc64.
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llvm-svn: 76805
2009-07-22 22:08:31 +00:00
e270d4a4dd
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
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llvm-svn: 76803
2009-07-22 22:03:29 +00:00
c510293251
Make the grep line in this test more specific, to avoid
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unintended matches.
llvm-svn: 76802
2009-07-22 22:02:42 +00:00
d2d52d1906
Ignore undef uses.
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llvm-svn: 76799
2009-07-22 21:51:42 +00:00
75bec765c3
Remove empty test.
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llvm-svn: 76763
2009-07-22 18:09:11 +00:00
7428d8acec
Introduce MetadataBase, a base class for MDString and MDNode.
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Derive MDString directly from MetadataBase.
Introduce new bitcode block to hold metadata.
llvm-svn: 76759
2009-07-22 17:43:22 +00:00
0cf7f5d6d2
Revert commit 76707, it was breaking the llvm-gcc build
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on linux platforms. The binutils assembler does not
recognize the "s" flag, see for example
http://sourceware.org/binutils/docs/as/Section.html
llvm-svn: 76733
2009-07-22 10:35:05 +00:00
8ebaec6b27
set the ELF "small" flag on objects that end up in .rodata.cst4 consistently,
...
updating a mips testcase to expect it.
llvm-svn: 76707
2009-07-22 00:41:56 +00:00
430f0cc544
Replace the original ad-hoc code for determining whether (v pred w) implies
...
(x pred y) with more thorough code that does more complete canonicalization
before resorting to range checks. This helps it find more cases where
the canonicalized expressions match.
llvm-svn: 76671
2009-07-21 23:03:19 +00:00
332a6590ae
Remove a big test case.
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llvm-svn: 76669
2009-07-21 22:52:04 +00:00
e3228acc62
Fix ocaml tests for 64-bit MacOS systems. LLVM is currently built
...
as 32-bit code by default, and if gcc defaults to 64-bit code then ocamlc
requires a -cc "gcc -arch i386" option. We were hardcoding -cc g++
and throwing away any other compiler options that were determined when
ocamlc was configured and built.
llvm-svn: 76658
2009-07-21 21:56:46 +00:00
38e88cb53f
Do not select tSXTB / tSXTH in thumb2 mode.
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llvm-svn: 76600
2009-07-21 18:15:26 +00:00
8e55200089
convert this test to filecheck format, which is faster and avoids false matches of "st" -> "stdin"
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llvm-svn: 76591
2009-07-21 17:36:24 +00:00
b61f9c8c8d
add a testcase for the pic16 section handling stuff.
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llvm-svn: 76579
2009-07-21 16:48:20 +00:00
07a6ac6b29
Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.
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llvm-svn: 76558
2009-07-21 09:15:00 +00:00
83423aa276
remove a very large testcase for now.
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llvm-svn: 76537
2009-07-21 06:28:36 +00:00
Bob Wilson