Commit Graph

20 Commits

Author SHA1 Message Date
Daniel Dunbar 0dd5e1ed39 More migration to raw_ostream, the water has dried up around the iostream hole.
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.

llvm-svn: 77019
2009-07-25 00:23:56 +00:00
Evan Cheng 4dc848f3e8 Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it.
This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround.

llvm-svn: 76703
2009-07-22 00:25:27 +00:00
Evan Cheng 07a6ac6b29 Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.
llvm-svn: 76558
2009-07-21 09:15:00 +00:00
Evan Cheng e20cbf3068 Enable cross register class coalescing.
llvm-svn: 76281
2009-07-18 02:10:10 +00:00
Evan Cheng 76b561dd70 Fix my brain cramp by inverting the assertion condition.
llvm-svn: 76131
2009-07-17 00:32:06 +00:00
Daniel Dunbar f60abdbb5a Disable this assert for now, it is firing on an llvm-gcc bootstrap. :(
llvm-svn: 76123
2009-07-16 23:02:46 +00:00
Daniel Dunbar 87b85dd4dc Fix inverted preprocessor conditional.
llvm-svn: 76111
2009-07-16 22:08:25 +00:00
Evan Cheng 357645efad Changed my mind. We now allow remat of instructions whose defs have subreg indices.
llvm-svn: 76100
2009-07-16 20:15:00 +00:00
Evan Cheng 84517443ca Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

llvm-svn: 75900
2009-07-16 09:20:10 +00:00
Torok Edwin fbcc663cbf llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
2009-07-14 16:55:14 +00:00
Torok Edwin 56d0659726 assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379
2009-07-11 20:10:48 +00:00
Evan Cheng f075943584 Remove TargetInstrInfo::CommuteChangesDestination and added findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements.
llvm-svn: 75264
2009-07-10 19:15:51 +00:00
Evan Cheng d379e896ff Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
llvm-svn: 74580
2009-07-01 01:59:31 +00:00
Evan Cheng 0dc101b897 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518
2009-06-30 08:49:04 +00:00
Lang Hames 1a65f61137 Removed SimpleRewriter.
llvm-svn: 72880
2009-06-04 18:45:36 +00:00
Evan Cheng b39a6be77a Fix for PR4225: When rewriter reuse a value in a physical register , it clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well.
llvm-svn: 72758
2009-06-03 09:00:27 +00:00
Lang Hames fc968ef687 Update to in-place spilling framework. Includes live interval scaling and trivial rewriter.
llvm-svn: 72729
2009-06-02 16:53:25 +00:00
Evan Cheng e23c109a67 Fix PR4210. Rewritter should track and update kills of sub-registers as well.
llvm-svn: 71848
2009-05-15 06:48:19 +00:00
Evan Cheng df1aeeeb90 Teach TransferDeadness to delete truly dead instructions if they do not produce side effects.
llvm-svn: 71606
2009-05-12 23:07:00 +00:00
Lang Hames ab68cf24bb Renamed Spiller classes (plus uses and related files) to VirtRegRewriter.
llvm-svn: 71057
2009-05-06 02:36:21 +00:00