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Author SHA1 Message Date
Reid Spencer cd99fbdf3b Make more uses of getHighBitsSet and get rid of some pointless & of an 
APInt with its type mask.

llvm-svn: 35325
 2007-03-25 04:26:16 +00:00
Chris Lattner 843e44503c Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll 
llvm-svn: 35324
 2007-03-25 02:18:14 +00:00
Chris Lattner d685514e2e switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.

llvm-svn: 35322
 2007-03-25 02:14:49 +00:00
Reid Spencer d8aad61d4d More APIntification: 
* Convert the last use of a uint64_t that should have been an APInt.
* Change ComputeMaskedBits to have a const reference argument for the Mask
  so that recursions don't cause unneeded temporaries. This causes temps
  to be needed in other places (where the mask has to change) but this
  change optimizes for the recursion which is more frequent.
* Remove two instances of &ing a Mask with getAllOnesValue. Its not
  needed any more because APInt is accurate in its bit computations.
* Start using the getLowBitsSet and getHighBits set methods on APInt
  instead of shifting. This makes it more clear in the code what is
  going on.

llvm-svn: 35321
 2007-03-25 02:03:12 +00:00
Chris Lattner 927f30da08 Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers. 
llvm-svn: 35320
 2007-03-25 02:01:03 +00:00
Chris Lattner 03a643aa69 enforce the proper range for the i386 N constraint. 
llvm-svn: 35319
 2007-03-25 01:57:35 +00:00
Chris Lattner c8ddca703d Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll 
llvm-svn: 35318
 2007-03-25 01:44:57 +00:00
Chris Lattner 3a8248f79d fix a regression on vector or instructions. 
llvm-svn: 35314
 2007-03-24 23:56:43 +00:00
Chris Lattner 2a991268f7 don't rely on ADL 
llvm-svn: 35299
 2007-03-24 17:37:03 +00:00
Chris Lattner 7750e344d3 add a valuetype for v1i64, which is needed by mmx. 
llvm-svn: 35298
 2007-03-24 17:36:26 +00:00
Zhou Sheng e9ebd3f6ba Make some codes more efficient. 
llvm-svn: 35297
 2007-03-24 15:34:37 +00:00
Chris Lattner 43cab75914 add a bad case evan though of. 
llvm-svn: 35296
 2007-03-24 06:01:32 +00:00
Reid Spencer a962d18774 For PR1205: 
Convert some calls to ConstantInt::getZExtValue() into getValue() and
use APInt facilities in the subsequent computations.

llvm-svn: 35294
 2007-03-24 00:42:08 +00:00
Evan Cheng b7051f596a Adjust offset to compensate for big endian machines. 
llvm-svn: 35293
 2007-03-24 00:02:43 +00:00
Anton Korobeynikov 8aae2d7e1c Autodetect MMX & SSE stuff for AMD processors 
llvm-svn: 35292
 2007-03-23 23:46:48 +00:00
Bill Wendling 871c77cda1 PR1260: 
Add final support to get the QT example to compile.

llvm-svn: 35290
 2007-03-23 22:35:46 +00:00
Evan Cheng a883b58caf Make sure SEXTLOAD of the specific type is supported on the target. 
llvm-svn: 35289
 2007-03-23 22:13:36 +00:00
Reid Spencer 959a21d3dc For PR1205: 
* APIntify visitAdd and visitSelectInst
* Remove unused uint64_t versions of utility functions that have been
  replaced with APInt versions.
This completes most of the changes for APIntification of InstCombine. This
passes llvm-test and llvm/test/Transforms/InstCombine/APInt.

Patch by Zhou Sheng.

llvm-svn: 35287
 2007-03-23 21:24:59 +00:00
Evan Cheng e2f5f24e8e Also replace uses of SRL if that's also folded during ReduceLoadWidth(). 
llvm-svn: 35286
 2007-03-23 20:55:21 +00:00
Reid Spencer 6d39206bc2 For PR1205: 
APIntify visitDiv, visitMul and visitRem.

Patch by Zhou Sheng.

llvm-svn: 35283
 2007-03-23 20:05:17 +00:00
Chris Lattner 12b89cc148 switch AddReachableCodeToWorklist from being recursive to being iterative. 
llvm-svn: 35282
 2007-03-23 19:17:18 +00:00
Reid Spencer 6274c72ee1 For PR1205: 
APIntify several utility functions supporting logical operators and shift
operators.

Patch by Zhou Sheng.

llvm-svn: 35281
 2007-03-23 18:46:34 +00:00
Reid Spencer d96dc9020a Fix constant fold of div by zero and rem by zero to match IEEE 754 
requirements. We must return NaN in some cases and correctly signed
infinity in other cases. Passes CFP2006 (not that that says much).

llvm-svn: 35277
 2007-03-23 05:33:23 +00:00
Zhou Sheng 0900993ebc Make the "KnownZero ^ TypeMask" computation just once. 
llvm-svn: 35276
 2007-03-23 03:13:21 +00:00
Zhou Sheng 755f04b5d7 Simplify the code. 
llvm-svn: 35275
 2007-03-23 02:39:25 +00:00
Evan Cheng a824e79f06 A couple of bug fixes for reducing load width xform: 
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.

llvm-svn: 35274
 2007-03-23 02:16:52 +00:00
Reid Spencer b722f2b110 For PR1205: 
APInt support for logical operators in visitAnd, visitOr, and visitXor.

Patch by Zhou Sheng.

llvm-svn: 35273
 2007-03-22 22:19:58 +00:00
Reid Spencer 4154e732e6 For PR1205: 
* APIntify commonIntCastTransforms
* APIntify visitTrunc
* APIntify visitZExt

Patch by Zhou Sheng.

llvm-svn: 35271
 2007-03-22 20:56:53 +00:00
Reid Spencer c3e3b8a32f For PR1205: 
* Re-enable the APInt version of MaskedValueIsZero.
* APIntify the Comput{Un}SignedMinMaxValuesFromKnownBits functions
* APIntify visitICmpInst.

llvm-svn: 35270
 2007-03-22 20:36:03 +00:00
Bill Wendling 7c17fbc5b7 We generate a shufflevector instruction, so we don't need the builtin 
intrinsic.

llvm-svn: 35269
 2007-03-22 20:29:26 +00:00
Bill Wendling d551a18783 Support added for shifts and unpacking MMX instructions. 
llvm-svn: 35266
 2007-03-22 18:42:45 +00:00
Dan Gohman dcb291faa4 Change uses of Function::front to Function::getEntryBlock for readability. 
llvm-svn: 35265
 2007-03-22 16:38:57 +00:00
Reid Spencer 478dcd0239 Add the NoUnwind function attribute. 
llvm-svn: 35260
 2007-03-22 02:14:48 +00:00
Reid Spencer 32096786f1 Regenerate. 
llvm-svn: 35259
 2007-03-22 02:14:08 +00:00
Reid Spencer a483577d21 Add support for the noreturn and nounwind function attributes. 
llvm-svn: 35258
 2007-03-22 02:13:23 +00:00
Nick Lewycky b0da7ed9c8 Fix broken optimization disabled by a logic bug. 
Analyze GEPs. If the indices are all zero, transfer whether the pointer is
known to be not null through the GEP.

Add a few more cases for xor and shift instructions.

llvm-svn: 35257
 2007-03-22 02:02:51 +00:00
Evan Cheng 464dc9b74c More opportunities to reduce load size. 
llvm-svn: 35254
 2007-03-22 01:54:19 +00:00
Evan Cheng a20815e157 Fix for PR1257. Bug in live range shortening as a result of copy coalescing 
where the destination is dead.

llvm-svn: 35252
 2007-03-22 01:26:05 +00:00
Reid Spencer f40711637f For PR1248: 
* Fix some indentation and comments in InsertRangeTest
* Add an "IsSigned" parameter to AddWithOverflow and make it handle signed
  additions. Also, APIntify this function so it works with any bitwidth.
* For the icmp pred ([us]div %X, C1), C2 transforms, exit early if the
  div instruction's RHS is zero.
* Finally, for icmp pred (sdiv %X, C1), -C2, fix an off-by-one error. The
  HiBound needs to be incremented in order to get the range test correct.

llvm-svn: 35247
 2007-03-21 23:19:50 +00:00
Dale Johannesen 0c6bb5eab7 repair x86 performance, dejagnu problems from previous change 
llvm-svn: 35245
 2007-03-21 21:51:52 +00:00
Anton Korobeynikov 4ad4bcdc2d Add TODO list for MSIL backend 
llvm-svn: 35244
 2007-03-21 21:48:59 +00:00
Anton Korobeynikov aa3090d815 Let the new backend begin! 
llvm-svn: 35242
 2007-03-21 21:38:25 +00:00
Dale Johannesen a827d03154 add generation of unnecessary push/pop around calls 
llvm-svn: 35241
 2007-03-21 21:16:39 +00:00
Evan Cheng d63baead9b fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits)) 
llvm-svn: 35239
 2007-03-21 20:14:05 +00:00
Nicolas Geoffray 4ea5217880 Protect R31's frame offset from being used by callee-saved registers, when R31 
is the frame pointer.

llvm-svn: 35233
 2007-03-21 16:44:14 +00:00
Zhou Sheng 0458c1db71 Fix a bug in getAllOnesValue() which broke 
some test cases for bitwidth > 64.

llvm-svn: 35232
 2007-03-21 04:34:37 +00:00
Evan Cheng 61eee86487 Mark re-materializable instructions. 
llvm-svn: 35230
 2007-03-21 00:16:56 +00:00
Evan Cheng cba9538499 Updated. 
llvm-svn: 35229
 2007-03-20 22:32:39 +00:00
Evan Cheng 3578dd61c6 Potential spiller improvement. 
llvm-svn: 35228
 2007-03-20 22:22:38 +00:00
Dale Johannesen bacf4acf65 do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)

llvm-svn: 35227
 2007-03-20 21:54:54 +00:00
Dale Johannesen d05a1a2ade maintain LiveIn when splitting blocks (register scavenging needs it) 
llvm-svn: 35226
 2007-03-20 21:35:06 +00:00
Devang Patel eb5d241d00 DominanceFrontier::calculate(). 
Avoid recursion, Use iterative algorithm.

llvm-svn: 35225
 2007-03-20 21:25:31 +00:00
Jeff Cohen 1baf5c84ab Fix some VC++ warnings. 
llvm-svn: 35224
 2007-03-20 20:43:18 +00:00
Jeff Cohen e06855e684 Fix (and simplify) 48-bit byte swap. 
Get pos/neg infinity the correct way.

llvm-svn: 35223
 2007-03-20 20:42:36 +00:00
Devang Patel 1758cb50de LoopSimplify::FindPHIToPartitionLoops() 
Use ETForest instead of DominatorSet.

llvm-svn: 35221
 2007-03-20 20:18:12 +00:00
Lauro Ramos Venancio 971aa18867 Code clean up. 
llvm-svn: 35220
 2007-03-20 20:09:03 +00:00
Evan Cheng 550cf0369c Minor bug. 
llvm-svn: 35219
 2007-03-20 19:32:11 +00:00
Lauro Ramos Venancio a88c4a74f3 bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Reid Spencer 8d364d0e17 Regenerate. 
llvm-svn: 35215
 2007-03-20 17:19:31 +00:00
Reid Spencer 0ad5cebb09 Don't delete things before their last use (avoids bad reads). 
llvm-svn: 35214
 2007-03-20 17:18:33 +00:00
Lauro Ramos Venancio 25878b45f5 CopyToReg source operand can be a physical register. 
llvm-svn: 35213
 2007-03-20 16:46:44 +00:00
Zhou Sheng b3949340c8 Simplify isHighOnes(). 
llvm-svn: 35211
 2007-03-20 12:49:06 +00:00
Evan Cheng 0e3278e505 First cut trivial re-materialization support. 
llvm-svn: 35208
 2007-03-20 08:13:50 +00:00
Evan Cheng 9e7b838469 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
llvm-svn: 35207
 2007-03-20 08:11:30 +00:00
Evan Cheng 39eb62ea3b New entry. 
llvm-svn: 35206
 2007-03-20 08:10:17 +00:00
Evan Cheng 61f39d186c Added MRegisterInfo hook to re-materialize an instruction. 
llvm-svn: 35205
 2007-03-20 08:09:38 +00:00
Chris Lattner 3e1d917e80 Two changes: 
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204
 2007-03-20 06:08:29 +00:00
Chris Lattner f806e1cdbc fix indentation 
llvm-svn: 35202
 2007-03-20 02:25:53 +00:00
Reid Spencer 6fb989c5cd Regenerate. 
llvm-svn: 35199
 2007-03-20 01:13:36 +00:00
Reid Spencer d05bc52fec Plug some PATypeHolder memory leaks. 
llvm-svn: 35198
 2007-03-20 01:13:00 +00:00
Dale Johannesen e3a02be5f1 use types of loads and stores, not address, in CheckForIVReuse 
llvm-svn: 35197
 2007-03-20 00:47:50 +00:00
Dale Johannesen 8447d34903 fix obvious comment bug 
llvm-svn: 35196
 2007-03-20 00:30:56 +00:00
Chris Lattner af867a3937 Fix a nasty memory leak, caused by my revamp of the value symbol table. 
llvm-svn: 35195
 2007-03-20 00:18:10 +00:00
Reid Spencer 6682721316 Make isOneBitSet faster by using APInt::isPowerOf2. Thanks Chris. 
llvm-svn: 35194
 2007-03-20 00:16:52 +00:00
Reid Spencer cc031a43aa APIntify the isHighOnes utility function. 
llvm-svn: 35190
 2007-03-19 21:29:50 +00:00
Reid Spencer b1ec2e8ec7 Fix coding standards violation. 
llvm-svn: 35189
 2007-03-19 21:19:02 +00:00
Reid Spencer ef599b0786 Implement isMaxValueMinusOne in terms of APInt instead of uint64_t. 
Patch by Sheng Zhou.

llvm-svn: 35188
 2007-03-19 21:10:28 +00:00
Reid Spencer 3b93db72b4 Implement isMinValuePlusOne using facilities of APInt instead of uint64_t 
Patch by Zhou Sheng.

llvm-svn: 35187
 2007-03-19 21:08:07 +00:00
Reid Spencer 129a86792d Implement isOneBitSet in terms of APInt::countPopulation. 
llvm-svn: 35186
 2007-03-19 21:04:43 +00:00
Reid Spencer 450434ed65 1. Use APInt::getSignBit to reduce clutter (patch by Sheng Zhou) 
2. Replace uses of the "isPositive" utility function with APInt::isPositive

llvm-svn: 35185
 2007-03-19 20:58:18 +00:00
Reid Spencer 03c31d5bb0 Remove a redundant clause in an if statement. 
Patch by Sheng Zhou.

llvm-svn: 35184
 2007-03-19 20:47:50 +00:00
Reid Spencer a7bed60ab3 Regenerate. 
llvm-svn: 35183
 2007-03-19 20:40:51 +00:00
Reid Spencer 363fd46199 Fix test/Assembler/2007-03-19-NegValue.ll by using the new "isSigned" 
parameter on ConstantInt::get to indicate the signedness of the intended
value.

llvm-svn: 35182
 2007-03-19 20:40:22 +00:00
Reid Spencer 362fb29d80 Allow ConstantInt::get(Ty, uint64_t) to interpret the 64-bit values as a 
negative number. This is needed to fix test/Assembler/2007-03-19-NegValue.ll

llvm-svn: 35181
 2007-03-19 20:39:08 +00:00
Reid Spencer 6fae35acd3 Implement extension of sign bits for negative values in the uint64_t 
constructor. This helps to fix test/Assembler/2007-03-19-NegValue.ll

llvm-svn: 35180
 2007-03-19 20:37:47 +00:00
Anton Korobeynikov 2946e07557 Fix mingw32 build 
llvm-svn: 35177
 2007-03-19 20:19:08 +00:00
Reid Spencer d0e8d382db Regenerate. 
llvm-svn: 35174
 2007-03-19 18:40:50 +00:00
Reid Spencer fe65ae88fe For PR1248: 
Eliminate support for type planes in numbered values. This simplifies the
data structures involved in managing forward definitions, etc. Instead of
requiring maps from type to value, we can now just use a vector of values.
These changes also required rewrites of some support functions such as
InsertValue, getBBVal, and ResolveDefinitions. Some other cosmetic changes
were made as well.

llvm-svn: 35173
 2007-03-19 18:39:36 +00:00
Reid Spencer 49bd921f08 Add and Operator== method to ValID so equality can be done properly for 
named or numbered ValIDs.

llvm-svn: 35172
 2007-03-19 18:34:28 +00:00
Reid Spencer 508167861d For PR1258: 
Radically simplify the SlotMachine. There is no need to keep Value planes
around any more. This change causes slot numbering to number all un-named,
non-void values starting at 0 and incrementing monotonically through the
function, regardless of type (including BasicBlocks). Getting slot numbers
is now a single lookup operation instead of a double lookup.

llvm-svn: 35171
 2007-03-19 18:32:53 +00:00
Chris Lattner 9c62db7c8c fix ScalarRepl/2007-03-19-CanonicalizeMemcpy.ll 
llvm-svn: 35169
 2007-03-19 18:25:57 +00:00
Evan Cheng 25d00d545d Remove -reduce-joining-phys-regs options. Make it on by default. 
llvm-svn: 35165
 2007-03-19 18:08:26 +00:00
Evan Cheng 9bb01c9f4f Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng ee2763f76f Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
 2007-03-19 07:20:03 +00:00
Evan Cheng 5be3e09a30 Constant generation instructions are re-materializable. 
llvm-svn: 35161
 2007-03-19 07:09:02 +00:00
Evan Cheng 461c964d3d Added isReMaterializable. 
llvm-svn: 35160
 2007-03-19 06:22:07 +00:00
Evan Cheng c5e74f6404 Minor bug fix. 
llvm-svn: 35153
 2007-03-19 04:22:35 +00:00
Chris Lattner f01f87bc63 fix a warning 
llvm-svn: 35152
 2007-03-19 00:39:32 +00:00
Chris Lattner 877a3b424d implement the next chunk of SROA with memset/memcpy's of aggregates. This 
implements Transforms/ScalarRepl/memset-aggregate-byte-leader.ll

llvm-svn: 35150
 2007-03-19 00:16:43 +00:00
Nick Lewycky db204ecfbc Clean up this code and fix subtract miscompile. 
llvm-svn: 35146
 2007-03-18 22:58:46 +00:00
Chris Lattner 0741842b3b Implement InstCombine/and-xor-merge.ll:test[12]. 
Rearrange some code to simplify it now that shifts are binops

llvm-svn: 35145
 2007-03-18 22:51:34 +00:00
Chris Lattner 9b3e2b4ad9 minor updates 
llvm-svn: 35143
 2007-03-18 22:41:33 +00:00
Nick Lewycky f764441977 This is implemented. We now generate: 
entry:
        icmp ugt i32 %x, 4              ; <i1>:0 [#uses=1]
        br i1 %0, label %cond_true, label %cond_false

cond_true:              ; preds = %entry
        %tmp1 = tail call i32 (...)* @bar( i32 12 )             ; <i32> [#uses=0]
        ret void

cond_false:             ; preds = %entry
        switch i32 %x, label %cond_true15 [
                 i32 4, label %cond_true3
                 i32 3, label %cond_true7
                 i32 2, label %cond_true11
                 i32 0, label %cond_false17
        ]

...

llvm-svn: 35142
 2007-03-18 14:37:20 +00:00
Evan Cheng d8f2e4fe4c - Merge UsedBlocks info after two virtual registers are coalesced. 
- Use distance to closest use to determine whether to abort coalescing.

llvm-svn: 35141
 2007-03-18 09:05:55 +00:00
Evan Cheng 5382426577 Keep UsedBlocks info accurate. 
llvm-svn: 35140
 2007-03-18 09:02:31 +00:00
Nick Lewycky 17d20fd41e Propagate ValueRanges across equality. 
Add some more micro-optimizations: x * 0 = 0, a - x = a --> x = 0.

llvm-svn: 35138
 2007-03-18 01:09:32 +00:00
Anton Korobeynikov 22f436da42 Silence warning 
llvm-svn: 35137
 2007-03-17 14:48:06 +00:00
Evan Cheng f6f043332f Track the BB's where each virtual register is used. 
llvm-svn: 35135
 2007-03-17 09:29:54 +00:00
Evan Cheng 7b2a001669 Joining a live interval of a physical register with a virtual one can turn out 
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.

llvm-svn: 35134
 2007-03-17 09:27:35 +00:00
Evan Cheng a2465dfc07 Use SmallSet instead of std::set. 
llvm-svn: 35133
 2007-03-17 08:53:30 +00:00
Evan Cheng be22235790 If sdisel has decided to sink GEP index expression into any BB. Replace all uses 
in that BB.

llvm-svn: 35132
 2007-03-17 08:22:49 +00:00
Devang Patel b38c2ec89c Support 'I' inline asm constraint. 
llvm-svn: 35129
 2007-03-17 00:13:28 +00:00
Lauro Ramos Venancio 25d4052af6 Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.

llvm-svn: 35128
 2007-03-16 22:54:16 +00:00
Evan Cheng c5bc763f50 Turn on GEP index sinking by default. 
llvm-svn: 35127
 2007-03-16 18:32:30 +00:00
Evan Cheng 0a9d0cabaf Stupid bug. 
llvm-svn: 35126
 2007-03-16 17:50:20 +00:00
Bill Wendling 144b8bbf17 And now support for MMX logical operations. 
llvm-svn: 35125
 2007-03-16 09:44:46 +00:00
Evan Cheng 009ea54262 Sink a binary expression into its use blocks if it is a loop invariant 
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

llvm-svn: 35123
 2007-03-16 08:46:27 +00:00
Evan Cheng 0e34d6af6b Added isLegalAddressExpression(). Only allows X +/- C for now. 
llvm-svn: 35122
 2007-03-16 08:43:56 +00:00
Evan Cheng a2a2fd1e55 Added isLegalAddressExpression hook to test if the given expression can be 
folded into target addressing mode for the given type.

llvm-svn: 35121
 2007-03-16 08:42:32 +00:00
Nick Lewycky 4f73de2b4e Add more comments and update to new asm syntax. 
Add new micro-optimizations.

Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.

llvm-svn: 35119
 2007-03-16 02:37:39 +00:00
Bill Wendling e31034125c Multiplication support for MMX. 
llvm-svn: 35118
 2007-03-15 21:24:36 +00:00
Evan Cheng 88de94a4fb Debugging output stuff. 
llvm-svn: 35117
 2007-03-15 21:19:28 +00:00
Evan Cheng b9e3db67fb Estimate a cost using the possible number of scratch registers required and use 
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.

llvm-svn: 35109
 2007-03-14 22:43:40 +00:00
Evan Cheng a1779b9739 Under X86-64 large code model, do not emit 32-bit pc relative calls. 
llvm-svn: 35108
 2007-03-14 22:11:11 +00:00
Evan Cheng 71face25ef Notes about codegen issues. 
llvm-svn: 35107
 2007-03-14 21:03:53 +00:00
Evan Cheng e278f30a52 Clean up. 
llvm-svn: 35105
 2007-03-14 20:20:19 +00:00
Evan Cheng eb76f7c6fd Oops. 
llvm-svn: 35104
 2007-03-14 19:44:58 +00:00
Evan Cheng dda4c32db3 X86-64 JIT is in large code model. Need stubs for direct calls. 
llvm-svn: 35097
 2007-03-14 10:51:55 +00:00
Evan Cheng 386dfc9251 x86-64 JIT stub codegen. 
llvm-svn: 35096
 2007-03-14 10:48:08 +00:00
Evan Cheng e1a95206e3 Preliminary support for X86-64 JIT stub codegen. 
llvm-svn: 35095
 2007-03-14 10:44:30 +00:00
Zhou Sheng d8c645b0ba ShiftAmt might equal to zero. Handle this situation. 
llvm-svn: 35094
 2007-03-14 09:07:33 +00:00
Zhou Sheng b912844554 Enable KnownZero/One.clear(). 
llvm-svn: 35093
 2007-03-14 03:21:24 +00:00
Evan Cheng 2874855302 Try schedule def + use closer whne Sethi-Ullman numbers are the same. 
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.

llvm-svn: 35089
 2007-03-13 23:25:11 +00:00
Evan Cheng 72a8bcf238 AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] 
llvm-svn: 35088
 2007-03-13 21:05:54 +00:00
Evan Cheng 507eefa757 Zero is always a legal AM immediate. 
llvm-svn: 35087
 2007-03-13 20:37:59 +00:00
Evan Cheng b5eb932c93 Correct type info for isLegalAddressImmediate() check. 
llvm-svn: 35086
 2007-03-13 20:34:37 +00:00
Nicolas Geoffray 7aad92868c Stack and register alignment of call arguments in the ELF ABI 
llvm-svn: 35083
 2007-03-13 15:02:46 +00:00
Chris Lattner d1bce956b4 ifdef out some dead code. 
Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll

llvm-svn: 35082
 2007-03-13 14:27:42 +00:00
Zhou Sheng ebe634e662 For expression like 
"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)",
to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of
zext().

llvm-svn: 35080
 2007-03-13 06:40:59 +00:00
Zhou Sheng af4341d441 In APInt version ComputeMaskedBits(): 
1. Ensure VTy, KnownOne and KnownZero have same bitwidth.
  2. Make code more efficient.

llvm-svn: 35078
 2007-03-13 02:23:10 +00:00
Evan Cheng 818242bbaf Implement getTargetLowering() or else LSR won't be using ARM specific hooks. 
llvm-svn: 35077
 2007-03-13 01:20:42 +00:00
Evan Cheng b7004fd889 More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. 
llvm-svn: 35076
 2007-03-12 23:37:10 +00:00
Evan Cheng 2150b9286f Updated TargetLowering LSR addressing mode hooks for ARM and Thumb. 
llvm-svn: 35075
 2007-03-12 23:30:29 +00:00
Evan Cheng b9dce9db85 More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. 
llvm-svn: 35074
 2007-03-12 23:29:01 +00:00
Evan Cheng 3ab7ea7965 More flexible TargetLowering LSR hooks for testing whether an immediate is 
a legal target address immediate or scale.

llvm-svn: 35073
 2007-03-12 23:28:50 +00:00
Evan Cheng 720acdfb31 Use new TargetLowering addressing modes hooks. 
llvm-svn: 35072
 2007-03-12 23:27:37 +00:00
Evan Cheng 57f261b13a Stupid bug: SSE2 supports v2i64 add / sub. 
llvm-svn: 35070
 2007-03-12 22:58:52 +00:00
Reid Spencer 6223c05805 Revert the last patch as it violates the conditions of sext/zext. 
llvm-svn: 35068
 2007-03-12 18:37:25 +00:00
Jeff Cohen 72ac14ed29 Unbreak C++ build. 
llvm-svn: 35067
 2007-03-12 17:57:00 +00:00
Jeff Cohen 00227417d2 Unbreak VC++ build. Do not use identifiers starting with _ as they are reserved and 
can collide with system defined names.  Windows defines _BB, for example.

llvm-svn: 35066
 2007-03-12 17:56:27 +00:00
Zhou Sheng 3999ffa0c8 For APInt::z/sext(width), if width == BitWidth, just return *this. 
llvm-svn: 35065
 2007-03-12 17:47:45 +00:00
Reid Spencer 1791f23803 Add an APInt version of SimplifyDemandedBits. 
Patch by Zhou Sheng.

llvm-svn: 35064
 2007-03-12 17:25:59 +00:00
Reid Spencer d9281784be Add an APInt version of ShrinkDemandedConstant. 
Patch by Zhou Sheng.

llvm-svn: 35063
 2007-03-12 17:15:10 +00:00
Zhou Sheng be171ee5cd Avoid to assert on "(KnownZero & KnownOne) == 0". 
llvm-svn: 35062
 2007-03-12 16:54:56 +00:00
Zhou Sheng b3e00c4656 In function ComputeMaskedBits(): 
1. Replace getSignedMinValue() with getSignBit() for better code readability.
  2. Replace APIntOps::shl() with operator<<= for convenience.
  3. Make APInt construction more effective.

llvm-svn: 35060
 2007-03-12 05:44:52 +00:00
Nick Lewycky d9bd0bc3e2 Add value ranges. Currently inefficient in both execution time and 
optimization power.

llvm-svn: 35058
 2007-03-10 18:12:48 +00:00
Anton Korobeynikov 8a6dc102d3 Use range tests in LowerSwitch, where possible 
llvm-svn: 35057
 2007-03-10 16:46:28 +00:00
Nick Lewycky e455937fae Add getter methods for the extremes of a ConstantRange. 
llvm-svn: 35056
 2007-03-10 15:54:12 +00:00
Bill Wendling e9b81f5366 Adding more arithmetic operators to MMX. This is an almost exact copy of 
the addition. Please let me know if you have suggestions.

llvm-svn: 35055
 2007-03-10 09:57:05 +00:00
Devang Patel 5f50e61d52 Remove dead comments. 
llvm-svn: 35053
 2007-03-09 23:41:03 +00:00
Devang Patel bda1250624 Avoid recursion. Use iterative algorithm for RenamePass(). 
llvm-svn: 35052
 2007-03-09 23:39:14 +00:00
Devang Patel 58818c530f Increment iterator now because IVUseShouldUsePostIncValue may remove 
User from the list of I users.

llvm-svn: 35051
 2007-03-09 21:19:53 +00:00
Reid Spencer ad3618a33d Regenerate. 
llvm-svn: 35050
 2007-03-09 21:19:09 +00:00
Evan Cheng 09663aeac7 Minor stuff. 
llvm-svn: 35049
 2007-03-09 19:46:06 +00:00
Evan Cheng 31ef0ab7cf Add comments about LSR / ARM. 
llvm-svn: 35048
 2007-03-09 19:35:33 +00:00
Evan Cheng 603f3094eb Unfinished work and ideas related to register scavenger. 
llvm-svn: 35047
 2007-03-09 19:34:51 +00:00
Reid Spencer 3fcf0c24a9 For PR1245: 
Account for the sign bit when computing the number of bits required for
a negative integer literal constant.

llvm-svn: 35046
 2007-03-09 19:26:52 +00:00
Dale Johannesen 368faf9acd apply comments from review of last patch 
llvm-svn: 35045
 2007-03-09 19:18:59 +00:00
Dale Johannesen af0cff2671 Add some observations from CoreGraphics benchmark. Remove register 
scavenging todo item, since it is now implemented.

llvm-svn: 35044
 2007-03-09 17:58:17 +00:00
Anton Korobeynikov 2f4ae5306e Unbreak mingw32 build 
llvm-svn: 35042
 2007-03-09 11:53:34 +00:00
Evan Cheng df7949a8d0 If a virtual register is already marked alive in this block, that means it is 
alive in one of the successor block. Do not add it to the kill list.

llvm-svn: 35041
 2007-03-09 09:48:56 +00:00
Evan Cheng 9bc8d4b6f2 Print preds / succs BB numbers. 
llvm-svn: 35040
 2007-03-09 08:29:08 +00:00
Evan Cheng 91b0790297 Avoid variable shadowing. 
llvm-svn: 35039
 2007-03-09 06:02:17 +00:00
Bill Wendling 16574a72e1 Don't use std::hex. 
llvm-svn: 35038
 2007-03-08 23:37:24 +00:00
Bill Wendling 61a2773977 Don't use a cast. It causes an error on some platforms. 
llvm-svn: 35037
 2007-03-08 23:26:50 +00:00
Evan Cheng ea28fc5dc4 Implement inline asm modifier c. 
llvm-svn: 35035
 2007-03-08 22:42:46 +00:00
Chris Lattner ce8aba03ee implement support for floating point constants used as inline asm memory operands. 
llvm-svn: 35033
 2007-03-08 22:29:47 +00:00
Bill Wendling 6092ce25cf Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that 
moves, loads, etc. are recognized.

llvm-svn: 35031
 2007-03-08 22:09:11 +00:00
Evan Cheng 63170b6959 Fix a typo. 
llvm-svn: 35030
 2007-03-08 21:59:30 +00:00
Devang Patel 01919d2c0b Speed Up Pass Manager. 
- Check Immutableness before searching PreservedSet.
- Avoid unnecessary traversal while setting Last User.

llvm-svn: 35028
 2007-03-08 19:05:01 +00:00
Zhou Sheng d1eb3d593e Fix a bug in function ComputeMaskedBits(). 
llvm-svn: 35027
 2007-03-08 15:15:18 +00:00
Evan Cheng ddf082082c Putting more constants which do not contain relocations into .literal{4|8|16} 
llvm-svn: 35026
 2007-03-08 08:31:54 +00:00
Chris Lattner b7bc3f2d30 make this fail even in non-assert builds. 
llvm-svn: 35025
 2007-03-08 07:07:03 +00:00
Chris Lattner abd3bff4f2 This appears correct, enable it so we can see perf changes on testers 
llvm-svn: 35024
 2007-03-08 07:03:55 +00:00
Chris Lattner 9f022d550b Second half of PR1226. This is currently still disabled, until I have a chance to 
do the correctness/performance analysis testing.

llvm-svn: 35023
 2007-03-08 06:36:54 +00:00
Zhou Sheng 387d7b1a35 Fix a bug in APIntified ComputeMaskedBits(). 
llvm-svn: 35022
 2007-03-08 05:42:00 +00:00
Evan Cheng e94a2f8026 Change register allocation order to Dale's suggestion. 
llvm-svn: 35021
 2007-03-08 02:56:40 +00:00
Evan Cheng 977195e912 Bug fix. Not advancing the register scavenger iterator correctly. 
llvm-svn: 35020
 2007-03-08 02:55:08 +00:00
Reid Spencer bb5741fb02 For PR1205: 
Provide an APIntified version of MaskedValueIsZero. This will (temporarily)
cause a "defined but not used" message from the compiler. It will be used
in the next patch in this series.

Patch by Sheng Zhou.

llvm-svn: 35019
 2007-03-08 01:52:58 +00:00
Reid Spencer aa69640b10 For PR1205: 
Add a new ComputeMaskedBits function that is APIntified. We'll slowly
convert things over to use this version. When its all done, we'll remove
the existing version.

llvm-svn: 35018
 2007-03-08 01:46:38 +00:00
Evan Cheng d918477ac3 For Darwin, put constant data into .const, .const_data, .literal{4|8|16} 
sections.

llvm-svn: 35017
 2007-03-08 01:25:25 +00:00
Evan Cheng 13a1d96963 Put constant data to .const, .const_data, .literal{4|8|16} sections. 
llvm-svn: 35016
 2007-03-08 01:07:07 +00:00
Evan Cheng 58aeb9c444 Add ReadOnlySection directive. 
llvm-svn: 35015
 2007-03-08 01:00:38 +00:00
Evan Cheng f9e003b653 Added ContainsRelocations() to check if a constant might only be resolvable at load time. 
llvm-svn: 35014
 2007-03-08 00:59:12 +00:00
Evan Cheng f030f2d628 Only safe to use a call-clobbered or spilled callee-saved register as scratch register. 
llvm-svn: 35010
 2007-03-07 20:30:36 +00:00
Bill Wendling 6d8211c0ac Remove useless pattern fragments. 
llvm-svn: 35009
 2007-03-07 18:23:09 +00:00
Anton Korobeynikov ed4b303c10 Refactoring of formal parameter flags. Enable properly use of 
zext/sext/aext stuff.

llvm-svn: 35008
 2007-03-07 16:25:09 +00:00
Anton Korobeynikov dd6ce6900e Cleanup: make SetCounter an instance variable 
llvm-svn: 35007
 2007-03-07 08:25:02 +00:00
Evan Cheng 8a1d09d079 Avoid combining indexed load further. 
llvm-svn: 35005
 2007-03-07 08:07:03 +00:00
Devang Patel 2ac57e1f02 Now IndVarSimplify is a LoopPass. 
llvm-svn: 35003
 2007-03-07 06:39:01 +00:00
Bill Wendling 97905b4027 Properly support v8i8 and v4i16 types. It now converts them to v2i32 for 
load and stores.

llvm-svn: 35002
 2007-03-07 05:43:18 +00:00
Devang Patel 69730c96db Now LICM is a LoopPass. 
llvm-svn: 35001
 2007-03-07 04:41:30 +00:00
Anton Korobeynikov 942fda027f Fix DWARF debugging information on x86/Linux and (hopefully) 
Mingw32/Cygwin targets. This fixes PR978

llvm-svn: 35000
 2007-03-07 02:47:57 +00:00
Evan Cheng 17cdad0687 ARM always use register scavenger. No longer reserves R12. 
llvm-svn: 34999
 2007-03-07 02:46:23 +00:00
Evan Cheng 2818fdd019 Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions. 
llvm-svn: 34998
 2007-03-07 02:38:05 +00:00
Devang Patel 9779e56c04 Now LoopUnroll is a LoopPass. 
llvm-svn: 34996
 2007-03-07 01:38:05 +00:00
Devang Patel 901a27d892 Now LoopUnswitch is a LoopPass. 
llvm-svn: 34992
 2007-03-07 00:26:10 +00:00
Evan Cheng 67038e7a8b Fix one more Thumb eliminateFrameIndex bug. 
llvm-svn: 34990
 2007-03-07 00:12:18 +00:00
Reid Spencer 4fd528f213 Fix all of last night's JIT failures in Prolangs-C++ by finishing the 
implementation of getConstantValue().

llvm-svn: 34988
 2007-03-06 22:23:15 +00:00
Evan Cheng 5ed781b0db Register scavenging is now on by default for ARM. 
llvm-svn: 34987
 2007-03-06 22:02:53 +00:00
Evan Cheng 41bc2fd242 Make load / store optimizer use register scavenger. 
llvm-svn: 34986
 2007-03-06 21:59:20 +00:00
Evan Cheng 24f65cc91e Minor bug fix. 
llvm-svn: 34985
 2007-03-06 21:58:15 +00:00
Devang Patel b0743b5d6a Now LoopStrengthReduce is a LoopPass. 
llvm-svn: 34984
 2007-03-06 21:14:09 +00:00
Chris Lattner 13780ac7db big endian 32-bit systems (e.g. ppc32) want to return the high reg first, not 
the lo-reg first.  This is fallout from my ppc calling conv change yesterday,
it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx

llvm-svn: 34983
 2007-03-06 20:01:06 +00:00
Devang Patel db0db9740b Insert loop into LQ before visiting children. 
llvm-svn: 34982
 2007-03-06 19:50:49 +00:00
Anton Korobeynikov 6c5e0ad71c Small eye-candy: use asciz directive everywhere, where possible. 
llvm-svn: 34981
 2007-03-06 19:25:02 +00:00
Devang Patel 4a8725cf2f Use schedulePass() instead of assignPassManager() to add new LPPassManager. 
This ensures that require analysis info is available.

llvm-svn: 34980
 2007-03-06 19:11:25 +00:00
Devang Patel ef7ac13406 Add LPPassManager::insertLoop(). 
llvm-svn: 34979
 2007-03-06 19:00:02 +00:00
Bill Wendling bbd25984b7 Add LOAD/STORE support for MMX. 
llvm-svn: 34978
 2007-03-06 18:53:42 +00:00
Devang Patel fca3aa3645 LPPassManager::deleteLoopFromQueue() add meat. Cut-n-paste code from 
LoopUnswitch pass.

llvm-svn: 34977
 2007-03-06 18:38:33 +00:00
Evan Cheng d28de6700b Code clean up. Prepare to use register scavenger. 
llvm-svn: 34976
 2007-03-06 18:02:41 +00:00
Devang Patel 1699384509 LPPassManager. Implement preparePassManager() hook. 
llvm-svn: 34975
 2007-03-06 17:59:37 +00:00
Devang Patel 9d9fc90952 Keep track of higher level analysis. 
llvm-svn: 34974
 2007-03-06 17:52:53 +00:00
Devang Patel 84ffc223f1 LPPassManager : Add initialization and finalizatino hooks. 
llvm-svn: 34968
 2007-03-06 16:59:03 +00:00
Evan Cheng 8b8cac289b Minor interface change. 
llvm-svn: 34967
 2007-03-06 10:05:14 +00:00
Evan Cheng 4783ae8ac1 Scavenge a register using the register scavenger when needed. 
llvm-svn: 34966
 2007-03-06 10:03:56 +00:00
Evan Cheng c1b21857a4 If target decides to create an emergency spill slot, make sure it's closest to SP or frame pointer. 
llvm-svn: 34965
 2007-03-06 10:02:38 +00:00
Evan Cheng 372c2c69f8 Register scavenger is now capable of scavenging. It spills a register whose use of furthest away to make it available. 
llvm-svn: 34964
 2007-03-06 10:01:25 +00:00
Anton Korobeynikov e7ec3bc7bc Use new SDIselParamAttr enumeration. This removes "magick" constants 
from formal attributes' flags processing.

llvm-svn: 34963
 2007-03-06 08:12:33 +00:00
Anton Korobeynikov f0b9316552 Enumerate SDISel formal parameter attributes. Make use of new 
enumeration.

llvm-svn: 34960
 2007-03-06 06:10:33 +00:00
Anton Korobeynikov 666d23d4e6 Implement PR1240 
llvm-svn: 34959
 2007-03-06 05:32:48 +00:00
Reid Spencer 4e42790c43 1. Make StoreValueToMemory a little more efficient by not requiring caller 
to make a copy of the GenericValue.
2. Fix a copy & paste bug in StoreValueToMemory where 64-bit values were
   truncated to 32

llvm-svn: 34958
 2007-03-06 05:03:16 +00:00
Reid Spencer 1efc4aaf84 Fix some thinko's in the last patch. PtrSize has to be in bits and we 
might need to zext not just trunc the value.

llvm-svn: 34955
 2007-03-06 03:46:41 +00:00
Reid Spencer 10dbc1e896 Fix a bug in IntToPtr. Truncating to 64-bits only works if the integer 
is larger. Adjust so that it truncates to pointer width, only if necessary.

llvm-svn: 34954
 2007-03-06 03:41:50 +00:00
Reid Spencer c764c55745 Simplify code as a result of the change in GenericValue to have a single 
integer field of type APInt instead of different sized integer fields.

llvm-svn: 34952
 2007-03-06 03:11:31 +00:00
Reid Spencer 40015aad5a Radically simplify execution. This patch gets rid of all the special 
handling for integer of various sizes. GenericValue now has just a single
integer field of type APInt. We use its facilities directly in the
execution of all instructions.

llvm-svn: 34951
 2007-03-06 03:09:31 +00:00
Reid Spencer c45e10474a Adjust and simplify external function processing now that GenericValue has 
a single integer field of type APInt.

llvm-svn: 34950
 2007-03-06 03:08:12 +00:00
Reid Spencer 7f68713eb8 APInt's are no longer allocated on the heap because they are direct 
members of GenericValue. Consequently the code to clean them up isn't
needed.

llvm-svn: 34948
 2007-03-06 03:06:48 +00:00
Reid Spencer 2d89fa84bc Remove the insufficient code in Interpreter::create that computed the 
Target DataLayout incorrectly. For now, we'll trust that the module has
got the correct DataLayout. In the future, this needs to be changed to
tell the TargetData to be "current host".

llvm-svn: 34947
 2007-03-06 03:05:57 +00:00
Reid Spencer 87aa65f40e Simplify things significantly because GenericValue now has a single integer 
field, of type APInt, instead of multiple integer fields. Also, get rid of
the special endianness code in StoreValueToMemory and LoadValueToMemory.
ExecutionEngine is always used to execute on the host platform so this is
now unnecessary.

llvm-svn: 34946
 2007-03-06 03:04:04 +00:00
Devang Patel a8c81c5261 Use std::deque to manage loop queue inside LPPassManager. 
llvm-svn: 34943
 2007-03-06 02:30:46 +00:00
Devang Patel 42dd1e92c7 Keep track of inherited analysis. For example, if a loop pass does not 
preserve dominator info then it should update parent FPPassManager's
available analysis info to reflect this.

llvm-svn: 34942
 2007-03-06 01:55:46 +00:00
Devang Patel d74ede70fb Add preparePassManager() hook. This allows each pass to check whether 
current active pass manager is appropriate or not.

A loop pass may consider current LPPassManager in appropraite if loop
pass is not preserving analysis information that is used by other
passes managed by current LPPassManager. In such situation, loop pass
can pop current LPPassManager from the PMStack using this  hook
and use new LPPassManager for itself.

llvm-svn: 34941
 2007-03-06 01:06:16 +00:00
Chris Lattner 4f2e4e0f92 Switch PPC return lower to use an autogenerated CC description. 
llvm-svn: 34940
 2007-03-06 00:59:59 +00:00
Reid Spencer 3939b1a274 Remove an unnecessary if statement and adjust indentation. 
llvm-svn: 34939
 2007-03-05 23:36:13 +00:00
Bill Wendling b1c86b49ea Add the emms intrinsic for MMX support. 
llvm-svn: 34938
 2007-03-05 23:09:45 +00:00
Devang Patel ec2b9a7850 Current pass manager, not the parent pass manager, assumes the role of 
last user when one of the managed pass uses info provided by parent pass
manager.

This was exposed by LPPassManager work.

llvm-svn: 34936
 2007-03-05 22:57:49 +00:00
Devang Patel 003a559633 Avoid constructing std::strings unless pass debugging is ON. 
llvm-svn: 34933
 2007-03-05 20:01:30 +00:00
Devang Patel 7ebf09dbca Account for time consumed by releaseMemory() properly. 
llvm-svn: 34932
 2007-03-05 18:20:51 +00:00
Lauro Ramos Venancio f10769dda7 Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS. 
Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi.

llvm-svn: 34931
 2007-03-05 17:59:58 +00:00
Chris Lattner 66e6a8229a This is the first major step of implementing PR1226. We now successfully 
scalarrepl things down to elements, but mem2reg can't promote elements that
are memset/memcpy'd.  Until then, the code is disabled "0 &&".

llvm-svn: 34924
 2007-03-05 07:52:57 +00:00
Jeff Cohen 7157fe3f4b Ensure 64-bit correctness. 
llvm-svn: 34923
 2007-03-05 05:45:08 +00:00
Jeff Cohen a531d04b64 Implement memoryLimit on Windows. 
llvm-svn: 34922
 2007-03-05 05:22:08 +00:00
Chris Lattner fe53cf2459 fix a subtle bug that caused an MSVC warning. Thanks to Jeffc for pointing this out. 
llvm-svn: 34920
 2007-03-05 00:11:19 +00:00
Chris Lattner 5fdded1d2f Add some simplifications for demanded bits, this allows instcombine to turn: 
define i64 @test(i64 %A, i32 %B) {
        %tmp12 = zext i32 %B to i64             ; <i64> [#uses=1]
        %tmp3 = shl i64 %tmp12, 32              ; <i64> [#uses=1]
        %tmp5 = add i64 %tmp3, %A               ; <i64> [#uses=1]
        %tmp6 = and i64 %tmp5, 123              ; <i64> [#uses=1]
        ret i64 %tmp6
}

into:

define i64 @test(i64 %A, i32 %B) {
        %tmp6 = and i64 %A, 123         ; <i64> [#uses=1]
        ret i64 %tmp6
}

This implements Transforms/InstCombine/add2.ll:test1

llvm-svn: 34919
 2007-03-05 00:02:29 +00:00
Jeff Cohen b622c11f77 Unbreak VC++ build. 
llvm-svn: 34917
 2007-03-05 00:00:42 +00:00
Chris Lattner ab2f913b68 simplify some code 
llvm-svn: 34914
 2007-03-04 23:16:36 +00:00
Chris Lattner 47206667c0 fold away addc nodes when we know there cannot be a carry-out. 
llvm-svn: 34913
 2007-03-04 20:40:38 +00:00
Chris Lattner 2dcc6e7f58 generalize 
llvm-svn: 34910
 2007-03-04 20:08:45 +00:00
Chris Lattner e2e13caeb2 canonicalize constants to the RHS of addc/adde. If nothing uses the carry out of 
addc, turn it into add.

This allows us to compile:

long long test(long long A, unsigned B) {
  return (A + ((long long)B << 32)) & 123;
}

into:

_test:
        movl $123, %eax
        andl 4(%esp), %eax
        xorl %edx, %edx
        ret

instead of:
_test:
        xorl %edx, %edx
        movl %edx, %eax
        addl 4(%esp), %eax   ;; add of zero
        andl $123, %eax
        ret

llvm-svn: 34909
 2007-03-04 20:03:15 +00:00
Chris Lattner 362621c7ae eliminate some ops if they have an undef RHS 
llvm-svn: 34908
 2007-03-04 20:01:46 +00:00
Chris Lattner 1e04147240 fix typo 
llvm-svn: 34906
 2007-03-04 06:36:24 +00:00
Chris Lattner d647f92a14 add missing braces 
llvm-svn: 34905
 2007-03-04 06:13:52 +00:00
Chris Lattner c33fd469ef minor cleanups 
llvm-svn: 34904
 2007-03-04 04:50:21 +00:00
Reid Spencer b8825b8c04 Remove unneeded header file. 
llvm-svn: 34903
 2007-03-04 04:41:04 +00:00
Chris Lattner 8258b44b22 Speed up -instcombine by 20% by avoiding a particularly expensive passmgr call. 
llvm-svn: 34902
 2007-03-04 04:27:24 +00:00
Chris Lattner a5403a587c switch MarkAliveBlocks over to using SmallPtrSet instead of std::set, speeding 
up simplifycfg by 20%

llvm-svn: 34901
 2007-03-04 04:20:48 +00:00
Chris Lattner 16cf9a7686 Speed up Loop::isLCSSAForm by using a hash table instead of a sorted vector. 
llvm-svn: 34900
 2007-03-04 04:06:39 +00:00
Chris Lattner d7b4c92cd0 make better use of LCSSA information in RewriteLoopExitValues. Before, we 
would scan the entire loop body, then scan all users of instructions in the
loop, looking for users outside the loop.  Now, since we know that the
loop is in LCSSA form, we know that any users outside the loop will be LCSSA
phi nodes.  Just scan them.

This speeds up indvars significantly.

llvm-svn: 34898
 2007-03-04 03:43:23 +00:00
Reid Spencer 69904f939a Guard further against APInt operations with operands of unequal bit width. 
llvm-svn: 34897
 2007-03-04 01:25:35 +00:00
Chris Lattner 1f7648efba Implement PR1179/PR1232 and test/Transforms/IndVarsSimplify/loop_evaluate_[234].ll 
This makes -indvars require and use LCSSA, updating it as appropriate.

llvm-svn: 34896
 2007-03-04 01:00:28 +00:00
Chris Lattner ca401aac31 Fix CodeGen/Generic/fpowi-promote.ll and PR1239 
llvm-svn: 34893
 2007-03-03 23:43:21 +00:00
Chris Lattner ed30abf0cb Make RewriteLoopExitValues far less nested by using continue in the loop 
llvm-svn: 34891
 2007-03-03 22:48:48 +00:00
Chris Lattner 567b9254cd Add an expand action for ISD label which just deletes the label. 
This "fixes" PR1238.

llvm-svn: 34890
 2007-03-03 19:21:38 +00:00
Reid Spencer 04a1829559 Remove unnecessary #include. 
llvm-svn: 34889
 2007-03-03 18:29:16 +00:00
Reid Spencer 603682ad1d Deal with error handling better. 
llvm-svn: 34887
 2007-03-03 18:19:18 +00:00
Reid Spencer 1f87660d29 Make sure that when we store a value it is masked to its correct bit 
width. This helps CBE work with non-standard integer bit widths.

llvm-svn: 34885
 2007-03-03 16:33:33 +00:00
Reid Spencer ec8c51c1b1 Complete the APIntification of the interpreter. All asserts for > 64 bits 
have been removed and dealt with. The interpreter should now be able to
execute any LLVM program using any bit width.

llvm-svn: 34884
 2007-03-03 08:38:04 +00:00
Reid Spencer 00919f5769 Avoid memory leakage by having caller construct the APInt for the 
destination value of LoadValueFromMemory.

llvm-svn: 34883
 2007-03-03 08:36:29 +00:00
Reid Spencer 50d7ad9183 Fix constant folding of fp->int bitcast for vectors. 
llvm-svn: 34880
 2007-03-03 08:32:46 +00:00
Evan Cheng d74cb0e194 Only propagate IsKill if the last use is a kill. 
llvm-svn: 34878
 2007-03-03 06:32:37 +00:00
Reid Spencer 54c6e84c83 Implement APInt support for the binary operators. 
Move the getConstantExpr function towards the end of the file so we don't
need a dozen forward declarations.

llvm-svn: 34877
 2007-03-03 06:22:22 +00:00
Reid Spencer 72aafa1d49 1. Have the ExecutionContext keep track of the APInt's allocated and 
ensure they are cleaned up when the stack frame exits.
2. Move a function to the Execution.cpp file where it belongs.

llvm-svn: 34876
 2007-03-03 06:19:55 +00:00
Nate Begeman 323cf8f602 http://llvm.org/bugs/show_bug.cgi?id=1237 
llvm-svn: 34875
 2007-03-03 06:18:18 +00:00
Reid Spencer 815f8dd225 Implement loading and storing of APInt values from memory. 
llvm-svn: 34874
 2007-03-03 06:18:03 +00:00
Nick Lewycky e6049c2f08 Emit low/high immediate loads properly for Linux/PPC. 
llvm-svn: 34871
 2007-03-03 05:29:51 +00:00
Chris Lattner da1d04a057 my recent change caused a failure in a bswap testcase, because it changed 
the order that instcombine processed instructions in the testcase.  The end
result is that instcombine finished with:

define i16 @test1(i16 %a) {
        %tmp = zext i16 %a to i32               ; <i32> [#uses=2]
        %tmp21 = lshr i32 %tmp, 8               ; <i32> [#uses=1]
        %tmp5 = shl i32 %tmp, 8         ; <i32> [#uses=1]
        %tmp.upgrd.32 = or i32 %tmp21, %tmp5            ; <i32> [#uses=1]
        %tmp.upgrd.3 = trunc i32 %tmp.upgrd.32 to i16           ; <i16> [#uses=1]
        ret i16 %tmp.upgrd.3
}

which can't get matched as a bswap.

This patch makes instcombine more sophisticated about removing truncating
casts, allowing it to turn this into:

define i16 @test2(i16 %a) {
        %tmp211 = lshr i16 %a, 8
        %tmp52 = shl i16 %a, 8
        %tmp.upgrd.323 = or i16 %tmp211, %tmp52
        ret i16 %tmp.upgrd.323
}

which then matches as bswap.  This fixes bswap.ll and implements
InstCombine/cast2.ll:test[12].  This also implements cast elimination of
add/sub.

llvm-svn: 34870
 2007-03-03 05:27:34 +00:00
Nick Lewycky db42295ff2 Translate bit operations to English. 
llvm-svn: 34868
 2007-03-03 03:14:40 +00:00
Evan Cheng 3fd728596e Watch out for cases like this: 
entry (0x8b056f0, LLVM BB @0x8b01b30, ID#0):
Live Ins: %r0 %r1 %r2 %r3
        %reg1032 = tMOVrr %r3<kill>
        %reg1033 = tMOVri8 1
        %reg1034 = tMOVri8 0
        tCMPi8 %reg1029<kill>, 0
        tBcc mbb<entry,0x8b06a10>, 0
    Successors according to CFG: 0x8b06980 0x8b06a10

entry (0x8b06980, LLVM BB @0x8b01b30, ID#12):
    Predecessors according to CFG: 0x8b056f0
        %reg1036 = tMOVrr %reg1034<kill>
    Successors according to CFG: 0x8b06a10

entry (0x8b06a10, LLVM BB @0x8b01b30, ID#13):
    Predecessors according to CFG: 0x8b056f0 0x8b06980
        %reg1024<dead> = tMOVrr %reg1030<kill>
        ...

reg1030 and r1 have already been joined. When reg1024 and reg1030 are joined,
r1 live range from function entry to the tMOVrr instruction are dead. Eliminate
r1 from the livein set of the entry BB, not the BB where the copy is.

llvm-svn: 34866
 2007-03-03 02:18:00 +00:00
Chris Lattner 960a543037 add a top-level iteration loop to instcombine. This means that it will never 
finish without combining something it is capable of.

llvm-svn: 34865
 2007-03-03 02:04:50 +00:00
Reid Spencer c34dedf686 APIntify this pass. 
llvm-svn: 34863
 2007-03-03 00:48:31 +00:00
Reid Spencer 53a3739c80 Finally get this patch right :) 
Replace expensive getZExtValue() == 0 calls with isZero() calls.

llvm-svn: 34861
 2007-03-02 23:51:25 +00:00
Reid Spencer ba547cbb2a Dang, I've done that twice now! Undo previous commit. 
llvm-svn: 34860
 2007-03-02 23:37:53 +00:00
Reid Spencer 558990e189 Use more efficient test for one value in a ConstantInt. 
llvm-svn: 34859
 2007-03-02 23:35:28 +00:00
Reid Spencer 29fe20a98b Guard against huge loop trip counts in an APInt safe way. 
llvm-svn: 34858
 2007-03-02 23:31:34 +00:00
Evan Cheng deaea25eb9 X86-64 VACOPY needs custom expansion. va_list is a struct { i32, i32, i8*, i8* }. 
llvm-svn: 34857
 2007-03-02 23:16:35 +00:00
Reid Spencer dec03a08d6 Make sure debug code is not evaluated in non-debug case. 
llvm-svn: 34856
 2007-03-02 23:15:21 +00:00
Reid Spencer 1e102971d2 1. Sort switch cases using APInt safe comparison. 
2. Make sure debug output of APInt values is safe for all bit widths.

llvm-svn: 34855
 2007-03-02 23:05:28 +00:00
Reid Spencer 43376a74af Use APInt safe isOne() method on ConstantInt instead of getZExtValue()==1 
llvm-svn: 34854
 2007-03-02 23:03:17 +00:00
Reid Spencer bb38d79ad6 Make sorting of ConstantInt be APInt clean through use of ult function. 
llvm-svn: 34853
 2007-03-02 23:01:14 +00:00