Commit Graph

246601 Commits

Author SHA1 Message Date
Chad Rosier 611b73b1f9 Fix 80-column violations. NFC.
llvm-svn: 286117
2016-11-07 16:28:04 +00:00
Enrico Granata 3949cb61a5 Fix an issue where LLDB would hang trying to launch tvOS simulator binaries
llvm-svn: 286116
2016-11-07 16:25:01 +00:00
Jonas Hahnfeld 50fed0475f [OpenMP] Enable ThreadSanitizer to check OpenMP programs
This patch allows ThreadSanitizer (Tsan) to verify OpenMP programs.
It means that no false positive will be reported by Tsan when
verifying an OpenMP programs.
This patch introduces annotations within the OpenMP runtime module to
provide information about thread synchronization to the Tsan runtime.

In order to enable the Tsan support when building the runtime, you must
enable the TSAN_SUPPORT option with the following environment variable:

-DLIBOMP_TSAN_SUPPORT=TRUE

The annotations will be enabled in the main shared library
(same mechanism of OMPT).

Patch by Simone Atzeni and Joachim Protze!

Differential Revision: https://reviews.llvm.org/D13072

llvm-svn: 286115
2016-11-07 15:58:36 +00:00
Yaxun Liu 1d50fe9bef [OpenCL] Remove redundant test for OpenCL header file
Differential Revision: https://reviews.llvm.org/D26302

llvm-svn: 286114
2016-11-07 15:55:51 +00:00
Sanjay Patel 86408a8048 [InstCombine] allow splat vector folds in adjustMinMax() (retry r285732)
This was reverted at r285866 because there was a crash handling a scalar
select of vectors. I added a check for that pattern and a test case based
on the example provided in the post-commit thread for r285732.

llvm-svn: 286113
2016-11-07 15:52:45 +00:00
Jonas Paulsson 4f0509fab3 [SystemZ] Correct the SchedModel regarding vector unit / instructions.
* Use a generic vector unit to model the issue unit more accurately.
* Update some vector instructions that actually use the vector unit for more
  than one cycle.

Review: Ulrich Weigand
llvm-svn: 286112
2016-11-07 15:45:06 +00:00
Amara Emerson 614b44bbe9 This patch adds support for 16 bit floating point registers to the inline asm register selection on AArch64.
Without this patch, register allocation for the example below fails.

define half @test(half %a1, half %a2) #0 {
entry:
  %0 = tail call half asm "sqrshl ${0:h}, ${1:h}, ${2:h}", "=w,w,w" (half %a1, half %a2) #1
  ret half %0
}

Patch by Florian Hahn.

Differential Revision: https://reviews.llvm.org/D25080

llvm-svn: 286111
2016-11-07 15:42:12 +00:00
Chad Rosier d6daac4746 [AArch64] Removed the narrow load merging code in the ld/st optimizer.
This feature has been disabled for some time now, so remove cruft.

Differential Revision: https://reviews.llvm.org/D26248

llvm-svn: 286110
2016-11-07 15:27:22 +00:00
Jonas Paulsson 818431a61a [SystemZ] Fixes in SchedModels for older subtargets.
IssueWidth updated to reflect the capacity of the issue unit correctly.
Correct number of FX and LS units modelled (2, was 1).

Review: Ulrich Weigand
llvm-svn: 286109
2016-11-07 14:47:25 +00:00
Chad Rosier 8f348017b0 [AliasSetTracker] Make AST smarter about assume intrinsics that don't actually affect memory.
Differential Revision: https://reviews.llvm.org/D26252

llvm-svn: 286108
2016-11-07 14:11:45 +00:00
James Molloy b03e0879fc [Thumb1] Move padding earlier when synthesizing TBBs off of the PC
When the base register (register pointing to the jump table) is the PC, we expect the jump table to directly follow the jump sequence with no intervening padding.

If there is intervening padding, the calculated offsets will not be correct. One solution would be to account for any padding in the emitted LDRB instruction, but at the moment we don't support emitting MCExprs for the load offset.

In the meantime, it's correct and only a slight amount worse to just move the padding up, from just before the jump table to just before the jump instruction sequence. We can do that by emitting code alignment before the jump sequence, as we know the number of instructions in the sequence is always 4.

llvm-svn: 286107
2016-11-07 13:38:21 +00:00
Alexey Bataev 2158fa6f20 [OPENMP] Fixed test on MIPS-based buildbots.
llvm-svn: 286106
2016-11-07 13:37:34 +00:00
Simon Pilgrim b56c731f18 [X86][AVX512] Add AVX512VL/AVX512BWVL vector truncation tests
llvm-svn: 286105
2016-11-07 13:34:29 +00:00
Simon Pilgrim 02666ac9c3 [X86][SSE] Drop unnecessary -mcpu argument from trunc tests
cpu/triple duplication

llvm-svn: 286104
2016-11-07 13:28:20 +00:00
Alexey Bataev ac5eabb0b9 [OPENMP] Fixed capturing of VLA variables.
After some changes in codegen capturing of VLA variables in OpenMP regions was broken, causing compiler crash. Patch fixes this issue.

llvm-svn: 286103
2016-11-07 11:16:04 +00:00
Diana Picus 1e2b7e6672 Revert "[OPENMP] Fixed capturing of VLA variables."
This reverts commit r286098 because the modified test breaks on many of the
buildbots.

llvm-svn: 286102
2016-11-07 10:01:43 +00:00
Pavel Labath 1071ac1935 Make space for FreeBSD core file tests
This renames the functionalities/postmortem/linux-core to elf-core and puts the
"linux" part into the individual names of the core files. Since the tests for
linux and freebsd core files are going to be very similar, having them close
together means they can reuse most of the plumbing.

llvm-svn: 286101
2016-11-07 09:58:58 +00:00
Eugene Leviant 0a8f1fe6f7 [ELF] Make InputSection<ELFT>::writeTo virtual
Differential revision: https://reviews.llvm.org/D26281

llvm-svn: 286100
2016-11-07 09:04:06 +00:00
Roger Ferrer Ibanez a5672e0c4b Protect std::experimental::optional tests under libcpp-no-exceptions
In these tests there are some paths that explicitly throw, so use
the TEST_THROW macro that was proposed for this and then skip the tests
that may enter the throwing path.

Differential Revision: https://reviews.llvm.org/D26142

llvm-svn: 286099
2016-11-07 08:23:59 +00:00
Alexey Bataev 420537fad8 [OPENMP] Fixed capturing of VLA variables.
After some changes in codegen capturing of VLA variables in OpenMP
regions was broken, causing compiler crash. Patch fixes this issue.

llvm-svn: 286098
2016-11-07 08:07:25 +00:00
Craig Topper 8e06631b09 [AVX-512][Sema] Add more intrinsics to the checks for valid immediates for embedded rounding control arguments.
llvm-svn: 286097
2016-11-07 07:01:09 +00:00
Eric Liu cf2913c6f1 Deduplicate replacements by FileEntry instead of file names.
Summary:
The current version does not deduplicate equivalent file paths correctly.
For example, a relative path and an absolute path are considered inequivalent.
Comparing FileEnry addresses these issues.

Reviewers: djasper

Subscribers: alexshap, klimek, cfe-commits

Differential Revision: https://reviews.llvm.org/D26288

llvm-svn: 286096
2016-11-07 06:08:23 +00:00
Dylan McKay c988b334b6 [AVR] Enable the ISel, frame analyzer, and alloca passes
llvm-svn: 286095
2016-11-07 06:02:55 +00:00
Brian Gesiak 2980b0a15e Update CommandLine.rst getRegisteredOptions example
Summary: Update the docs to match the changes in http://reviews.llvm.org/D7132

Reviewers: beanz, llvm-commits, modocache

Differential Revision: https://reviews.llvm.org/D26296

llvm-svn: 286094
2016-11-07 02:43:01 +00:00
Vedant Kumar 6ba1db9f78 [lldb] Fix -Waggressive-loop-optimizations warning
We shouldn't access past the end of an array, even if we think that the
layout of the struct containing the array is always what we expect. The
compiler is free to optimize away the stores as undefined behavior, and
in fact, GCC 6.2.1 claims it will do exactly this.

llvm-svn: 286093
2016-11-07 02:39:37 +00:00
Craig Topper b110e04851 [AVX-512] Remove masked pmovzx/pmovsx builtins and autoupgrade them to selects and native zext/sext.
This mostly reuses earlier autoupgrade support for the sse and avx equivalents. Just needed to add the code to add the select.

llvm-svn: 286092
2016-11-07 02:12:57 +00:00
Craig Topper adac5ca0a6 [X86] Remove GCCBuiltins from cvtsi2ss/cvtsi2sd/cvtss2sd intrinsics as they aren't used by clang. Add TODOs to remove these and some other unused intrinsics.
llvm-svn: 286091
2016-11-07 00:13:46 +00:00
Craig Topper 96041c6ba9 [X86] Use StringRef::startswith to reduce a few compares in the intrinsic autoupgrade code.
llvm-svn: 286090
2016-11-07 00:13:42 +00:00
Craig Topper 7e545335d6 [AVX-512] Remove 128/256 masked pshufb intrinsics. Autoupgrade them to legacy intrinsics and a select.
llvm-svn: 286089
2016-11-07 00:13:39 +00:00
Zachary Turner 6560d2c2d5 Convert some helper functions to use StringRef.
I will probably submit a lot of small trivial changes
like this over the coming weeks.  The end goal is to
convert Options::SetOptionValue to take the option arg
as a StringRef, but doing so in one pass would be a huge
mess of disparate changes just to satisfy the compiler,
and with a high risk of breaking.  So I'm going to do
this in small pieces, changing seemingly random things
here and there until the final change to the signature
of Options::SetOptionValue() can be done trivially.

llvm-svn: 286088
2016-11-07 00:07:25 +00:00
Daniel Jasper de72a79511 Also delete the go side of the bindings deleted in r286085/r286086.
Also delete a comment I forgot to delete.

llvm-svn: 286087
2016-11-06 23:21:22 +00:00
Daniel Jasper 7ee8c309bd Delete one more function that needs to go after r286062.
llvm-svn: 286086
2016-11-06 21:20:45 +00:00
Daniel Jasper 7dbdb29d4a Remove functions from go bindings that have been deleted in r286062.
llvm-svn: 286085
2016-11-06 21:02:14 +00:00
Krzysztof Parzyszek 39d14f3bc3 Reapply r286080 with a phony change in Hexagon's CMakeLists.txt
Cmake has not recognized that Hexagon.td has a new dependency in
HexagonPatterns.td. All changes to that file were not visible to
the build bots.

llvm-svn: 286084
2016-11-06 20:55:57 +00:00
Davide Italiano cc7376290d [RandomNumberGenerator] Remove MSVC 2013 compatibility hack.
llvm-svn: 286083
2016-11-06 20:55:40 +00:00
Saleem Abdulrasool 804e12eeb5 ARM: lower fpowi appropriately for Windows ARM
This handles the last case of the builtin function calls that we would
generate code which differed from Microsoft's ABI.  Rather than
generating a call to `__pow{d,s}i2` we now promote the parameter to a
float or double and invoke `powf` or `pow` instead.

Addresses PR30825!

llvm-svn: 286082
2016-11-06 19:46:54 +00:00
Krzysztof Parzyszek f8d38d11b9 Revert r286080: it breaks build bots
llvm-svn: 286081
2016-11-06 19:36:09 +00:00
Krzysztof Parzyszek 9e3520c884 [Hexagon] Remove redundant custom selection code
The clr/set/toggle-bit instructions (with the bit index given as an
immediate operand) had both, custom selection code that generated them,
and selection patterns at the same time. The selection patterns were
not used, because the custom selection code was executed first.
This patch removes the custom code in favor of the selection patterns.
The custom code handled 64-bit registers as well with an immediate bit
index, and so new patterns were added to implement that.

It was also the same case for the instruction "Rd += asr(Rs, Rt)",
except that the custom code did not offer any additional functionality,
and was simply removed.

llvm-svn: 286080
2016-11-06 19:03:38 +00:00
Krzysztof Parzyszek c93815ef04 [Hexagon] Round 5 of selection pattern simplifications
Remove unnecessary type casts in patterns.

llvm-svn: 286079
2016-11-06 18:13:14 +00:00
Krzysztof Parzyszek f914278f8b [Hexagon] Round 4 of selection pattern simplifications
Give simpler or more meaningful names to pat frags and xforms.

llvm-svn: 286078
2016-11-06 18:09:56 +00:00
Krzysztof Parzyszek 846597d081 [Hexagon] Round 3 of selection pattern simplifications
Remove unnecessary C++ functions for SDNode transforms. Move more
pat frags to files where they are used.

llvm-svn: 286077
2016-11-06 18:05:14 +00:00
Krzysztof Parzyszek 84755104b4 [Hexagon] Round 2 of selection pattern simplifications
Add pat frags for any-, sign-, and zero-extensions.

llvm-svn: 286076
2016-11-06 17:56:48 +00:00
Simon Pilgrim 39df78e384 [SelectionDAG] Add support for vector demandedelts in XOR opcodes
llvm-svn: 286075
2016-11-06 16:49:19 +00:00
Simon Pilgrim 3ac353cb51 [X86] Add knownbits vector xor test
In preparation for demandedelts support

llvm-svn: 286074
2016-11-06 16:36:29 +00:00
Craig Topper 46de41330c [AVX-512] Remove intrinsics for 128/256-bit masked variable shift. Instead upgrade them to a select and the older AVX2 intrinsic.
llvm-svn: 286073
2016-11-06 16:29:19 +00:00
Craig Topper af9b3fe752 [AVX-512] Remove intrinsics for 128/256-bit masked shift by immediate. Instead upgrade them to a select and the older SSE/AVX2 intrinsic.
llvm-svn: 286072
2016-11-06 16:29:14 +00:00
Simon Pilgrim dd4809a603 [SelectionDAG] Add support for vector demandedelts in OR opcodes
llvm-svn: 286071
2016-11-06 16:29:09 +00:00
Craig Topper c9467ed31e [AVX-512] Remove intrinsics for 128/256-bit masked shift by single element in xmm. Instead upgrade them to a select and the older SSE/AVX2 intrinsic.
llvm-svn: 286070
2016-11-06 16:29:08 +00:00
Craig Topper 1b468b4e3a [AVX-512] Remove a 512-bit test cases from the avx512vl test file. It already exists in the avx512f test file.
llvm-svn: 286069
2016-11-06 16:29:03 +00:00
Simon Pilgrim c104185580 [X86] Add knownbits vector or test
In preparation for demandedelts support

llvm-svn: 286068
2016-11-06 16:05:59 +00:00