a7ec2dcefd
Some first rudimentary support for ARM EHABI: print exception table in "text mode".
...
llvm-svn: 127099
2011-03-05 18:43:15 +00:00
00d09428fe
Remove unused conditional negate operations.
...
llvm-svn: 127090
2011-03-05 16:54:31 +00:00
369ea3fdb4
ptx: add basic intrinsic support
...
llvm-svn: 127084
2011-03-05 14:17:37 +00:00
641e2d4f8c
Increased the register pressure limit on x86_64 from 8 to 12
...
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.
Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.
Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.
llvm-svn: 127067
2011-03-05 08:00:22 +00:00
27c079e1b0
whitespace
...
llvm-svn: 127065
2011-03-05 06:31:54 +00:00
88842e4574
Initialize variable.
...
llvm-svn: 127038
2011-03-04 21:38:47 +00:00
434248a62c
Improve div/rem node handling on mips. Patch by Akira Hatanaka
...
llvm-svn: 127034
2011-03-04 21:03:24 +00:00
a744ef3f90
Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka
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llvm-svn: 127032
2011-03-04 20:48:08 +00:00
8887d6593f
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic
...
llvm-svn: 127029
2011-03-04 20:27:44 +00:00
f8198e4311
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
...
llvm-svn: 127027
2011-03-04 20:01:52 +00:00
328e2ce043
Fix an old copy-n-paste
...
llvm-svn: 127020
2011-03-04 19:20:24 +00:00
a0d73fd65e
Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global.
...
llvm-svn: 127019
2011-03-04 19:11:05 +00:00
22b69db8dd
Expands FCOS and FSIN nodes when type is f64.
...
llvm-svn: 127017
2011-03-04 18:54:14 +00:00
db93ddb41b
Fixes addc pattern when immediate cannot be represented with 16-bit. Patch by Akira Hatanaka
...
llvm-svn: 127005
2011-03-04 17:59:18 +00:00
ed874eff93
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
...
llvm-svn: 127003
2011-03-04 17:51:39 +00:00
a1d947dd14
Allow vector shifts (shl,lshr,ashr) on SPU.
...
There was a previous implementation with patterns that would
have matched e.g.
shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.
llvm-svn: 126998
2011-03-04 13:19:18 +00:00
3531e9b0d9
Allow load from constant on SPU.
...
A 'load <4 x i32>* null' crashes llc before this fix.
llvm-svn: 126995
2011-03-04 12:00:11 +00:00
f63614a982
PR9377: Handle x86 str with register operand in a way consistent with gas.
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llvm-svn: 126970
2011-03-04 00:10:17 +00:00
f5d23beff7
PR8053: Fix encoding of S bit in some ARM instructions.
...
Patch by Zonr Chang!
llvm-svn: 126967
2011-03-03 23:07:15 +00:00
af52c52569
Optimize fprintf -> iprintf if there are no floating point arguments
...
and siprintf is available on the target.
llvm-svn: 126940
2011-03-03 14:20:22 +00:00
8e9a126a6c
PTX: Fix Emacs renaming a symbol
...
llvm-svn: 126938
2011-03-03 14:09:40 +00:00
2dfb888392
Optimize sprintf -> siprintf if there are no floating point arguments
...
and siprintf is available on the target.
llvm-svn: 126937
2011-03-03 14:09:28 +00:00
969dfbcff6
PTX: Fix a couple of lint violations
...
llvm-svn: 126936
2011-03-03 13:34:29 +00:00
815de536e5
Optimize printf -> iprintf if there are no floating point arguments
...
and iprintf is available on the target. Currently iprintf is only
marked as being available on the XCore.
llvm-svn: 126935
2011-03-03 13:17:51 +00:00
3bc0bcf3ad
Use X86_thiscall calling convention for Win64 as well.
...
llvm-svn: 126934
2011-03-03 07:49:07 +00:00
ab8881accd
Add a readme entry for the redundant movw issue for pr9370.
...
llvm-svn: 126930
2011-03-03 06:39:09 +00:00
ec84568904
pr9367: Add missing predicated BLX instructions.
...
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.
llvm-svn: 126915
2011-03-03 01:41:01 +00:00
b8b6041734
Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
...
Patch by Ted Kremenek!
llvm-svn: 126895
2011-03-02 23:08:33 +00:00
e84af17b6e
Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard.
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llvm-svn: 126882
2011-03-02 21:20:09 +00:00
a3769f8021
Add Win64 thiscall calling convention.
...
llvm-svn: 126862
2011-03-02 19:29:22 +00:00
dd567b214b
[AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement
...
missing patterns for them.
Add a SIMD test subdirectory to hold tests for SIMD instruction
selection correctness and quality.
'
llvm-svn: 126845
2011-03-02 17:23:43 +00:00
7ed32cc51b
ptx: fix lint and compiler warnings
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llvm-svn: 126838
2011-03-02 07:58:46 +00:00
59515dc703
Add 64-bit addressing to PTX backend
...
- Add '64bit' sub-target option.
- Select 32-bit/64-bit loads/stores based on '64bit' option.
- Fix function parameter order.
Patch by Justin Holewinski
llvm-svn: 126837
2011-03-02 07:36:48 +00:00
65b1476031
Extend initial support for primitive types in PTX backend
...
- Allow i16, i32, i64, float, and double types, using the native .u16,
.u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.
Patch by Justin Holewinski
llvm-svn: 126824
2011-03-02 03:20:28 +00:00
c76ae9c8e0
Add datalayout information for the IEEE quad precision fp128 type.
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llvm-svn: 126780
2011-03-01 20:56:50 +00:00
3b1459b810
Narrow right shifts need to encode their immediates differently from a normal
...
shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
llvm-svn: 126723
2011-03-01 01:00:59 +00:00
0c6cb46ac1
add a note
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llvm-svn: 126719
2011-03-01 00:24:51 +00:00
ec0fc7d842
Fix .fpu printing in ARM assembly, regarding bug http://llvm.org/bugs/show_bug.cgi?id=8931
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llvm-svn: 126689
2011-02-28 22:04:27 +00:00
63b0d108a2
Add missing whitespace in the formatting.
...
llvm-svn: 126687
2011-02-28 21:45:12 +00:00
c93d207e8c
fix a signed comparison warning.
...
llvm-svn: 126682
2011-02-28 20:50:35 +00:00
20a1cbefad
[AVX] Add decode support for VUNPCKLPS/D instructions, both 128-bit
...
and 256-bit forms. Because the number of elements in a vector
does not determine the vector type (4 elements could be v4f32 or
v4f64), pass the full type of the vector to decode routines.
llvm-svn: 126664
2011-02-28 19:06:56 +00:00
58775fea6f
Fix the arm's disassembler for blx that was building an MCInst without the
...
needed two predicate operands before the imm operand.
llvm-svn: 126662
2011-02-28 18:46:31 +00:00
6e3d443646
Fix a typo which cause dag combine crash. rdar://9059537.
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llvm-svn: 126661
2011-02-28 18:45:27 +00:00
67c5c3e939
Support for byval parameters on ARM. Will be enabled by a forthcoming
...
patch to the front-end. Radar 7662569.
llvm-svn: 126655
2011-02-28 17:17:53 +00:00
612b85e58c
Add branch hinting for SPU.
...
The implemented algorithm is overly simplistic (just speculate all branches are
taken)- this is work in progress.
llvm-svn: 126651
2011-02-28 14:08:24 +00:00
75a800d3bf
Add preliminary support for .f32 in the PTX backend.
...
- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
to accept the float type.
- Add appropriate test cases.
Patch by Justin Holewinski
llvm-svn: 126636
2011-02-28 06:34:09 +00:00
25bddae404
Silence enum conversion warnings.
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llvm-svn: 126578
2011-02-27 18:13:53 +00:00
d4e5003a3f
Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs.
...
It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).
llvm-svn: 126568
2011-02-27 08:47:19 +00:00
26691d9660
Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic.
...
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible
It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.
llvm-svn: 126557
2011-02-26 22:48:07 +00:00
b2c80da4ae
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
...
llvm-svn: 126518
2011-02-25 21:41:48 +00:00
fcf51fd298
Roll out r126425 and r126450 to see if it fixes the failures on the buildbots.
...
llvm-svn: 126488
2011-02-25 16:30:32 +00:00
e3ecd5fb9b
Add patterns to use post-increment addressing for Neon VST1-lane instructions.
...
llvm-svn: 126477
2011-02-25 06:42:42 +00:00
a921dc5860
Fix typo.
...
llvm-svn: 126467
2011-02-25 01:29:29 +00:00
70d29634a9
Each prologue may have multiple vpush instructions to store callee-saved
...
D registers since the vpush list may not have gaps. Make sure the stack
adjustment instruction isn't moved between them. Ditto for vpop in
epilogues.
Sorry, can't reduce a small test case.
rdar://9043312
llvm-svn: 126457
2011-02-25 00:24:46 +00:00
0152b7bc7c
remove command line option debugging hook.
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llvm-svn: 126441
2011-02-24 21:53:03 +00:00
b037383a35
Enable DebugInfo support for COFF object files.
...
Patch by Nathan Jeffords!
llvm-svn: 126425
2011-02-24 21:04:00 +00:00
42f52e737e
Add XCore intrinsic for eeu instruction.
...
llvm-svn: 126384
2011-02-24 13:39:18 +00:00
3923466e82
Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memory
...
operands starts at index 2, not 1.
rdar://9045024
PR9305
llvm-svn: 126359
2011-02-24 02:36:52 +00:00
bfa5cc0e08
Add XCore intrinsic for clre instruction.
...
llvm-svn: 126322
2011-02-23 18:52:05 +00:00
4995b05f56
Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable
...
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.
llvm-svn: 126320
2011-02-23 18:35:59 +00:00
2c610aa3ed
Add XCore intrinsic for the setv instruction.
...
llvm-svn: 126315
2011-02-23 16:46:37 +00:00
12377e0947
Fix format for setc instruction.
...
llvm-svn: 126314
2011-02-23 15:20:16 +00:00
aab96995f6
Add XCore intrinsic for settw instruction.
...
llvm-svn: 126313
2011-02-23 14:45:03 +00:00
97e6428014
Change VFPNeonA8 definition to make the code easier to read.
...
llvm-svn: 126298
2011-02-23 02:35:33 +00:00
d6b641e5bc
More fcopysign correctness and performance fix.
...
The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.
The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
vmov.i32 d1, #0x80000000
vbsl d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702
llvm-svn: 126295
2011-02-23 02:24:55 +00:00
9a6040dc86
[AVX] General VUNPCKL codegen support.
...
llvm-svn: 126264
2011-02-22 23:31:46 +00:00
b7e635dcad
Use the same (%dx) hack for in[bwl] as for out[bwl].
...
llvm-svn: 126244
2011-02-22 20:40:09 +00:00
04ad35b53f
VFP single precision arith instructions can go down to NEON pipeline, but on Cortex-A8 only.
...
llvm-svn: 126238
2011-02-22 19:53:14 +00:00
e8a93fe8f0
Stack alignment is 16 bytes on FreeBSD/i386 too.
...
llvm-svn: 126226
2011-02-22 17:30:05 +00:00
666cf56668
Guard against de-referencing MBB.end().
...
llvm-svn: 126192
2011-02-22 07:07:59 +00:00
2ce663031f
available_externally (hidden or not) GVs are always accessed via stubs. rdar://9027648.
...
llvm-svn: 126191
2011-02-22 06:58:34 +00:00
919772fd5d
Only use blx for external function calls on thumb, these could be fixed
...
up by the dynamic linker, but it's better to use the correct instruction
to begin with.
Fixes rdar://9011034
llvm-svn: 126176
2011-02-22 01:37:10 +00:00
60e7629258
Recognize loopz and loopnz as aliases for loope and loopne.
...
From Dimitry Andric.
llvm-svn: 126168
2011-02-22 00:43:07 +00:00
e39062199e
Implement xgetbv and xsetbv.
...
Patch by Jai Menon.
llvm-svn: 126165
2011-02-22 00:35:18 +00:00
87a9f19f9c
Skipping over debugvalue instructions to determine whether the split spot is in a IT block. rdar://9030770
...
llvm-svn: 126159
2011-02-21 23:40:47 +00:00
f3292b2196
Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
...
In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working.
- The debugger needs to be aware of prolog_end attribute attached with line table entries.
- The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)
llvm-svn: 126155
2011-02-21 23:21:26 +00:00
5e8603d1b9
Fixed a bug in the X86 disassembler where a member of the
...
X86 instruction decode structure was being interpreted as
being in units of bits, although it is actually stored in
units of bytes.
llvm-svn: 126147
2011-02-21 21:55:05 +00:00
1ae65c7cb8
Add XCore intrinsics for various instructions on ports.
...
llvm-svn: 126132
2011-02-21 18:23:30 +00:00
bda7175a43
The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri.
...
llvm-svn: 126130
2011-02-21 17:37:17 +00:00
5237febf0c
a serious "compare CSE" issue that is nontrivial to get right,
...
but which is responsible for us doing really bad things to 256.bzip2.
llvm-svn: 126126
2011-02-21 17:03:47 +00:00
860abd0f28
Target/X86/X86FastISel: [PR6275] Fix Win32's dllimport function with fastisel.
...
"dllimport" function must not be GlobalVariable, but Function. It is enough to check with GlobalValue.
test/CodeGen/X86/dll-linkage.ll is updated to check llc -O0.
llvm-svn: 126110
2011-02-21 04:50:06 +00:00
a82203f875
Generate correct Sparc32 ABI compliant code for functions that return a struct.
...
llvm-svn: 126108
2011-02-21 03:42:44 +00:00
e9cba7bd34
add a missed loop deletion case.
...
llvm-svn: 126103
2011-02-21 02:13:39 +00:00
659c793a4e
add an idiom that loop idiom could theoretically catch.
...
llvm-svn: 126101
2011-02-21 01:33:38 +00:00
39314bdbc8
A lo/hi mul has higher latency than an imul r,ri, e.g. 5 cycles compared to 3
...
on Core 2 and Nehalem, so the code we generate is better than GCC's here.
llvm-svn: 126100
2011-02-21 01:29:32 +00:00
8731d0cc83
The signed version of our "magic number" computation for the integer approximation
...
of a constant had a minor typo introduced when copying it from the book, which
caused it to favor negative approximations over positive approximations in many
cases. Positive approximations require fewer operations beyond the multiplication.
In the case of division by 3, we still generate code that is a single instruction
larger than GCC's code.
llvm-svn: 126097
2011-02-21 00:22:02 +00:00
ac6b001f56
If both operands are loads from stores in memory we can't use movlpd/movlps
...
since one needs to be a register operand. Just use movss instead of forcing
an operand into a register.
Fixes PR9239
llvm-svn: 126072
2011-02-20 05:04:42 +00:00
ba1186c23e
Use explicit add_subdirectory's for LLVM target sublibraries instead
...
of testing for its presence at cmake time.
This way the build automatically regenerates the makefiles when a svn
update brings in a new sublibrary.
llvm-svn: 126068
2011-02-20 02:55:27 +00:00
78b9851a3a
Minor x86 README updates.
...
llvm-svn: 126054
2011-02-19 21:54:28 +00:00
47ffd35bea
implement PR9264: disambiguating 'bt mem, imm' as a btl.
...
This is reasonable to do since all bt-mem forms do the
same thing.
llvm-svn: 126047
2011-02-19 21:06:36 +00:00
c509ff6944
Fix typos.
...
llvm-svn: 126018
2011-02-19 03:19:09 +00:00
740467a245
Avoid dangling else warnings.
...
llvm-svn: 126004
2011-02-19 00:43:45 +00:00
1341df93f7
add a way to disable all builtins, wire it up to opt's -disable-simplifylibcalls flag.
...
llvm-svn: 125978
2011-02-18 22:34:03 +00:00
5ed962656c
Move library stuff out of the toplevel CMakeLists.txt file.
...
llvm-svn: 125968
2011-02-18 22:06:14 +00:00
0e125bb4d0
introduce a new TargetLibraryInfo pass, which transformations can use to
...
query about available library functions. For now this just has
memset_pattern16, which exists on darwin, but it can be extended for a
bunch of other things in the future.
llvm-svn: 125965
2011-02-18 21:50:34 +00:00
cdd20affec
Fix style and a typo
...
llvm-svn: 125949
2011-02-18 19:49:06 +00:00
9cd43977c3
Add assembly parsing support for "msr" and also fix its encoding. Also add
...
testcases for the disassembler to make sure it still works for "msr".
llvm-svn: 125948
2011-02-18 19:45:59 +00:00
0281731cc2
add a poor division by constant case.
...
llvm-svn: 125832
2011-02-18 05:35:49 +00:00
f69c80bac2
Recognize monitor/mwait with explicit register arguments
...
llvm-svn: 125805
2011-02-18 00:48:11 +00:00
889a508157
Recognize leavel and leaveq aliases for leave.
...
Validate encoding of leave in 64bit mode.
llvm-svn: 125795
2011-02-17 23:36:39 +00:00
Anton Korobeynikov