Commit Graph

80993 Commits

Author SHA1 Message Date
James Y Knight 89ac11de32 [Sparc] Add more instruction aliases.
These are mostly from the chart in the SparcV8 spec, section "A.3
Synthetic Instructions".

Differential Revision: http://reviews.llvm.org/D9834

llvm-svn: 241461
2015-07-06 16:01:07 +00:00
James Y Knight 7208a12eef [Sparc] Add support for flush instruction.
Differential Revision: http://reviews.llvm.org/D9833

llvm-svn: 241460
2015-07-06 16:01:04 +00:00
Rafael Espindola 76ad232179 Remove getRelocationAddress.
Originally added in r139314.

Back then it didn't actually get the address, it got whatever value the
relocation used: address or offset.

The values in different object formats are:

* MachO: Always an offset.
* COFF: Always an address, but when talking about the virtual address of
  sections it says: "for simplicity, compilers should set this to zero".
* ELF: An offset for .o files and and address for .so files. In the case of the
  .so, the relocation in not linked to any section (sh_info is 0). We can't
  really compute an offset.

Some API mappings would be:

* Use getAddress for everything. It would be quite cumbersome. To compute the
  address elf has to follow sh_info, which can be corrupted and therefore the
  method has to return an ErrorOr. The address of the section is also the same
  for every relocation in a section, so we shouldn't have to check the error
  and fetch the value for every relocation.

* Use a getValue and make it up to the user to know what it is getting.

* Use a getOffset and:
 * Assert for dynamic ELF objects. That is a very peculiar case and it is
   probably fair to ask any tool that wants to support it to use ELF.h. The
   only tool we have that reads those (llvm-readobj) already does that. The
   only other use case I can think of is a dynamic linker.
 * Check that COFF .obj files have sections with zero virtual address spaces. If
   it turns out that some assembler/compiler produces these, we can change
   COFFObjectFile::getRelocationOffset to subtract it. Given COFF format,
   this can be done without the need for ErrorOr.

The getRelocationAddress method was never implemented for COFF. It also
had exactly one use in a very peculiar case: a shortcut for adding the
section value to a pcrel reloc on MachO.

Given that, I don't expect that there is any use out there of the C API. If
that is not the case, let me know and I will add it back with the implementation
inlined and do a proper deprecation.

llvm-svn: 241450
2015-07-06 14:55:37 +00:00
Chad Rosier 85a346395e Fix a bug in the A57FPLoadBalancing register tracking/scavenger.
The code in AArch64A57FPLoadBalancing::scavengeRegister() to handle dead defs
was not correctly handling aliased registers.  E.g. if the dead def was of D2,
then S2 was not being marked as unavailable, so it could potentially be used
across a live-range in which it would be clobbered.

Patch by Geoff Berry <gberry@codeaurora.org>!
Phabricator: http://reviews.llvm.org/D10900

llvm-svn: 241449
2015-07-06 14:46:34 +00:00
Rafael Espindola 76d650e8d7 Check that COFF .obj files have sections with zero virtual address spaces.
When talking about the virtual address of sections the coff spec says:
  ... for simplicity, compilers should set this to zero. Otherwise, it is an
  arbitrary value that is subtracted from offsets during relocation.

We don't currently subtract it, so check that it is zero.

If some producer does create such files, we can change getRelocationOffset
instead.

llvm-svn: 241447
2015-07-06 14:26:07 +00:00
Asaf Badouh c6f3c82ffc [X86][AVX512] Multiply Packed Unsigned Integers with Round and Scale
pmulhrsw

review:
http://reviews.llvm.org/D10948

llvm-svn: 241443
2015-07-06 14:03:40 +00:00
Petar Jovanovic 0326a06c15 [Mips] Add support for MCJIT for MIPS32r6
Add support for resolving MIPS32r6 relocations in MCJIT.

Patch by Vladimir Radosavljevic.

Differential Revision: http://reviews.llvm.org/D10687

llvm-svn: 241442
2015-07-06 12:50:55 +00:00
Craig Topper d26d2d9a50 [TableGen] Change a couple methods to return an ArrayRef instead of a const std::vector reference. NFC
llvm-svn: 241430
2015-07-06 06:23:01 +00:00
Sanjay Patel cc9fad0bf7 remove unnecessary temp variable; NFCI
llvm-svn: 241415
2015-07-05 21:21:47 +00:00
Peter Collingbourne 46eb0f539c Verifier: Forbid comdats on linker declarations.
Differential Revision: http://reviews.llvm.org/D10945

llvm-svn: 241414
2015-07-05 20:52:40 +00:00
Peter Collingbourne 6a9d1774d0 IR: Do not consider available_externally linkage to be linker-weak.
From the linker's perspective, an available_externally global is equivalent
to an external declaration (per isDeclarationForLinker()), so it is incorrect
to consider it to be a weak definition.

Also clean up some logic in the dead argument elimination pass and clarify
its comments to better explain how its behavior depends on linkage,
introduce GlobalValue::isStrongDefinitionForLinker() and start using
it throughout the optimizers and backend.

Differential Revision: http://reviews.llvm.org/D10941

llvm-svn: 241413
2015-07-05 20:52:35 +00:00
Sanjay Patel a4860f3af2 use range-based for loops; NFCI
llvm-svn: 241412
2015-07-05 20:15:21 +00:00
Benjamin Kramer 9bfb627a0e [TargetLowering] StringRefize asm constraint getters.
There is some functional change here because it changes target code from
atoi(3) to StringRef::getAsInteger which has error checking. For valid
constraints there should be no difference.

llvm-svn: 241411
2015-07-05 19:29:18 +00:00
Asaf Badouh 73f26f8ffc [x86][AVX512] add Multiply High Op
include encoding and intrinsics tests.

review
http://reviews.llvm.org/D10896

llvm-svn: 241406
2015-07-05 12:23:20 +00:00
Michael Kuperstein 5f05153fbb [X86] Fix incorrect/inefficient pushw encodings for x86-64 targets
Correctly support assembling "pushw $imm8" on x86-64 targets. 
Also some cleanup of the PUSH instructions (PUSH64i16 and PUSHi16 actually
represent the same instruction)

This fixes PR23996

Patch by: david.l.kreitzer@intel.com
Differential Revision: http://reviews.llvm.org/D10878

llvm-svn: 241404
2015-07-05 10:25:41 +00:00
Nemanja Ivanovic d358b8f80d Add missing builtins to the PPC back end for ABI compliance (vol. 2)
This patch corresponds to review:
http://reviews.llvm.org/D10874

Back end portion of the second round of additions to altivec.h.

llvm-svn: 241398
2015-07-05 06:03:51 +00:00
Sanjay Patel f73f8919ed use range-based for loops; NFCI
llvm-svn: 241395
2015-07-04 19:38:52 +00:00
Simon Pilgrim ea1b6ee366 [X86][SSE] Improved i8/i16 to f64 uint2fp vector conversions
Followup to D10433 and D10589 that fixes i8/i16 uint2fp vector conversions by zero extending to i32 and using the sint2fp path (unless the target does actually support uint2fp).

llvm-svn: 241394
2015-07-04 15:33:34 +00:00
Sanjay Patel 82db3b7d5e use valid bits to avoid unnecessary machine trace metric recomputations
Although this does cut the number of traces recomputed by ~10% for the
test case mentioned in http://reviews.llvm.org/D10460, it doesn't
make a dent in the overall performance. That example needs to be more
selective when invalidating traces.

llvm-svn: 241393
2015-07-04 15:00:28 +00:00
Yaron Keren fffc068d68 Fix spelling, NFC.
llvm-svn: 241392
2015-07-04 05:48:52 +00:00
Peter Collingbourne 17eff10f68 LTO: expose LTO_SYMBOL_ALIAS, which indicates that the symbol is an alias.
This is needed for COFF linkers to distinguish between weak external aliases
and regular symbols with LLVM weak linkage, which are represented as strong
symbols in COFF.

llvm-svn: 241389
2015-07-04 03:42:35 +00:00
Rui Ueyama d5297ee724 Object/COFF: Do not rely on VirtualSize being 0 in object files.
llvm-svn: 241387
2015-07-04 03:25:51 +00:00
Lang Hames 78937c2ae5 [RuntimeDyld] Skip relocations for external symbols with 64-bit address ~0ULL.
Requested by Eugene Rozenfeld of the LLILC team, this feature allows JIT
clients to skip relocations for selected external symbols by returning ~0ULL
from their symbol resolver. If this value is returned for a given symbol,
RuntimeDyld will skip all relocations for that symbol. The client will be
responsible for applying the skipped relocations manually before the code
is executed.

llvm-svn: 241383
2015-07-04 01:35:26 +00:00
Craig Topper de8395229a [X86] Add proper 64-bit mode checks to jrcxz and jcxz.
llvm-svn: 241381
2015-07-04 00:01:07 +00:00
Matt Arsenault 24e33d10a0 AMDGPU: Fix indentation of switch
llvm-svn: 241380
2015-07-03 23:33:38 +00:00
Simon Atanasyan 5db0276925 [ELFYAML] Fix handling SHT_NOBITS sections by obj2yaml/yaml2obj tools
SHT_NOBITS sections do not have content in an object file. Now the yaml2obj
tool does not accept `Content` field for such sections, and the obj2yaml
tool does not attempt to read the section content from a file.

Restore r241350 and r241352.

llvm-svn: 241377
2015-07-03 23:00:54 +00:00
Rafael Espindola d74b4f0a32 Use a continue to reduce indentation.
llvm-svn: 241375
2015-07-03 22:02:28 +00:00
Rafael Espindola 74d079b272 Use a continue to reduce indentation.
llvm-svn: 241374
2015-07-03 21:57:41 +00:00
Rafael Espindola a88a196f04 Context is allocated just a few lines above. Don't check if it is null.
llvm-svn: 241373
2015-07-03 21:54:41 +00:00
Rafael Espindola a4b2733c86 Fix build with -DLLVM_USE_INTEL_JITEVENTS=ON -DLLVM_USE_OPROFILE=ON.
Is anyone using those?

llvm-svn: 241372
2015-07-03 21:47:00 +00:00
Filipe Cabecinhas 0011c58444 Remove always-true comparison, NFC.
Summary:
Looking at r241279, I noticed that UpgradedIntrinsics only gets written
to in the following code:

    if (UpgradeIntrinsicFunction(&F, NewFn))
      UpgradedIntrinsics[&F] = NewFn;

Looking through UpgradeIntrinsicFunction, we always return false OR
NewFn will be set to a different function from our source.

This patch pulls the F != NewFn into UpgradeIntrinsicFunction as an
assert, and removes the check from callers of UpgradeIntrinsicFunction.

Reviewers: rafael, chandlerc

Subscribers: llvm-commits-list

Differential Revision: http://reviews.llvm.org/D10915

llvm-svn: 241369
2015-07-03 20:12:01 +00:00
Rafael Espindola ed067c45d4 Return ErrorOr from getSymbolAddress.
It can fail trying to get the section on ELF and COFF. This makes sure the
error is handled.

llvm-svn: 241366
2015-07-03 18:19:00 +00:00
Rafael Espindola e2df87f24b Replace a few more MachO only uses of getSymbolAddress.
llvm-svn: 241365
2015-07-03 18:02:36 +00:00
Rafael Espindola dea0016f1e Use getValue instead of getAddress in a few MachO only cases.
In MachO the value of the symbol is always the address, so we can use the
simpler function.

llvm-svn: 241364
2015-07-03 17:44:18 +00:00
Rafael Espindola e9da9aa4f3 This reverts commit r241350 and r241352.
r241350 broke lld tests.
r241352 depends on r241350.

Original messages:
"[ELFYAML] Fix handling SHT_NOBITS sections by obj2yaml/yaml2obj tools"
"[ELFYAML] Make the Size field for .bss section optional"

llvm-svn: 241354
2015-07-03 14:54:02 +00:00
Simon Atanasyan d0f7b425a7 [ELFYAML] Make the Size field for .bss section optional
It's a common case to have a zero-size .bss section in an object file.

llvm-svn: 241352
2015-07-03 14:19:06 +00:00
Simon Atanasyan b776eaed2e [ELFYAML] Fix handling SHT_NOBITS sections by obj2yaml/yaml2obj tools
SHT_NOBITS sections do not have content in an object file. Now yaml2obj
tool does not accept `Content` field for such sections, and obj2yaml
tool does not attempt to read the section content from a file.

llvm-svn: 241350
2015-07-03 14:07:06 +00:00
Rafael Espindola d48e54c5ea Avoid a use after free.
llvm-svn: 241345
2015-07-03 12:20:34 +00:00
Simon Pilgrim b504263e4a [X86][SSE] Sign extension for target vector sizes less than 128 bits (pt2)
Add support for v2i8/v2i16 to v2f64 by using a sign extension to v2i32 before conversion to v2f64.

Differential Revision: http://reviews.llvm.org/D10589

llvm-svn: 241325
2015-07-03 08:01:36 +00:00
Yaron Keren 5dbf346c52 Initialize booleans CallsUnwindInit and CallsEHReturn with false instead of 0.
llvm-svn: 241324
2015-07-03 07:56:24 +00:00
Simon Pilgrim 385bf00ea2 [X86][SSE] Sign extension for target vector sizes less than 128 bits (pt1)
This patch adds support for sign extension for sub 128-bit vectors, such as to v2i32. It concatenates with UNDEF subvectors up to 128-bits, performs the sign extension (i.e. as v4i32) and then extracts the target subvector.

Patch 1/2 of D10589 - the second patch covers the conversion of v2i8/v2i16 to v2f64.

llvm-svn: 241323
2015-07-03 07:51:01 +00:00
Nadav Rotem 754eb7c563 Fix an overly aggressive assertion in getCopyFromPartsVector.
The assertion in getCopyFromPartsVector assumed that the vector 'part' must
match the type of argument (arguments are potentially split into multiple
parts). However, in some cases the targets return a 'part' of the right size
but with a different type. We already handle this case correctly later on
and generate a bitcast. This commit just makes sure that we are actually
checking the property that we care about.

llvm-svn: 241312
2015-07-02 23:23:52 +00:00
Adrian Prantl 18c073ad6b DIBuilder: Now that DICompileUnit is distinct, stop using temporary nodes
for the arrays.

llvm-svn: 241308
2015-07-02 22:32:52 +00:00
Akira Hatanaka 56c70441dc Use function attribute "trap-func-name" and remove TargetOptions::TrapFuncName.
This commit changes normal isel and fast isel to read the user-defined trap
function name from function attribute "trap-func-name" attached to llvm.trap or
llvm.debugtrap instead of from TargetOptions::TrapFuncName. This is needed to
use clang's command line option "-ftrap-function" for LTO and enable changing
the trap function name on a per-call-site basis.

Out-of-tree projects currently using TargetOptions::TrapFuncName to specify the
trap function name should attach attribute "trap-func-name" to the call sites
of llvm.trap and llvm.debugtrap instead.

rdar://problem/21225723

Differential Revision: http://reviews.llvm.org/D10832

llvm-svn: 241305
2015-07-02 22:13:27 +00:00
Akira Hatanaka 5c40eeabef Add functions for adding and testing string attributes to CallInst. NFC.
This change is needed later when I make changes to attach string function
attributes to llvm.trap and llvm.debugtrap.

llvm-svn: 241304
2015-07-02 22:08:48 +00:00
Dan Gohman bfaf7e15d1 [WebAssembly] Set the HasFloatingPointExceptions flag for WebAssembly.
llvm-svn: 241302
2015-07-02 21:36:25 +00:00
Rafael Espindola d0212cd46c Try to fix the build of IntelJITEventListener.
llvm-svn: 241301
2015-07-02 21:24:12 +00:00
Rafael Espindola 5d0c2ffadf Return ErrorOr from SymbolRef::getName.
This function can really fail since the string table offset can be out of
bounds.

Using ErrorOr makes sure the error is checked.

Hopefully a lot of the boilerplate code in tools/* can go away once we have
a diagnostic manager in Object.

llvm-svn: 241297
2015-07-02 20:55:21 +00:00
Bill Schmidt a1c30053e7 [PPC64LE] Remove implicit-subreg restriction from VSX swap removal
In r241285, I removed the SUBREG_TO_REG restriction from VSX swap
removal, determining that this was overly conservative.  We have
another form of the same restriction in that we check for the presence
of implicit subregs in vector operations.  As with SUBREG_TO_REG for
partial register conversions, an implicit subreg is safe in and of
itself, provided no other operation makes a lane-sensitive assumption
about the result.  This patch removes that restriction, by removing
the HasImplicitSubreg flag and all code that relies on it.

I've added a test case that fails to optimize before this patch is
applied, and optimizes properly with the patch.  Test based on a
report from Anton Blanchard.

llvm-svn: 241290
2015-07-02 19:01:22 +00:00
Bill Schmidt 7c691fee1c [PPC64LE] Teach swap optimization about the doubleword splat idiom
With a previous patch, the VSX swap optimization is able to recognize
the doubleword load-splat idiom that can be implemented using lxvdsx.
However, that does not cover a doubleword splat where the source is a
register.  We can implement this using xxspltd (a special form of
xxpermdi).  This patch teaches the swap optimization pass about this
idiom.

As a prerequisite, it also permits swap optimization to succeed for
all forms of SUBREG_TO_REG.  Previously we were conservative and only
allowed SUBREG_TO_REG when it copied a full register.  However, on
reflection any form of SUBREG_TO_REG is safe in and of itself, so long
as an unsafe operation is not performed on its result.  In particular,
a widening SUBREG_TO_REG often occurs as an input to a doubleword
splat idiom, particularly in auto-vectorized code.

The doubleword splat idiom is an XXPERMDI operation where both source
registers are identical, and the selection mask is either 0 (splat the
first element) or 3 (splat the second element).  To determine whether
the registers are identical, we use the existing mechanism for looking
through "copy-like" operations.  That mechanism has a side effect of
marking the XXPERMDI operation as using a physical register, which
would invalidate its presence in a swap-optimized region.  This is
correct for the form of XXPERMDI that performs a swap and hence would
be removed, but is not what we want for a doubleword-splat variety of
XXPERMDI.  Therefore we reset the physical-register flag on the
XXPERMDI when it represents a splat.

A simple test case is added to verify that we generate the splat and
that we also remove the xxswapd instructions that would otherwise be
associated with the load and store of another operand.

llvm-svn: 241285
2015-07-02 17:03:06 +00:00