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13600 Commits

Author SHA1 Message Date
Dan Gohman 6320f52ff4 Move the last uses of RetainFunc etc. over to using getRetainCallee() etc. 
so that a declaration for objc_retain is created when needed if it doesn't
already exist. rdar://9825114.

llvm-svn: 135821
 2011-07-22 22:29:21 +00:00
Jim Grosbach d69b3423a8 Add FIXME 
llvm-svn: 135819
 2011-07-22 22:15:38 +00:00
Jim Grosbach bc5d709ad9 ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX. 
llvm-svn: 135818
 2011-07-22 22:13:00 +00:00
Jim Grosbach e7e1e163db ARM assembly parsing and encoding updates. 
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.

llvm-svn: 135817
 2011-07-22 22:06:05 +00:00
Jim Grosbach 999afadffa ARM assembly parsing and encoding tests. 
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.

llvm-svn: 135810
 2011-07-22 21:34:56 +00:00
Bruno Cardoso Lopes 7a2075511b Fix test check! 
llvm-svn: 135802
 2011-07-22 20:55:28 +00:00
Bruno Cardoso Lopes a89039998d Fix PR10422 by adding the necessary AVX UCOMISD memory versions to 
load folding logic

llvm-svn: 135801
 2011-07-22 20:53:20 +00:00
Jim Grosbach 5b84e16503 ARM assembly parsing and encoding tests for SMLAWB/SMLAWT. 
llvm-svn: 135800
 2011-07-22 20:51:24 +00:00
Jim Grosbach e2220221a2 ARM assembly parsing and encoding tests. 
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.

llvm-svn: 135798
 2011-07-22 20:30:40 +00:00
Jim Grosbach 8dfcc0bb92 ARM assembly parsing and encoding of SMLAL instruction. 
Fix parsing of carry-setting variant SMLALS and add tests.

llvm-svn: 135797
 2011-07-22 20:18:21 +00:00
Jim Grosbach d7c8c35301 ARM encoding and assembly parsing of SMLAD{X} instructions. 
Fix encoding of destination register. Add tests.

llvm-svn: 135796
 2011-07-22 20:11:20 +00:00
Jim Grosbach 0b28f0cca2 ARM testcases for assembly parsing and encoding SMLA* instructions. 
llvm-svn: 135795
 2011-07-22 20:01:34 +00:00
Rafael Espindola 77242dd537 Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64 
too. Patch by Jeff Muizelaar.

llvm-svn: 135789
 2011-07-22 18:56:05 +00:00
Jim Grosbach d1f8bde10f ARM assembly parsing and encoding for SMC instruction. 
llvm-svn: 135782
 2011-07-22 18:13:31 +00:00
Jim Grosbach 24ace20824 ARM encoding and assembly parsing tests. 
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.

llvm-svn: 135780
 2011-07-22 18:04:48 +00:00
Jim Grosbach 0a547701a4 ARM assembly parsing and encoding for SETEND instruction. 
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.

llvm-svn: 135776
 2011-07-22 17:44:50 +00:00
Jim Grosbach 4535b9194a ARM assembly parsing and encoding tests for SEL instruction. 
llvm-svn: 135772
 2011-07-22 16:59:33 +00:00
Bruno Cardoso Lopes 612e56174b -Inspected a AVX code block added by someone in early Feb. This was never used 
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.

- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.

- Fix a fragile test and make it more useful.

llvm-svn: 135729
 2011-07-22 00:15:07 +00:00
Bruno Cardoso Lopes 14a95bda04 Although we already support this, add testcases for consistency 
llvm-svn: 135728
 2011-07-22 00:15:03 +00:00
Bruno Cardoso Lopes 91eff5140f Add a DAGCombine for transforming 128->256 casts into a simple 
vxorps + vinsertf128 pair of instructions

llvm-svn: 135727
 2011-07-22 00:15:00 +00:00
Dan Gohman e106aee6f5 Fix MergeInVectorType to check for vector types with the same alloc 
size but different element types, so that it filters out the cases
that CreateShuffleVectorCast doesn't handle. This fixes rdar://9786827.

llvm-svn: 135721
 2011-07-21 23:30:09 +00:00
Jim Grosbach 3354674b48 ARM parsing and encoding tests for SBC instruction. 
llvm-svn: 135718
 2011-07-21 23:03:59 +00:00
Jim Grosbach 8dbf59d041 ARM testcases for SADD/SASX parsing and encoding. 
llvm-svn: 135715
 2011-07-21 23:00:49 +00:00
Jim Grosbach 2a0320c877 ARM assembly parsing support for RSC instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135713
 2011-07-21 22:56:30 +00:00
Jim Grosbach 17806e6636 ARM assembly parsing support for RSB instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135712
 2011-07-21 22:37:43 +00:00
Jim Grosbach 2a22c06267 ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH. 
llvm-svn: 135710
 2011-07-21 22:29:23 +00:00
Jim Grosbach b31e60b7c6 ARM parsing and encodings tests for saturating arithmetic insns. 
llvm-svn: 135709
 2011-07-21 22:18:28 +00:00
Jim Grosbach 0a8d89242f ARM assembly parsing POP/PUSH mnemonics. 
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.

llvm-svn: 135702
 2011-07-21 19:57:11 +00:00
Jim Grosbach b2aa2c4a24 Add tests for ARM PKH assembly parsing. 
llvm-svn: 135696
 2011-07-21 19:02:03 +00:00
Bruno Cardoso Lopes 178fb40612 - Register v16i16 as valid VR256 register class 
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16

llvm-svn: 135663
 2011-07-21 02:24:08 +00:00
Bruno Cardoso Lopes b878caa5e2 Add support for 256-bit versions of VPERMIL instruction. This is a new 
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:

Instead of:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vextractf128  $1, %ymm0, %xmm1
  shufps  $1, %xmm1, %xmm1
  movss %xmm1, 28(%rsp)
  movss %xmm1, 24(%rsp)
  movss %xmm1, 20(%rsp)
  movss %xmm1, 16(%rsp)
  vextractf128  $0, %ymm0, %xmm0
  shufps  $1, %xmm0, %xmm0
  movss %xmm0, 12(%rsp)
  movss %xmm0, 8(%rsp)
  movss %xmm0, 4(%rsp)
  movss %xmm0, (%rsp)
  vmovaps (%rsp), %ymm0
We get:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vpermilps $85, %ymm0, %ymm0

llvm-svn: 135662
 2011-07-21 01:55:47 +00:00
Andrew Trick bd243d0dfe LSR, correct fix for rdar://9786536. Silly casting bug. 
llvm-svn: 135654
 2011-07-21 01:45:54 +00:00
Andrew Trick 858e9f083d LSR must sometimes sign-extend before generating double constants. 
rdar://9786536

llvm-svn: 135650
 2011-07-21 01:05:01 +00:00
Andrew Trick 8acb434402 LSR crashes on an empty IVUsers list. 
rdar://9786536

llvm-svn: 135644
 2011-07-21 00:40:04 +00:00
Devang Patel bcd50a10d5 While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value. 
llvm-svn: 135627
 2011-07-20 21:57:04 +00:00
Eli Friedman 0cdc148ab8 Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef. 
llvm-svn: 135625
 2011-07-20 21:37:47 +00:00
Eli Friedman ae60b6b008 Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389. 
llvm-svn: 135607
 2011-07-20 19:36:11 +00:00
Jim Grosbach 2ea9f25f5f Add parsing/encoding tests for ARM ORR instruction. 
llvm-svn: 135602
 2011-07-20 18:48:53 +00:00
Jim Grosbach a3fcb962eb Consolidate ARM NOP encoding test. 
llvm-svn: 135600
 2011-07-20 18:39:38 +00:00
Jim Grosbach 614e90a126 ARM parsing and encoding tests for MVN 
llvm-svn: 135599
 2011-07-20 18:37:08 +00:00
Jim Grosbach 8d11490771 ARM assembly parsing of MUL instruction. 
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.

llvm-svn: 135596
 2011-07-20 18:20:31 +00:00
Eli Friedman 6ed783228d PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS. 
llvm-svn: 135595
 2011-07-20 18:14:33 +00:00
Evan Cheng 76792992d6 Add MCObjectFileInfo and sink the MCSections initialization code from 
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!

llvm-svn: 135569
 2011-07-20 05:58:47 +00:00
Andrew Trick 638b355a16 indvars: Added getInsertPointForUses to find a valid place to truncate the IV. 
llvm-svn: 135568
 2011-07-20 05:32:06 +00:00
Eric Christopher 60648578ba New pointer rotate test. 
llvm-svn: 135562
 2011-07-20 03:09:11 +00:00
Andrew Trick f53622e129 indvars test case for r135558. 
llvm-svn: 135559
 2011-07-20 02:14:37 +00:00
Andrew Trick c5dd3e976a indvars -disable-iv-rewrite fix: derived GEP IVs 
llvm-svn: 135558
 2011-07-20 02:08:58 +00:00
Akira Hatanaka a4c09bce9b Lower memory barriers to sync instructions. 
llvm-svn: 135537
 2011-07-19 23:30:50 +00:00
Evan Cheng ccf243d56b Fix an obvious typo that's preventing x86 (32-bit) from using .literal16. 
llvm-svn: 135535
 2011-07-19 23:14:32 +00:00
Eli Friedman 55d6ccbb79 PR10386: Don't try to split an edge from an indirectbr. 
llvm-svn: 135534
 2011-07-19 22:59:41 +00:00