01b7cae58d
Fix parameter spelling: sse not sse1
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llvm-svn: 52185
2008-06-10 17:57:58 +00:00
07f4eecd2a
Fix some more quoting issues in RUN lines, this time regarding unintended
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variable expansions involving the $ character.
This fixes 4 tests that were not running properly before.
llvm-svn: 52183
2008-06-10 16:10:32 +00:00
400c49c781
Remove double pipes in RUN commandlines.
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This fixes 5 testcases that were not being run properly before.
llvm-svn: 52180
2008-06-10 15:11:36 +00:00
1b095b443c
Convert several tests to use temporary files instead of redundantly
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executing the test commands.
llvm-svn: 52163
2008-06-10 00:36:41 +00:00
29479df2ac
add support for PIC on linux x86-64
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llvm-svn: 52139
2008-06-09 09:52:31 +00:00
976b1eee81
Fix a memcpy lowering bug. Even though the memcpy alignment is smaller than the desired alignment, the frame destination alignment may still be larger than the desired alignment. Don't change its alignment to something smaller.
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llvm-svn: 51970
2008-06-04 23:37:54 +00:00
92d62b43c2
Fix the position of MemOperands in nodes that use variadic_ops
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in DAGISelEmitter output. This bug was recently uncovered by the
addition of patterns for CALL32m and CALL64m, which are nodes
that now have both MemOperands and variadic_ops.
This bug was especially visible with PIC in various configurations,
because the new patterns are matching the indirect call code used
in many PIC configurations.
llvm-svn: 51877
2008-06-02 17:40:38 +00:00
96af4ddb62
Add patterns for CALL32m and CALL64m. They aren't matched in most
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cases due to an isel deficiency already noted in
lib/Target/X86/README.txt, but they can be matched in this fold-call.ll
testcase, for example.
This is interesting mainly because it exposes a tricky tblgen bug;
tblgen was incorrectly computing the starting index for variable_ops
in the case of a complex pattern.
llvm-svn: 51706
2008-05-29 21:50:34 +00:00
714663ab94
Expand small memmovs using inline code. Set the X86 threshold for expanding
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memmove to a more plausible value, now that it's actually being used.
llvm-svn: 51696
2008-05-29 19:42:22 +00:00
5e28227dbd
Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.
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llvm-svn: 51667
2008-05-29 08:22:04 +00:00
6892c5507f
Add nounwind.
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llvm-svn: 51665
2008-05-29 07:09:24 +00:00
68079268f5
Fix PR2289: vr defined by multiple implicit_def as result of coalescing.
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llvm-svn: 51648
2008-05-28 17:40:10 +00:00
427412e7c8
Teach local register allocator to deal with landing pad MBB's.
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llvm-svn: 51647
2008-05-28 17:22:32 +00:00
221e9d0d22
Specify a target so that this tests tests what it's intended to test.
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llvm-svn: 51600
2008-05-27 17:55:57 +00:00
923a375053
Make this test independent of the target-triple; the stack alignment
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is specifically what this test depends on.
llvm-svn: 51599
2008-05-27 17:44:23 +00:00
213e114a2c
The Linux ABI emits an extra "movl %esp, %ebp" in function prologue and
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sometimes a "mov %ebp, %esp" in the epilogue.
Force these tests that rely on counting 'mov' to use i686-apple-darwin8.8.0
where they were written.
llvm-svn: 51568
2008-05-26 20:18:56 +00:00
948627aadd
New loadl_pd and loadh_pd tests.
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llvm-svn: 51525
2008-05-24 00:10:02 +00:00
04d24edcbb
Use movlps / movhps to modify low / high half of 16-byet memory location.
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llvm-svn: 51501
2008-05-23 21:23:16 +00:00
3388d022ac
Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add
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load-folding table entries for PMULDQ and PMULLD.
llvm-svn: 51489
2008-05-23 17:49:40 +00:00
f3be7a7ea7
Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed many 'ps' load folding patterns in X86InstrSSE.td which are missing the proper alignment checks.
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Also fixed some 80 col. violations.
llvm-svn: 51462
2008-05-23 00:37:07 +00:00
a1100782d5
Add a couple of test cases.
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llvm-svn: 51441
2008-05-22 21:19:19 +00:00
53963b775e
Add missing patterns.
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llvm-svn: 51435
2008-05-22 18:56:56 +00:00
a87f1a568c
testcase for PR2267
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llvm-svn: 51408
2008-05-22 04:45:22 +00:00
a5d27ae586
Fix PR2343. An *interesting* coalescer bug.
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BB1:
vr1025 = copy vr1024
..
BB2:
vr1024 = op
= op vr1025
<loop eventually branch back to BB1>
Even though vr1025 is copied from vr1024, it's not safe to coalesced them since live range of vr1025 intersects the def of vr1024. This happens when vr1025 is assigned the value of the previous iteration of vr1024 in the loop.
llvm-svn: 51394
2008-05-21 22:34:12 +00:00
1e427c3264
sabre brings to my attention that the 'tr' suffix is also obsolete
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llvm-svn: 51349
2008-05-20 21:00:03 +00:00
f45ff35bfe
Rename the last test with .llx extension to .ll, resolve duplicate test by renaming to isnan2. Now that no test has llx ending there is no need to search for them from dg.exp too.
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llvm-svn: 51328
2008-05-20 19:52:04 +00:00
cd2e772d08
Run vortex-bug as x86-64, which is what the original bug was triggered on.
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llvm-svn: 51289
2008-05-20 00:54:39 +00:00
0bf92b14f1
Use common where we mean common, not weak.
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llvm-svn: 51173
2008-05-16 00:52:30 +00:00
0a0fa7cf78
Fix a bug in LoopStrengthReduce that caused it to emit IR with
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use-before-def. The problem comes up in code with multiple PHIs where
one PHI is being rewritten in terms of the other, but the other needs
to be casted first. LLVM rules requre the cast instruction to be
inserted after any PHI instructions, but when instructions were
inserted to replace the second PHI value with a function of the first,
they were ended up going before the cast instruction. Avoid this
problem by remembering the location of the cast instruction, when one
is needed, and inserting the expansion of the new value after it.
This fixes a bug that surfaced in 255.vortex on x86-64 when
instcombine was removed from the middle of the loop optimization
passes.
llvm-svn: 51169
2008-05-15 23:26:57 +00:00
3ab94df276
When bit-twiddling CondCode values for integer comparisons produces
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SETOEQ, is it does with (SETEQ & SETULE), map it to SETEQ.
llvm-svn: 51112
2008-05-14 18:17:09 +00:00
1120279ae6
Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset.
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pshufd $1, (%rdi), %xmm0
movd %xmm0, %eax
=>
movl 4(%rdi), %eax
llvm-svn: 51026
2008-05-13 08:35:03 +00:00
3f40c69083
On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16.
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llvm-svn: 51019
2008-05-13 00:54:02 +00:00
b980f6fb3d
Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.
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llvm-svn: 51008
2008-05-12 23:04:07 +00:00
e6942c31ea
New test for tail merging
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llvm-svn: 51007
2008-05-12 22:59:44 +00:00
71b9afb053
When transforming a vector_shuffle to a load, the base address must not be an undef.
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llvm-svn: 50940
2008-05-10 06:46:49 +00:00
9c4d685165
Add nounwind.
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llvm-svn: 50931
2008-05-10 02:22:25 +00:00
bec201fa06
If all sources of a PHI node are defined by an implicit_def, just emit an implicit_def instead of a copy.
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llvm-svn: 50927
2008-05-10 00:17:50 +00:00
867af2678f
Add a pattern to do move the low element of a v4f32 and zero extend the rest.
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llvm-svn: 50922
2008-05-09 23:37:55 +00:00
961339bbdb
Handle a few more cases of folding load i64 into xmm and zero top bits.
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Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.
llvm-svn: 50918
2008-05-09 21:53:03 +00:00
0352e63e39
Simplify test.
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llvm-svn: 50911
2008-05-09 19:56:32 +00:00
0360ecbec1
Use movq to move low half of XMM register and zero-extend the rest.
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llvm-svn: 50874
2008-05-08 22:35:02 +00:00
78af38c392
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.
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llvm-svn: 50838
2008-05-08 00:57:18 +00:00
0d6311d46c
Add nounwind.
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llvm-svn: 50837
2008-05-07 22:59:08 +00:00
7ca4a67ca1
Yet another nasty spiller bug.
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%ecx = op
store %cl<kill>, (addr)
(addr) = op %al
It's not safe to unfold the last operand and eliminate store even though %cl is marked kill. It's a sub-register use which means one of its super-register(s) may be used below.
llvm-svn: 50794
2008-05-07 00:49:28 +00:00
f5d2c3b45a
Use target triple in tests, not 'realign-stack=0' option. Per request.
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llvm-svn: 50778
2008-05-06 23:09:29 +00:00
ef3faa1b1c
Fix PR2287. Darwin passes mmx values in register in 64-mode, not Linux.
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llvm-svn: 50716
2008-05-06 07:23:50 +00:00
3e58393c3d
Added addition atomic instrinsics and, or, xor, min, and max.
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llvm-svn: 50663
2008-05-05 19:05:59 +00:00
9c0c60d080
no need for eh info
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llvm-svn: 50658
2008-05-05 18:24:33 +00:00
bcde172222
Add AsmPrinter support for emitting a directive to declare that
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the code being generated does not require an executable stack.
Also, add target-specific code to make use of this on Linux
on x86.
llvm-svn: 50634
2008-05-05 00:28:39 +00:00
d9481366e3
Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.
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llvm-svn: 50619
2008-05-04 09:15:50 +00:00
Dale Johannesen