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Author SHA1 Message Date
Chris Lattner 894d2e6146 add a bunch of classes for other common patterns. 
As usual, no change in generated .inc files.

llvm-svn: 115882
 2010-10-07 00:35:28 +00:00
Owen Anderson 6da4d820fa Since the Hello pass is built as a loadable dynamic library, don't try to convert it to new-style registration yet. 
llvm-svn: 115881
 2010-10-07 00:31:16 +00:00
Chris Lattner e17d7212f1 Define a new BinOpRI8 class and use it to define the imm8 versions of and. 
llvm-svn: 115880
 2010-10-07 00:12:45 +00:00
Jakob Stoklund Olesen b19bae4e3e Constrain the offset register to a *_NOSP register class when inserting LEA 
instructions.

This unbreaks the machine code verifier and fixes PR8317.

llvm-svn: 115879
 2010-10-07 00:07:26 +00:00
Chris Lattner 356f16c142 add the pattern operator to match to X86TypeInfo, use this to 
convert AND64ri32 to use BinOpRI.

llvm-svn: 115878
 2010-10-07 00:01:39 +00:00
Jakob Stoklund Olesen b2dd88db6b Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass. 
This function looks like it is about ready to be generated by TebleGen.

llvm-svn: 115876
 2010-10-06 23:56:46 +00:00
Jakob Stoklund Olesen 18842783cc Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE. 
This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.

llvm-svn: 115875
 2010-10-06 23:54:39 +00:00
Jakob Stoklund Olesen 1a065e4e5b Skip unused registers when verifying LiveIntervals. 
llvm-svn: 115874
 2010-10-06 23:54:35 +00:00
Jim Grosbach 25cd3bfbd7 remove trailing whitespace 
llvm-svn: 115860
 2010-10-06 22:46:47 +00:00
Jason W Kim bff84d418f First in a sequence of ARM/MC/*ELF* specific work. 
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored

llvm-svn: 115859
 2010-10-06 22:36:46 +00:00
Rafael Espindola 883936ce0b Another case of 256 sections not being enough :-) 
llvm-svn: 115858
 2010-10-06 22:28:19 +00:00
Owen Anderson af08ad4350 Appease the clang self-host buildbot by providing a correct instantiation. 
llvm-svn: 115857
 2010-10-06 22:23:20 +00:00
Jim Grosbach 24ab1ce8c2 Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions. 
llvm-svn: 115853
 2010-10-06 22:01:26 +00:00
Jim Grosbach f49540cb4f Kill of the vestiges of the 'call' Modifier (no longer needed for PLT). 
llvm-svn: 115845
 2010-10-06 21:36:43 +00:00
Jim Grosbach 2c95027258 Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed 
"lane" operand modifier.

llvm-svn: 115843
 2010-10-06 21:22:32 +00:00
Jim Grosbach 2e3e2a006b Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be 
pseudo instructions.

llvm-svn: 115840
 2010-10-06 21:16:16 +00:00
Rafael Espindola 5f2d6a5cd9 Get binding and visibility info from the the alias, but Type from the symbol 
being aliased.

llvm-svn: 115836
 2010-10-06 21:02:29 +00:00
Owen Anderson ad8134f03b Hide analysis group registration behind a macro, just like pass registration. 
llvm-svn: 115835
 2010-10-06 21:02:27 +00:00
Devang Patel 9a33ec24eb Add support for DW_TAG_unspecified_parameters. 
llvm-svn: 115833
 2010-10-06 20:50:40 +00:00
Jim Grosbach 233b3a2f95 Add a 'pattern' arg to the ARM PseudoNeonI class. 
llvm-svn: 115831
 2010-10-06 20:36:55 +00:00
Michael J. Spencer e535b01a74 MC: Add missing forward in MCLoggingStreamer. 
llvm-svn: 115830
 2010-10-06 20:36:47 +00:00
Bill Wendling 5ed50b6151 Revert "RequiresUnique" patch. This should be handled at a lower level. 
llvm-svn: 115827
 2010-10-06 20:18:44 +00:00
Rafael Espindola d444577382 If a symbol is global, reloc against it even if it is in a mergeable section. 
llvm-svn: 115817
 2010-10-06 19:27:21 +00:00
Nick Lewycky ec0da969fb Remove unused variables. 
llvm-svn: 115802
 2010-10-06 18:11:50 +00:00
Jim Grosbach 8025f89860 target operand flag values aren't a bitmask 
llvm-svn: 115798
 2010-10-06 16:51:55 +00:00
Rafael Espindola 83b2a3337f Make sure weak symbols are listed after the local ones. 
llvm-svn: 115795
 2010-10-06 16:47:31 +00:00
Rafael Espindola 8f3d2c9058 Correctly handle GOTPCREL relocations. 
llvm-svn: 115793
 2010-10-06 16:23:36 +00:00
Dan Gohman aadc5596f1 ComputeLinearIndex doesn't need its TLI argument. 
llvm-svn: 115792
 2010-10-06 16:18:29 +00:00
Bill Wendling 10f60fa411 Change RequiresMerge to RequiresUnique. It's a better description of what this 
fix is trying to accomplish.

This code could still use some polishing.

llvm-svn: 115759
 2010-10-06 07:03:52 +00:00
Evan Cheng 49d4c0bd18 - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This 
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755
 2010-10-06 06:27:31 +00:00
Bill Wendling cd8fe46d4b If the destination module all ready has a copy of the global coming from the 
source module *and* it must be merged (instead of simply replaced or appended
to), then merge instead of replacing or adding another global.

The ObjC __image_info section was being appended to because of this
failure. This caused a crash because the linker expects the image info section
to be a specific size.

<rdar://problem/8198537>

llvm-svn: 115753
 2010-10-06 06:16:30 +00:00
Chris Lattner 6e85be2ecf enhance X86TypeInfo to include information about the encoding and 
operand kind for immediates.  Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it.  AND64ri32 needs some
more refactoring before it can make the switcheroo.

llvm-svn: 115752
 2010-10-06 05:55:42 +00:00
Chris Lattner 94eff91dc0 add a class for _REV nodes. 
llvm-svn: 115748
 2010-10-06 05:35:22 +00:00
Chris Lattner a46073b56b sink more intelligence into the ITy base class. Now it knows 
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).

llvm-svn: 115747
 2010-10-06 05:28:38 +00:00
Chris Lattner b6da2be7e8 refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info. 
llvm-svn: 115745
 2010-10-06 05:20:57 +00:00
Chris Lattner 7bbd809b6c with tblgen suitably extended, we can now get the load node from typeinfo. 
llvm-svn: 115744
 2010-10-06 04:58:43 +00:00
NAKAMURA Takumi ad205575fc lib/System/Win32/Signals.inc: Enable LLVM_DISABLE_CRT_DEBUG also on mingw. 
llvm-svn: 115731
 2010-10-06 02:15:22 +00:00
Bill Wendling 0198ce06fc Provide a fast "get me the target triple from the module" API. This can 
drastically reduce the linking time during LTO.

Patch by Shantonu Sen!

llvm-svn: 115728
 2010-10-06 01:22:42 +00:00
Chris Lattner 1fc81e90f7 lets go all meta and define new X86 type wrappers that declare the associated 
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)

llvm-svn: 115727
 2010-10-06 00:45:24 +00:00
Chris Lattner eadaeaab93 introduce a new BinOpRM class and use it to factor AND*rm. This points out 
that I need a heavier handed approach to get ultimate factorization.

llvm-svn: 115726
 2010-10-06 00:30:49 +00:00
Chris Lattner 9402633637 remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places 
where !cast is just as short.

llvm-svn: 115722
 2010-10-06 00:19:21 +00:00
Chris Lattner 04c342ea20 replace stuff like: 
let AsmString = !strconcat(
                     !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
                     !strconcat("\t", asm));

with:

  let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);

:)

llvm-svn: 115720
 2010-10-06 00:05:18 +00:00
Chris Lattner 61ea00b494 allow !strconcat to take more than two operands to eliminate 
!strconcat(!strconcat(!strconcat(!strconcat

Simplify some x86 td files to use it.

llvm-svn: 115719
 2010-10-05 23:58:18 +00:00
Rafael Espindola d7565c3a06 Use a relocation against the symbol if it is a PLT and the symbol is in another 
section. Common because of linkonce sections.

llvm-svn: 115718
 2010-10-05 23:57:26 +00:00
Eric Christopher b9f2d50d5f Comment out fastisel debugging message. 
llvm-svn: 115717
 2010-10-05 23:50:58 +00:00
Chris Lattner 97b1368ae3 associate the instruction suffix letter with the integer gpr 
register class, and use this to simplify use of BinOpRR.

llvm-svn: 115716
 2010-10-05 23:43:04 +00:00
Chris Lattner 7359194b63 introduce a new BinOpRR class, and convert 4 and instructions to use it. 
llvm-svn: 115715
 2010-10-05 23:32:05 +00:00
Eric Christopher 8cfc459274 Random cleanup and make the intermediate register in fptosi a 
32-bit fp reg, not 64-bit.

Fixes SingleSource.

llvm-svn: 115711
 2010-10-05 23:13:24 +00:00
Jakob Stoklund Olesen 4d5156c7d0 Count uses in all nested loops, not just the deepest. 
llvm-svn: 115710
 2010-10-05 23:10:12 +00:00
Jakob Stoklund Olesen 56e2925e6c Remove SplitAnalysis::removeUse. It was only used to make SplitAnalysis 
reusable, but that is no longer relevant since a split will always replace the
original.

llvm-svn: 115709
 2010-10-05 23:10:09 +00:00