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54 Commits

Author SHA1 Message Date
Simon Pilgrim 017f896adb [SelectionDAG] Add VSELECT demanded elts support to computeKnownBits 
llvm-svn: 316947
 2017-10-30 19:31:08 +00:00
Simon Pilgrim 28b6219bd6 [X86][SSE] Add another computeKnownBits test showing missing VSELECT demandedelts support 
llvm-svn: 316945
 2017-10-30 19:19:58 +00:00
Simon Pilgrim b81fbf44c7 [X86][SSE] computeKnownBits tests showing missing VSELECT demandedelts support 
llvm-svn: 316940
 2017-10-30 18:48:31 +00:00
Craig Topper d4341920d5 [X86] Teach execution domain fixing to convert between VPERMILPS and VPSHUFD. 
llvm-svn: 313507
 2017-09-18 03:29:47 +00:00
Simon Pilgrim 3c81c34d8d [DAGCombiner] Add vector demanded elements support to ComputeNumSignBits 
Currently ComputeNumSignBits returns the minimum number of sign bits for all elements of vector data, when we may only be interested in one/some of the elements.

This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original ComputeNumSignBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1.

I've only added support for BUILD_VECTOR and EXTRACT_VECTOR_ELT so far, all others will default to demanding all elements but can be updated in due course.

Followup to D25691.

Differential Revision: https://reviews.llvm.org/D31311

llvm-svn: 299219
 2017-03-31 13:54:09 +00:00
Simon Pilgrim 5a68d401c7 [SelectionDAG] Add SelectionDAG.computeKnownBits test support for ISD::ABS 
llvm-svn: 298108
 2017-03-17 17:45:36 +00:00
Simon Pilgrim d06b025c9c [X86] Add SelectionDAG.computeKnownBits test showing inability to handle ISD::ABS 
We have to be careful as abs(INT_MIN) == INT_MIN.

llvm-svn: 298103
 2017-03-17 16:58:15 +00:00
Simon Pilgrim 9f5c251d57 [X86][SSE] Lower 128-bit vectors to SIGN/ZERO_EXTEND_VECTOR_IN_REG ops 
As described on PR31712, we miss a variety of legalization combines because we lower these to X86ISD::VSEXT/VZEXT despite them having the same functionality. This patch makes 128-bit (SSE41) SIGN/ZERO_EXTEND_VECTOR_IN_REG ops legal, adds the necessary tablegen plumbing and uses a helper 'getExtendInVec' to decide when to use SIGN/ZERO_EXTEND_VECTOR_IN_REG or VSEXT/VZEXT.

We're missing a couple of shuffle combines that will be added in a future patch for review.

Later patches can then support the AVX2 cases as a mixture of SIGN/ZERO_EXTEND and SIGN/ZERO_EXTEND_VECTOR_IN_REG, and then finally deal with the AVX512 cases.

Differential Revision: https://reviews.llvm.org/D30549

llvm-svn: 296985
 2017-03-05 09:57:20 +00:00
Simon Pilgrim fb32eea1b4 [SelectionDAG] Improve knownbits handling of UMIN/UMAX (PR31293) 
This patch improves the knownbits logic for unsigned integer min/max opcodes.

For UMIN we know that the result will have the maximum of the inputs' known leading zero bits in the result, similarly for UMAX the maximum of the inputs' leading one bits.

This is particularly useful for simplifying clamping patterns,. e.g. as SSE doesn't have a uitofp instruction we want to use sitofp instead where possible and for that we need to confirm that the top bit is not set.

Differential Revision: https://reviews.llvm.org/D28853

llvm-svn: 292528
 2017-01-19 22:41:22 +00:00
Simon Pilgrim d0ccf5e2e3 [X86][SSE] Simplify umax knownbits test 
combineSRA doesn't detect sign bits splats that it does itself so just use -1 as the demanded input so that its already splatted

llvm-svn: 292361
 2017-01-18 11:20:31 +00:00
Simon Pilgrim 421f2d9af8 [X86][SSE] Split UMIN and UMAX known bits tests 
llvm-svn: 292277
 2017-01-17 22:12:25 +00:00
Simon Pilgrim 3e91519a1c [SelectionDAG] Add knownbits support for BITREVERSE 
llvm-svn: 292130
 2017-01-16 14:49:26 +00:00
Simon Pilgrim 355cd67d2d [X86][SSE] Test showing missing BITREVERSE knownbits support 
llvm-svn: 292118
 2017-01-16 13:59:42 +00:00
Simon Pilgrim 54945a12ec [SelectionDAG] Add ability for computeKnownBits to peek through bitcasts from 'large element' scalar/vector to 'small element' vector. 
Extension to D27129 which already supported bitcasts from 'small element' vector to 'large element' scalar/vector types.

llvm-svn: 289329
 2016-12-10 17:00:00 +00:00
Simon Pilgrim 017b7a71d8 [SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes (REAPPLIED) 
Reapplied with fix for PR31323 - X86 SSE2 vXi16 multiplies for illegal types were creating CONCAT_VECTORS nodes with vector inputs that might not total the number of elements in the result type.

llvm-svn: 289232
 2016-12-09 17:53:11 +00:00
Daniel Jasper f51e05ffbc Revert "[SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes" 
This reverts commit r288916 as it is currently causing a crasher in
Halide. Reproducer on llvm.org/PR31323. While it might be that halide is
generating invalid IR, llc shouldn't crash.

llvm-svn: 289194
 2016-12-09 09:04:51 +00:00
Simon Pilgrim ba05d41095 [SelectionDAG] Add knownbits support for vector demandedelts in SMAX/SMIN/UMAX/UMIN opcodes 
llvm-svn: 288926
 2016-12-07 17:54:00 +00:00
Simon Pilgrim ef76b83164 [X86] Add knownbits vector UMAX test 
In preparation for demandedelts support

llvm-svn: 288920
 2016-12-07 17:21:13 +00:00
Simon Pilgrim 967325b373 [SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes 
llvm-svn: 288916
 2016-12-07 16:28:21 +00:00
Simon Pilgrim b421ef2370 [X86] Add test to show missed opportunities to calculate knownbits in INSERT_VECTOR_ELT 
llvm-svn: 288912
 2016-12-07 15:27:18 +00:00
Simon Pilgrim 1577b39f51 [SelectionDAG] We can ignore knownbits from an undef shuffle vector index if we don't actually demand that element 
llvm-svn: 288839
 2016-12-06 18:58:25 +00:00
Simon Pilgrim 4a2979ce12 [X86][SSE] Add knownbits test demonstrating demandedelts not ignoring undef shuffle elements 
llvm-svn: 288825
 2016-12-06 17:00:47 +00:00
Simon Pilgrim 7c7b649639 [X86] Improve UMAX/UMIN knownbits test 
Test the sequential effect of each op

llvm-svn: 288815
 2016-12-06 15:17:50 +00:00
Simon Pilgrim ae63dd10f8 [X86] Add tests to show missed opportunities to calculate knownbits in SMAX/SMIN/UMAX/UMIN 
llvm-svn: 288801
 2016-12-06 12:12:20 +00:00
Simon Pilgrim 84b6f26eca [X86][SSE] Added knownbits through bitcast test 
llvm-svn: 287928
 2016-11-25 15:07:15 +00:00
Simon Pilgrim e40900dddd [SelectionDAG] Add knowbits support for CONCAT_VECTOR opcode 
llvm-svn: 287387
 2016-11-18 22:21:22 +00:00
Simon Pilgrim 3a5328ecdd [X86] Add knownbits concat_vector test 
Support coming in a future patch

llvm-svn: 287385
 2016-11-18 21:59:38 +00:00
Simon Pilgrim 807f9cf243 [SelectionDAG] Add support for vector demandedelts in BSWAP opcodes 
llvm-svn: 286582
 2016-11-11 11:51:29 +00:00
Simon Pilgrim 08dedfc589 [X86] Add knownbits vector BSWAP test 
In preparation for demandedelts support

llvm-svn: 286579
 2016-11-11 11:33:21 +00:00
Simon Pilgrim 813721e98a [SelectionDAG] Add support for vector demandedelts in UREM/SREM opcodes 
llvm-svn: 286578
 2016-11-11 11:23:43 +00:00
Simon Pilgrim 8bc531d349 [X86] Add knownbits vector UREM/SREM tests 
In preparation for demandedelts support

llvm-svn: 286577
 2016-11-11 11:11:40 +00:00
Simon Pilgrim 0652227814 [SelectionDAG] Add support for vector demandedelts in UDIV opcodes 
llvm-svn: 286576
 2016-11-11 10:47:24 +00:00
Simon Pilgrim da1a43e861 [X86] Add knownbits vector UDIV test 
In preparation for demandedelts support

llvm-svn: 286575
 2016-11-11 10:39:15 +00:00
Simon Pilgrim 38f0045cb0 [SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodes 
llvm-svn: 286516
 2016-11-10 22:41:49 +00:00
Simon Pilgrim a0dee61df3 [X86] Updated knownbits vector ADD/SUB test 
In preparation for demandedelts support

llvm-svn: 286513
 2016-11-10 22:34:12 +00:00
Simon Pilgrim 8bbfacaf2c [X86] Add knownbits vector ADD test 
llvm-svn: 286511
 2016-11-10 22:21:04 +00:00
Simon Pilgrim fe3a54371d [SelectionDAG] Add support for splatted vectors in SUB opcode 
llvm-svn: 286509
 2016-11-10 21:57:42 +00:00
Simon Pilgrim 7e0a4b8fdf [X86] Add knownbits vector SUB test 
llvm-svn: 286508
 2016-11-10 21:50:23 +00:00
Simon Pilgrim d67af68f06 [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodes 
llvm-svn: 286481
 2016-11-10 17:43:52 +00:00
Simon Pilgrim e517f0a417 [X86] Add knownbits vector TRUNC test 
In preparation for demandedelts support

llvm-svn: 286477
 2016-11-10 17:24:33 +00:00
Simon Pilgrim ee187fd6e7 [SelectionDAG] Add support for vector demandedelts in MUL opcodes 
llvm-svn: 286471
 2016-11-10 16:27:42 +00:00
Simon Pilgrim 2cf393c8fe [X86] Add knownbits vector MUL test 
In preparation for demandedelts support

llvm-svn: 286463
 2016-11-10 15:57:33 +00:00
Simon Pilgrim ca57e53ded [SelectionDAG] Add support for vector demandedelts in SRA opcodes 
llvm-svn: 286461
 2016-11-10 15:05:09 +00:00
Simon Pilgrim 7be6d99442 [X86] Add knownbits vector arithmetic shift test 
In preparation for demandedelts support

llvm-svn: 286457
 2016-11-10 14:46:24 +00:00
Simon Pilgrim 3bf99c056a [SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodes 
llvm-svn: 286448
 2016-11-10 13:52:42 +00:00
Simon Pilgrim ede8ad7c5a [X86] Add knownbits vector logical shift test 
In preparation for demandedelts support

llvm-svn: 286447
 2016-11-10 13:34:17 +00:00
Simon Pilgrim 39df78e384 [SelectionDAG] Add support for vector demandedelts in XOR opcodes 
llvm-svn: 286075
 2016-11-06 16:49:19 +00:00
Simon Pilgrim 3ac353cb51 [X86] Add knownbits vector xor test 
In preparation for demandedelts support

llvm-svn: 286074
 2016-11-06 16:36:29 +00:00
Simon Pilgrim dd4809a603 [SelectionDAG] Add support for vector demandedelts in OR opcodes 
llvm-svn: 286071
 2016-11-06 16:29:09 +00:00
Simon Pilgrim c104185580 [X86] Add knownbits vector or test 
In preparation for demandedelts support

llvm-svn: 286068
 2016-11-06 16:05:59 +00:00