c0a5aaeab0
[x86] Rename In32BitMode predicate to Not64BitMode
...
That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)
Patch by David Woodhouse
llvm-svn: 197768
2013-12-20 02:04:49 +00:00
47fc44e52e
AVX-512: Added legal type MVT::i1 and VK1 register for it.
...
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.
llvm-svn: 197384
2013-12-16 13:52:35 +00:00
9b5c3dcf01
Added new X86 patterns to select SSE scalar fp arithmetic instructions from
...
a vector packed single/double fp operation followed by a vector insert.
The effect is that the backend coverts the packed fp instruction
followed by a vectro insert into a SSE or AVX scalar fp instruction.
For example, given the following code:
__m128 foo(__m128 A, __m128 B) {
__m128 C = A + B;
return (__m128) {c[0], a[1], a[2], a[3]};
}
previously we generated:
addps %xmm0, %xmm1
movss %xmm1, %xmm0
we now generate:
addss %xmm1, %xmm0
llvm-svn: 197145
2013-12-12 11:50:47 +00:00
f7c33c8162
Ensure that the backend no longer emits unnecessary vector insert instructions
...
immediately after SSE scalar fp instructions like addss or mulss.
Added patterns to select SSE scalar fp arithmetic instructions from a scalar
fp operation followed by a blend.
For example, given the following code:
__m128 foo(__m128 A, __m128 B) {
A[0] += B[0];
return A;
}
previously we generated:
addss %xmm0, %xmm1
movss %xmm1, %xmm0
now we generate:
addss %xmm1, %xmm0
llvm-svn: 196925
2013-12-10 15:22:48 +00:00
c592e5251c
Add an intrinsic for the SSE2 PAUSE instruction.
...
llvm-svn: 195697
2013-11-26 00:20:43 +00:00
d1cd0be6f3
Fix assembly operands for the SSE2 cvtsd2ss instruction.
...
llvm-svn: 195129
2013-11-19 14:36:00 +00:00
be79768b6a
Lift alignment restrictions on load folding for a significant portion of AVX instructions.
...
llvm-svn: 194048
2013-11-05 06:31:43 +00:00
b638d05ecb
Fix PR17764
...
- When selecting BLEND from vselect, the operands need swapping as due to the
difference between vselect and SSE/AVX's BLEND insn
llvm-svn: 193900
2013-11-02 00:10:02 +00:00
0ccab2d66c
X86: Custom lower sext v16i8 to v16i16, and the corresponding truncate.
...
Also update the cost model.
llvm-svn: 193270
2013-10-23 21:06:07 +00:00
da8446b833
X86: Custom lower zext v16i8 to v16i16.
...
On sandy bridge (PR17654) we now get
vpxor %xmm1, %xmm1, %xmm1
vpunpckhbw %xmm1, %xmm0, %xmm2
vpunpcklbw %xmm1, %xmm0, %xmm0
vinsertf128 $1, %xmm2, %ymm0, %ymm0
On haswell it's a simple
vpmovzxbw %xmm0, %ymm0
There is a maze of duplicated and dead transforms and patterns in this
area. Remove the dead custom lowering of zext v8i16 to v8i32, that's
already handled by LowerAVXExtend.
llvm-svn: 193262
2013-10-23 19:19:04 +00:00
f7290f7194
Replace (V)MOVZDI2PDIrr/rm instructions with patterns that select (V)MOVDI2PDIrr/rm.
...
llvm-svn: 193146
2013-10-22 04:35:20 +00:00
2783993fca
X86 vector element shift-by-immediate instructions take i8 immediates. Make
...
the instruction defenitions and ISEL reflect this.
Prior to this patch these instructions took an i32i8imm, and the high bits were
dropped during encoding. This led to incorrect behavior for shifts by
immediates higher than 255. This patch fixes that issue by detecting large
immediate shifts and returning constant zero (for logical shifts) or capping
the shift amount at an encodable value (for arithmetic shifts).
Fixes <rdar://problem/14968098>
llvm-svn: 193096
2013-10-21 17:51:24 +00:00
ef9e993eaa
Remove x86_sse42_crc32_64_8 intrinsic. It has no functional difference from x86_sse42_crc32_32_8 and was not mapped to a clang builtin. I'm not even sure why this form of the instruction is even called out explicitly in the docs. Also add AutoUpgrade support to convert it into the other intrinsic with appropriate trunc and zext.
...
llvm-svn: 192672
2013-10-15 05:20:47 +00:00
d7abdb6f12
Create classes to reduce the size of the tablegen entries for the CRC32 instructions.
...
llvm-svn: 192568
2013-10-14 05:19:58 +00:00
a422b09ae3
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
...
llvm-svn: 192567
2013-10-14 04:55:01 +00:00
4432208884
Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
...
llvm-svn: 192566
2013-10-14 01:42:32 +00:00
7158745e55
Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.
...
llvm-svn: 192565
2013-10-14 01:21:22 +00:00
c4a5a3f65d
Don't use 64-bit versions of MOVMSKPD in CodeGen. The instructions only produce a 1-bit result so we can just use SUBREG_TO_REG to extend the 32-bit versions.
...
llvm-svn: 192562
2013-10-14 00:24:33 +00:00
aab53e7785
Mark some more instructions as CodeGenOnly. Remove filters from the disassembler.
...
llvm-svn: 192522
2013-10-12 04:46:18 +00:00
5fb5bd3373
Allow non-AVX form of pmovmskb to take a GR64 operand.
...
llvm-svn: 192341
2013-10-10 05:33:31 +00:00
3ada6deaac
Remove duplicate instructions.
...
llvm-svn: 192340
2013-10-10 05:01:22 +00:00
a3a714082b
AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.
...
llvm-svn: 192283
2013-10-09 08:16:14 +00:00
49d3319857
Mark some instructions as CodeGenOnly since they aren't needed by the assembler or disassembler. Disassembler already filtered them, but asm parser still had them in its tables.
...
llvm-svn: 192271
2013-10-09 03:56:16 +00:00
bc749db947
Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size.
...
llvm-svn: 192266
2013-10-09 02:18:34 +00:00
72c8cd7bc3
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
...
llvm-svn: 192171
2013-10-08 05:53:50 +00:00
07ad1b23bb
Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.
...
llvm-svn: 192090
2013-10-07 07:19:47 +00:00
68d2546ec6
Remove FsMOVAPSrr and friends. They have no patterns and are no longer selected anywhere.
...
llvm-svn: 192089
2013-10-07 06:10:45 +00:00
a0e0735e6a
Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not.
...
This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this.
llvm-svn: 192088
2013-10-07 05:42:48 +00:00
8f14de8f32
Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS is used in AVX512 mode.
...
llvm-svn: 191489
2013-09-27 07:16:24 +00:00
c6a1aac735
Removal some duplicate patterns.
...
llvm-svn: 191488
2013-09-27 07:11:17 +00:00
4467f33e3c
Fixing Intel format of the vshufpd instruction.
...
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759
llvm-svn: 191481
2013-09-27 01:44:23 +00:00
9a3915a74f
Lift alignment restrictions on load/store folding of VEXTRACTI128/VINSERTI128.
...
llvm-svn: 191073
2013-09-20 05:37:49 +00:00
98064b9f4d
Lift alignment restrictions for load/store folding on VINSERTF128/VEXTRACTF128. Fixes PR17268.
...
llvm-svn: 190916
2013-09-18 03:55:53 +00:00
de39520f79
Add llvm.x86.* intrinsics for Intel SHA Extensions
...
Add llvm.x86.* intrinsics for all of the Intel SHA Extensions instructions, as
well as tests. Also remove mayLoad and hasSideEffects, which can be inferred
from the instruction patterns.
llvm-svn: 190864
2013-09-17 13:44:39 +00:00
a6d204ec68
Make F16C feature flag imply AVX rather than just checking both at the patterns.
...
llvm-svn: 190775
2013-09-16 04:29:58 +00:00
8eb45a4ef6
Add the remaining Intel SHA instructions
...
Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit
xmm0 dependency.
llvm-svn: 190754
2013-09-14 15:03:21 +00:00
3fe264d625
Adds support for Atom Silvermont (SLM) - -march=slm
...
Implements Instruction scheduler latencies for Silvermont,
using latencies from the Intel Silvermont Optimization Guide.
Auto detects SLM.
Turns on post RA scheduler when generating code for SLM.
llvm-svn: 190717
2013-09-13 19:23:28 +00:00
1650175de6
Partial support for Intel SHA Extensions (sha1rnds4)
...
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.
Support for the remaining instructions will follow in a separate patch.
llvm-svn: 190611
2013-09-12 15:51:31 +00:00
8952974e29
AVX-512: implemented extractelement with variable index.
...
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.
llvm-svn: 190595
2013-09-12 08:55:00 +00:00
adbb9a121f
Add neverHasSideEffects=1 on a couple move instructions.
...
llvm-svn: 190259
2013-09-08 00:50:45 +00:00
9a5ed9c3bd
AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS
...
llvm-svn: 189472
2013-08-28 11:21:58 +00:00
93eeb47d49
AVX-512: added conversion instructions.
...
llvm-svn: 189349
2013-08-27 13:54:04 +00:00
0a2b6290f1
AVX-512: Added shuffle instructions -
...
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
single and double forms.
llvm-svn: 189215
2013-08-26 12:45:35 +00:00
540d582594
AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ
...
llvm-svn: 188786
2013-08-20 11:00:29 +00:00
fd2b389263
Move AVX and non-AVX replication inside a couple multiclasses to avoid repeating each instruction for both individually.
...
llvm-svn: 188743
2013-08-20 04:24:14 +00:00
3ce8dbbac2
AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions.
...
llvm-svn: 188637
2013-08-18 13:08:57 +00:00
5bc180c14f
X86: Turn fp selects into mask operations.
...
double test(double a, double b, double c, double d) { return a<b ? c : d; }
before:
_test:
ucomisd %xmm0, %xmm1
ja LBB0_2
movaps %xmm3, %xmm2
LBB0_2:
movaps %xmm2, %xmm0
after:
_test:
cmpltsd %xmm1, %xmm0
andpd %xmm0, %xmm2
andnpd %xmm3, %xmm0
orpd %xmm2, %xmm0
Small speedup on Benchmarks/SmallPT
llvm-svn: 187706
2013-08-04 12:05:16 +00:00
cd46691728
AVX-512 set: added VEXTRACTPS instruction
...
llvm-svn: 187705
2013-08-04 10:46:07 +00:00
67b05fc0b3
Added INSERT and EXTRACT intructions from AVX-512 ISA.
...
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.
llvm-svn: 187491
2013-07-31 11:35:14 +00:00
efd67d4612
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
...
Patch by Richard Mitton.
llvm-svn: 187476
2013-07-31 02:47:52 +00:00
6030a65039
Remove some errant space charcters in mnemonic strings.
...
llvm-svn: 186932
2013-07-23 06:45:34 +00:00
61da939a17
More Intel syntax alias fixes.
...
llvm-svn: 186814
2013-07-22 09:58:07 +00:00
03db790dc6
Change %xmm0 to XMM0 in Intel side of asm strings for PBLENDVB.
...
llvm-svn: 186812
2013-07-22 09:22:49 +00:00
89703c06f2
Removed PackedDouble domain from scalar instructions. Added more formats for the scalar stuff.
...
llvm-svn: 183626
2013-06-09 07:37:10 +00:00
00b20cc924
[PATCH] Fix VGATHER* operand constraints
...
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."
---
[1] http://software.intel.com/sites/default/files/319433-014.pdf
llvm-svn: 183327
2013-06-05 18:12:26 +00:00
fad029202f
Removed SSEPacked domain from all forms (AVX, SSE, signed, unsigned) scalar compare instructions, like COMISS, COMISD.
...
No functional changes.
llvm-svn: 182371
2013-05-21 12:04:22 +00:00
9264c95400
Corrected Atom latencies for SSE SQRT instructions.
...
llvm-svn: 181346
2013-05-07 19:57:34 +00:00
817c1d92b4
Put VMOVPQIto64rr in the VRPDI class.
...
Patch by Joshua Magee.
llvm-svn: 180842
2013-05-01 13:00:16 +00:00
aec90531f9
X86: Now that we have a canonical form for vector integer abs, match it into pabs.
...
llvm-svn: 180600
2013-04-26 12:05:21 +00:00
e440d476ee
Annotate the remaining x86 instructions with SchedRW lists.
...
Now all x86 instructions that have itinerary classes also have SchedRW
lists. This is required before the new scheduling models can be used.
There are still unannotated instructions remaining, but they don't have
itinerary classes either.
llvm-svn: 178051
2013-03-26 18:24:22 +00:00
4d39e81fb8
Remove IIC_DEFAULT from X86Schedule.td
...
All the instructions tagged with IIC_DEFAULT had nothing in common, and
we already have a NoItineraries class to represent untagged
instructions.
llvm-svn: 177937
2013-03-25 23:12:41 +00:00
712f674880
Model prefetches and barriers as loads.
...
It's not yet clear if these instructions need a more careful model.
llvm-svn: 177599
2013-03-20 23:09:53 +00:00
5b535c965e
Add a catch-all WriteSystem SchedWrite type.
...
This is used for all the expensive system instructions.
llvm-svn: 177598
2013-03-20 23:09:50 +00:00
cd4ebb7639
Annotate the remaining SSE MOV instructions.
...
llvm-svn: 177592
2013-03-20 22:37:16 +00:00
c6dc70d865
Annotate SSE horizontal and integer instructions.
...
llvm-svn: 177591
2013-03-20 22:37:13 +00:00
7a8bb72a3a
Add some missing SSE annotations.
...
llvm-svn: 177540
2013-03-20 16:56:39 +00:00
3a546156c7
Annotate various null idioms with SchedRW lists.
...
llvm-svn: 177461
2013-03-19 23:23:31 +00:00
24aac1dc92
Annotate SSE float conversions with SchedRW lists.
...
llvm-svn: 177460
2013-03-19 23:23:29 +00:00
a5158c8f0a
Add SchedRW annotations to most of X86InstrSSE.td.
...
We hitch a ride with the existing OpndItins class that was used to add
instruction itinerary classes in the many multiclasses in this file.
Use the link provided by the X86FoldableSchedWrite.Folded to find the
right SchedWrite for folded loads.
llvm-svn: 177326
2013-03-18 22:01:35 +00:00
adfa5eaf8c
Unaligned loads should use the VMOVUPS opcode.
...
llvm-svn: 177130
2013-03-14 23:49:44 +00:00
8fb09f0abb
Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction.
...
llvm-svn: 173667
2013-01-28 06:48:25 +00:00
c7e6feee42
Combine AVX and SSE forms of MOVSS and MOVSD into the same multiclasses so they get instantiated together.
...
llvm-svn: 172704
2013-01-17 06:59:42 +00:00
0d2c29e807
Simplify nested strconcats in X86 td files since strconcat can take more than 2 arguments.
...
llvm-svn: 172379
2013-01-14 07:46:34 +00:00
4c69a05d2d
Create a single multiclass for SSE and AVX version of MOVL/MOVH. Prevents needing to specify everything twice. No functional change intended
...
llvm-svn: 172378
2013-01-14 07:26:58 +00:00
bcd14a0f26
X86: Add patterns for X86ISD::VSEXT in registers.
...
Those can occur when something between the sextload and the store is on the same
chain and blocks isel. Fixes PR14887.
llvm-svn: 172353
2013-01-13 11:37:04 +00:00
bd62d64cbf
Remove unnecessary # tokens at the beginning and end of defm names.
...
llvm-svn: 171694
2013-01-07 05:04:39 +00:00
4f1c7256f9
Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior.
...
cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.
Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.
llvm-svn: 171668
2013-01-06 20:39:29 +00:00
9791afb182
Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP.
...
llvm-svn: 171356
2013-01-02 08:00:39 +00:00
4bc5c4e152
Merge SSE and AVX instruction definitions for PSHUFD/PSHUFHW/PSHUFLW.
...
llvm-svn: 171355
2013-01-02 07:27:49 +00:00
db1a84c84a
Revert 171351. It broke MC/X86/x86-32-avx.s.
...
llvm-svn: 171352
2013-01-02 01:35:11 +00:00
86d0cdb82f
Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP.
...
llvm-svn: 171351
2013-01-01 20:53:20 +00:00
12ed9cd6ae
Remove unused argument from a multiclass.
...
llvm-svn: 171340
2013-01-01 03:42:44 +00:00
2edafc059d
Merge intrinsic instruction definitions for SSE and AVX versions of RCPPS and RSQRTPS.
...
llvm-svn: 171339
2013-01-01 03:30:21 +00:00
d04dbec6c9
Remove 2 unused multiclasses.
...
llvm-svn: 171338
2013-01-01 02:02:45 +00:00
7cc4f322cf
Merge AVX/SSE instruction definitions for SQRTPS/PD, RSQRTPS, RCPPS. No funcitonal change intended.
...
llvm-svn: 171337
2013-01-01 00:11:07 +00:00
c2521cd309
Use packed instead of scalar itineraries for SSE1/2 SQRTPS/PD, RCPPS, and RSQRTPS. VEX-encoded forms already use packed.
...
llvm-svn: 171336
2012-12-31 23:49:05 +00:00
fe82eb6bcd
Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those.
...
llvm-svn: 171237
2012-12-29 18:18:20 +00:00
6b27251a76
Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled.
...
llvm-svn: 171227
2012-12-29 16:44:25 +00:00
ab2e6842cc
Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses.
...
llvm-svn: 171171
2012-12-27 22:53:47 +00:00
e2eec3c52b
Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses.
...
llvm-svn: 171166
2012-12-27 18:51:50 +00:00
757f3fc394
Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.
...
llvm-svn: 171143
2012-12-27 07:16:08 +00:00
09ce4b9efe
Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again.
...
llvm-svn: 171141
2012-12-27 06:34:54 +00:00
1b8c0750ee
Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier.
...
llvm-svn: 171118
2012-12-26 21:30:22 +00:00
18f2675e9b
Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns.
...
llvm-svn: 171117
2012-12-26 21:04:30 +00:00
24f316e4db
Merge still more SSE/AVX instruction definitions.
...
llvm-svn: 171103
2012-12-26 07:54:43 +00:00
af629e2700
Merge more SSE/AVX instruction definitions.
...
llvm-svn: 171102
2012-12-26 07:20:35 +00:00
65fe30450d
Fix 80 column violation.
...
llvm-svn: 171097
2012-12-26 06:15:53 +00:00
f4d0fe8fcd
Fix class name in comment.
...
llvm-svn: 171096
2012-12-26 06:15:09 +00:00
59747c4dbd
Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions.
...
llvm-svn: 171095
2012-12-26 06:14:15 +00:00
8a48677586
Remove 'v' from mnemonic to fix asm matching failures.
...
llvm-svn: 171093
2012-12-26 06:02:15 +00:00
Eric Christopher