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138 Commits

Author SHA1 Message Date
Preston Gurd 3fe264d625 Adds support for Atom Silvermont (SLM) - -march=slm 
Implements Instruction scheduler latencies for Silvermont,
using latencies from the Intel Silvermont Optimization Guide.

Auto detects SLM.

Turns on post RA scheduler when generating code for SLM.

llvm-svn: 190717
 2013-09-13 19:23:28 +00:00
Benjamin Kramer b289319fb8 X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equivalent. 
Give it the right register format so we can also emit it when AVX is enabled.

llvm-svn: 183971
 2013-06-14 09:31:41 +00:00
Eric Christopher b27cd8bea6 Reapply "Subtract isn't commutative, fix this for MMX psub." with 
a somewhat randomly chosen cpu that will minimize cpu specific
differences on bots.

llvm-svn: 181814
 2013-05-14 18:33:40 +00:00
Eric Christopher 3eee7454cf Temporarily revert "Subtract isn't commutative, fix this for MMX psub." 
It's causing failures on the atom bot.

llvm-svn: 181812
 2013-05-14 18:20:42 +00:00
Eric Christopher 0344f495f9 Subtract isn't commutative, fix this for MMX psub. 
Patch by Andrea DiBiagio.

llvm-svn: 181809
 2013-05-14 17:52:05 +00:00
Jakob Stoklund Olesen 267dd946f6 Annotate x87 and mmx instructions with SchedRW lists. 
This only covers the instructions that were given itinerary classes for
the Atom model.

llvm-svn: 178050
 2013-03-26 18:24:20 +00:00
Jakob Stoklund Olesen 4d39e81fb8 Remove IIC_DEFAULT from X86Schedule.td 
All the instructions tagged with IIC_DEFAULT had nothing in common, and
we already have a NoItineraries class to represent untagged
instructions.

llvm-svn: 177937
 2013-03-25 23:12:41 +00:00
Manman Ren acb8becc73 X86 MMX: optimize transfer from mmx to i32 
We used to generate a store (movq) + a load.
Now we use movd.

rdar://9946746

llvm-svn: 167056
 2012-10-30 22:15:38 +00:00
Michael Liao bbd10792c2 Introduce 'UseSSEx' to force SSE legacy encoding 
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
  enabled.

  As the penalty of inter-mixing SSE and AVX instructions, we need
  prevent SSE legacy insn from being generated except explicitly
  specified through some intrinsics. For patterns supported by both
  SSE and AVX, so far, we force AVX insn will be tried first relying on
  AddedComplexity or position in td file. It's error-prone and
  introduces bugs accidentally.

  'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
  by AVX, we need this predicate to force VEX encoding or SSE legacy
  encoding only.

  For insns not inherited by AVX, we still use the previous predicates,
  i.e. 'HasSSEx'. So far, these insns fall into the following
  categories:
  * SSE insns with MMX operands
  * SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
    CRC, and etc.)
  * SSE4A insns.
  * MMX insns.
  * x87 insns added by SSE.

2 test cases are modified:

 - test/CodeGen/X86/fast-isel-x86-64.ll
   AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
   selected by fast-isel due to complicated pattern and fast-isel
   fallback to materialize it from constant pool.

 - test/CodeGen/X86/widen_load-1.ll
   AVX code generation is different from SSE one after fixing SSE/AVX
   inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
   'vmovaps'.

llvm-svn: 162919
 2012-08-30 16:54:46 +00:00
Craig Topper a7aaa62d54 Remove the LowerMMXCONCAT_VECTORS function. It could never execute because there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result. 
llvm-svn: 161742
 2012-08-13 01:23:55 +00:00
Craig Topper f881d385da Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1. 
llvm-svn: 160941
 2012-07-30 02:14:02 +00:00
Preston Gurd 09de6ae399 Added X86 Atom latencies to X86InstrMMX.td. 
llvm-svn: 156615
 2012-05-11 14:27:12 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Andrew Trick 8523b16ff5 Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558
 2012-02-01 23:20:51 +00:00
Craig Topper eb8f9e9e5b Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget. 
llvm-svn: 147841
 2012-01-10 06:30:56 +00:00
Craig Topper 744f6311d3 Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level. 
llvm-svn: 147762
 2012-01-09 00:11:29 +00:00
Eli Friedman f1e2b50a30 PR9848: pandn is not commutative. 
No test because I can't think of any way to write one that won't break quickly.

llvm-svn: 130932
 2011-05-05 17:45:31 +00:00
Bill Wendling 402e54822b The pshufw instruction came about in MMX2 when SSE was introduced. Don't place 
it in with the SSSE3 instructions.

Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!

llvm-svn: 115552
 2010-10-04 20:24:01 +00:00
Chris Lattner d3593c3a8e the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288 
llvm-svn: 115473
 2010-10-03 19:09:13 +00:00
Chris Lattner b44b202d66 add support for the prefetch/prefetchw instructions, move femms into 
the right file.  The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.

llvm-svn: 115468
 2010-10-03 18:42:30 +00:00
Chris Lattner ae1a9de083 stub out a header to put 3dNow! instructions into. 
llvm-svn: 115429
 2010-10-02 23:06:23 +00:00
Chris Lattner 4756bbeba0 fix a regression introduced in r115243, in which the instruction 
backing int_x86_ssse3_pshuf_w got removed.  This caused PR8280.

llvm-svn: 115422
 2010-10-02 21:32:15 +00:00
Dale Johannesen dd224d2333 Massive rewrite of MMX: 
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.

llvm-svn: 115243
 2010-09-30 23:57:10 +00:00
Dale Johannesen 0ec303b97b Move remaining MMX instructions from SSE to MMX. 
llvm-svn: 113501
 2010-09-09 17:13:07 +00:00
Dale Johannesen 5f4a6f295c Move most MMX instructions (defined as anything that 
uses MMX, even if it also uses other things) from InstrSSE
into InstrMMX.  No (intended) functional change.

llvm-svn: 113462
 2010-09-09 01:02:39 +00:00
Dale Johannesen 0d2e6ad504 Add intrinsic-based patterns for MMX PINSRW and PEXTRW. 
llvm-svn: 113420
 2010-09-08 22:08:40 +00:00
Dale Johannesen 4dae01781f Slight cleanup, use only one form of MMXI_binop_rm_int. 
llvm-svn: 113406
 2010-09-08 20:54:00 +00:00
Dale Johannesen d79bb127dd Add intrinsic forms of mmx<->sse conversions. Notes: 
Omission of memory form of PI2PD is intentional; this
does not use an MMX register and does not put the chip
into MMX mode (PI2PS, oddly enough, does).
Operands of PI2PS follow the gcc builtin, not Intel.

llvm-svn: 113388
 2010-09-08 19:15:38 +00:00
Dale Johannesen 605acfe533 Add patterns for MMX that use the new intrinsics. 
Enable palignr intrinsic.
These may need adjustment for a new VT in due course.

llvm-svn: 113233
 2010-09-07 18:10:56 +00:00
Chris Lattner 620693806a fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3, 
this fixes rdar://8192860.  Unfortunately it can only be triggered
with llc because llvm-mc matches another (correctly encoded) version
of this, so no testcase.

llvm-svn: 108454
 2010-07-15 20:13:34 +00:00
Chris Lattner 6d60a14251 rip out even more sporadic v2f32 support. 
llvm-svn: 107610
 2010-07-05 04:38:33 +00:00
Dan Gohman 79b6a0f140 Fix an mmx movd encoding. 
llvm-svn: 104552
 2010-05-24 20:51:08 +00:00
Dan Gohman 098a47931c Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't 
have a pattern and it had an invalid encoding.

llvm-svn: 104244
 2010-05-20 18:05:01 +00:00
Kevin Enderby e3a1726034 Fixed the encoding of two of the X86 movq instuctions. The Move quadword from 
mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.

llvm-svn: 102952
 2010-05-03 21:03:31 +00:00
Stuart Hastings 24b63f1597 Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029. 
llvm-svn: 102199
 2010-04-23 19:03:32 +00:00
Chris Lattner be980f2df7 remove a bunch of dead patterns. 
llvm-svn: 99748
 2010-03-28 07:38:00 +00:00
Chris Lattner 26e6273772 fix a few more ambiguous types. 
llvm-svn: 98531
 2010-03-15 05:53:30 +00:00
Chris Lattner d8045649a6 fix some more ambiguous patterns, remove another nontemporalstore 
pattern which is broken (source and address swapped).

llvm-svn: 97958
 2010-03-08 18:57:56 +00:00
Dan Gohman 8c5d683aa9 The mayHaveSideEffects flag is no longer used. 
llvm-svn: 97348
 2010-02-27 23:47:46 +00:00
Chris Lattner 7489838a89 remove a confused pattern that is trying to match an address 
then use it as an MMX register (!?).

llvm-svn: 96901
 2010-02-23 07:16:12 +00:00
Chris Lattner a828850b4d X86InstrInfoSSE.td declares PINSRW as having type v8i16, 
don't alis it in the MMX .td file with a different width,
split into two X86ISD opcodes.  This fixes an x86 testcase.

llvm-svn: 96859
 2010-02-23 02:07:48 +00:00
David Greene 509be1fe5e TableGen fragment refactoring. 
Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files.  We will use this for
the AVX specification to help with the transition from the current
SSE specification.

llvm-svn: 95727
 2010-02-09 23:52:19 +00:00
Chris Lattner e96d534ce0 lower the last of the MRMInitReg instructions in MCInstLower. 
llvm-svn: 95435
 2010-02-05 21:30:49 +00:00
Mon P Wang 586d997e98 Improved widening loads by adding support for wider loads if 
the alignment allows.  Fixed a bug where we didn't use a
vector load/store for PR5626.

llvm-svn: 94338
 2010-01-24 00:05:03 +00:00
Sean Callanan 04d8cb74f3 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Dan Gohman 453d64c9f5 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Daniel Dunbar c4f8ea4ccb Add 'isCodeGenOnly' bit to Instruction .td records. 
- Used to mark fake instructions which don't correspond to an actual machine
   instruction (or are duplicates of a real instruction). This is to be used for
   "special cases" in the .td files, which should be ignored by things like the
   assembler and disassembler. We still need a good solution to handle pervasive
   duplication, like with the Int_ instructions.

 - Set the bit on fake "mov 0" style instructions, which allows turning an
   assembler matcher warning into a hard error.

 - -2 FIXMEs.

llvm-svn: 78731
 2009-08-11 22:17:52 +00:00
Eric Christopher d91dceea0f Whitespace, 80-column, and isTwoAddress -> Constraints = "" changes. 
No functional change.

llvm-svn: 78608
 2009-08-10 22:37:37 +00:00
Evan Cheng 3aa1e77572 Remove neverHasSideEffects on MMX_MOVD64rrv164 since it has a matching pattern. 
llvm-svn: 77978
 2009-08-03 18:07:19 +00:00
Rafael Espindola 70e9816624 Use movd instead of movq 
llvm-svn: 77956
 2009-08-03 05:21:05 +00:00