Commit Graph

154 Commits

Author SHA1 Message Date
Bob Wilson 947f04bad0 Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.

llvm-svn: 98409
2010-03-13 01:08:20 +00:00
Johnny Chen 9a3e2398ae Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.

llvm-svn: 98172
2010-03-10 18:59:38 +00:00
Johnny Chen 1d63b9574d Modified the asm string of 16-bit Thumb MUL instruction so that it prints:
MULS <Rdm>, <Rn>, <Rdm>

according to A8.6.105 MUL Encoding T1.

llvm-svn: 97675
2010-03-03 23:15:43 +00:00
Johnny Chen 44908a5e17 Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.

llvm-svn: 97573
2010-03-02 18:14:57 +00:00
Dan Gohman 8c5d683aa9 The mayHaveSideEffects flag is no longer used.
llvm-svn: 97348
2010-02-27 23:47:46 +00:00
Johnny Chen 74cca5a989 Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,
WFI, SEV, SETEND.

llvm-svn: 97149
2010-02-25 17:51:03 +00:00
Johnny Chen 90adefcf7e Added tNOP for disassembly only.
llvm-svn: 97105
2010-02-25 03:28:51 +00:00
Johnny Chen 57656da73f Added tSVC and tTRAP for disassembly only.
llvm-svn: 97098
2010-02-25 02:21:11 +00:00
Jim Grosbach 45fceea0e4 Updated version of r96634 (which was reverted due to failing 176.gcc and
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

llvm-svn: 96822
2010-02-22 23:10:38 +00:00
Jim Grosbach 3e2cad3b1a 80 column cleanup
llvm-svn: 96393
2010-02-16 21:23:02 +00:00
Jim Grosbach fba7fce5be Remove trailing whitespace
llvm-svn: 96388
2010-02-16 21:07:46 +00:00
Johnny Chen f40b8e03fb Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
llvm-svn: 95884
2010-02-11 18:12:29 +00:00
Jim Grosbach f7279bd10f Radar 7417921
tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686
2010-02-09 19:51:37 +00:00
Jim Grosbach a570d05228 tighten up eh.setjmp sequence a bit.
llvm-svn: 95603
2010-02-08 23:22:00 +00:00
Jim Grosbach a3575ca846 Adjust setjmp instruction sequence to not need 32-bit alignment padding
llvm-svn: 94627
2010-01-27 00:07:20 +00:00
Jim Grosbach 267430f74d Fix PR5694. The CMN instructions set the flags differently from CMP, so they
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.

llvm-svn: 94119
2010-01-22 00:08:13 +00:00
Johnny Chen 27f000a9af The most significant encoding bit of GPR:$src or GPR:$dst was over-specified in
the various MOV (register) instructions (16-bit Thumb), including tBRIND (the
indirect branch).  Instead of '1', it should be specified as '?', because GPR
only specifies the register class, which includes both hi-and-lo registers.

llvm-svn: 93759
2010-01-18 20:15:56 +00:00
Johnny Chen 0f45f4f849 Added 16-bit Thumb Load/Store immediate instructions with encoding bits so that
the disassembler can properly decode Load/Store register/immediate instructions.

llvm-svn: 93471
2010-01-14 22:42:17 +00:00
Johnny Chen b34888b6d0 Fixed a couple of places for Thumb MOV where encoding bits are underspecified.
llvm-svn: 93349
2010-01-13 21:00:26 +00:00
Jakob Stoklund Olesen a94837dc24 Remove the JustSP single-register regclass.
It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.

llvm-svn: 93280
2010-01-13 00:43:06 +00:00
Jakob Stoklund Olesen b05fbe1486 Add a SPR register class to the ARM target.
Certain Thumb instructions require only SP (e.g. tSTRspi).

llvm-svn: 91944
2009-12-22 23:54:44 +00:00
Johnny Chen 7f30b64dce Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.
llvm-svn: 91571
2009-12-16 23:36:52 +00:00
Johnny Chen 466231ab92 Add encoding bits for some Thumb instructions. Plus explicitly set the top two
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496
2009-12-16 02:32:54 +00:00
Johnny Chen c28e629c2d Added encoding bits for the Thumb ISA. Initial checkin.
llvm-svn: 91434
2009-12-15 17:24:14 +00:00
Jim Grosbach 36d4dec28a Thumb1 exception handling setjmp
llvm-svn: 90246
2009-12-01 18:10:36 +00:00
Evan Cheng bdb43a9d99 Remat VLDRD from constpool. Clean up some instruction property specifications.
llvm-svn: 89478
2009-11-20 19:57:15 +00:00
Evan Cheng b18525937c More consistent thumb1 asm printing.
llvm-svn: 89328
2009-11-19 06:57:41 +00:00
Evan Cheng 207b246650 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304
2009-11-06 23:52:48 +00:00
Evan Cheng c63943018f The .n suffix must go after the predicate.
llvm-svn: 86019
2009-11-04 07:38:48 +00:00
Evan Cheng 3f1a92468a Use ldr.n to workaround a darwin assembler bug.
llvm-svn: 85980
2009-11-04 00:00:39 +00:00
Bob Wilson 064c5fef11 For Thumb indirect branches, use "mov pc, reg" which does not switch
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.

llvm-svn: 85874
2009-11-03 06:29:56 +00:00
Bob Wilson 1c66e8a6b7 Put BlockAddresses into ARM constant pools.
llvm-svn: 85824
2009-11-02 20:59:23 +00:00
Evan Cheng 6f29ad9170 Use cbz and cbnz instructions.
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
Bob Wilson 1cf0b03064 Add ARM codegen for indirect branches.
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577
2009-10-30 05:45:42 +00:00
Dan Gohman 453d64c9f5 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
2009-10-29 18:10:34 +00:00
Bob Wilson 73789b848d Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411
2009-10-28 18:26:41 +00:00
Evan Cheng b02bdb4552 Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
llvm-svn: 85184
2009-10-27 00:08:59 +00:00
Evan Cheng 1b2b64f618 Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
ld / st pairs, etc.

llvm-svn: 83197
2009-10-01 08:22:27 +00:00
Evan Cheng 3bbc6c3ae6 Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
llvm-svn: 83191
2009-10-01 01:33:39 +00:00
Jim Grosbach bcad0c8421 Add "isBarrier = 1" to return instructions.
Patch by Sylvere Teissier.

llvm-svn: 83135
2009-09-30 01:35:11 +00:00
Evan Cheng a1c6495af7 Remove comments which don't add much to .s readibility.
llvm-svn: 81306
2009-09-09 01:38:23 +00:00
David Goodwin d93c668f00 Calls clobber FPSCR.
llvm-svn: 80956
2009-09-03 22:12:28 +00:00
Evan Cheng 4f835f1d7d Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
llvm-svn: 80615
2009-08-31 20:14:07 +00:00
Evan Cheng 4047b53a40 Print a nl before pic labels so they start at a new line. This makes assembly more readable.
llvm-svn: 80350
2009-08-28 06:59:37 +00:00
Evan Cheng 6da267de23 v4, v5 does not support sxtb / sxth.
llvm-svn: 80322
2009-08-28 00:31:43 +00:00
Bob Wilson ceffeb6abd Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676
2009-08-21 21:58:55 +00:00
Evan Cheng 01de985ae6 Fix an obvious copy-n-paste bug.
llvm-svn: 79535
2009-08-20 17:01:04 +00:00
David Goodwin a7c2dfbca1 Update Cortex-A8 instruction itineraries for integer instructions.
llvm-svn: 79436
2009-08-19 18:00:44 +00:00
Evan Cheng dd406177de Fix revsh pattern.
llvm-svn: 79318
2009-08-18 05:43:23 +00:00
Evan Cheng e41903b10d Also shrink immediate branches; also more assembler workarounds.
llvm-svn: 79014
2009-08-14 18:31:44 +00:00