ea2319112f
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
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rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
6ca42c5be3
Fix incorrect relocation generation. Patch by Kristof Beyls.
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Fixes PR11214.
llvm-svn: 147180
2011-12-22 21:36:43 +00:00
12ccf45bbb
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
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Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
llvm-svn: 147153
2011-12-22 18:04:04 +00:00
e2eed9649e
Local dynamic TLS model for direct object output. Create the correct TLS MIPS
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ELF relocations.
Patch by Jack Carter.
llvm-svn: 147118
2011-12-22 01:05:17 +00:00
7869d8c01e
ARM VFP optional data type on VMOV GPR<-->SPR.
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llvm-svn: 147104
2011-12-21 23:24:15 +00:00
8c59bbc1ed
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
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Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
b3ef713e44
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
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These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
c80a264386
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
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llvm-svn: 147069
2011-12-21 19:40:55 +00:00
c5af54ec89
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
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llvm-svn: 147025
2011-12-21 00:38:54 +00:00
6ac54afeba
Enable and fix a test.
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llvm-svn: 147011
2011-12-20 23:20:00 +00:00
2c59052984
ARM assembly parsing and encoding for VST2 single-element, double spaced.
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llvm-svn: 146990
2011-12-20 20:46:29 +00:00
c8ebeff9a1
ARM enable a few more tests.
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llvm-svn: 146985
2011-12-20 20:03:00 +00:00
75e2ab5db2
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
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llvm-svn: 146983
2011-12-20 19:21:26 +00:00
e2ca9e5b5f
ARM assembly shifts by zero should be plain 'mov' instructions.
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"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
8648c10184
ARM assembly parsing and encoding support for LDRD(label).
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rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
64f4de29e0
ARM NEON two-operand aliases for VPADD.
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rdar://10602276
llvm-svn: 146895
2011-12-19 19:51:03 +00:00
9ae4fc035b
ARM NEON implied destination aliases for VMAX/VMIN.
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llvm-svn: 146885
2011-12-19 18:57:38 +00:00
cef98cddbe
ARM NEON relax parse time diagnostics for alignment specifiers.
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There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
d3df3d3527
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
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asm parsing and testcase.
llvm-svn: 146801
2011-12-17 01:14:52 +00:00
64944090ff
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
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llvm-svn: 146709
2011-12-15 23:46:18 +00:00
a47294e24d
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
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llvm-svn: 146699
2011-12-15 22:56:33 +00:00
4a5c887370
ARM NEON VTBL/VTBX assembly parsing and encoding.
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llvm-svn: 146691
2011-12-15 22:27:11 +00:00
a8aa30b620
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
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llvm-svn: 146605
2011-12-14 23:25:46 +00:00
ad41ab5015
Improve the implementation of .incbin directive by replacing a loop by using
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getStreamer().EmitBytes. Suggestion by Benjamin Kramer!
llvm-svn: 146599
2011-12-14 22:34:45 +00:00
bb18fb4f52
ARM NEON fix alignment encoding for VST2 w/ writeback.
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Add tests for w/ writeback instruction parsing and encoding.
llvm-svn: 146594
2011-12-14 21:49:24 +00:00
109f25c966
Add the .incbin directive which takes the binary data from a file and emits
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it to the streamer. rdar://10383898
llvm-svn: 146592
2011-12-14 21:47:48 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
a342667fd0
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
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When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
llvm-svn: 146567
2011-12-14 17:30:24 +00:00
ab5830e51b
ARM assembler support for the target-specific .req directive.
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rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
485e5622f4
Thumb2 assembler aliases for "mov(shifted register)"
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rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
18bf363078
ARM LDM/STM system instruction variants.
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rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
dce106940e
Test for 146516
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llvm-svn: 146517
2011-12-13 21:06:59 +00:00
1f1a3598c2
ARM thumb2 parsing of "rsb rd, rn, #0".
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rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
4b0844e191
ARM NEON two-operand aliases for VQDMULH.
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llvm-svn: 146514
2011-12-13 20:40:37 +00:00
561e4e18cf
ARM pre-UAL NEG mnemonic for convenience when porting old code.
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llvm-svn: 146511
2011-12-13 20:23:22 +00:00
7200123fa3
Add test/MC/Mips/dg.exp.
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llvm-svn: 146472
2011-12-13 04:12:49 +00:00
341850fdc6
Move direct object emitter test to directory test/MC/Mips. Rename it to
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elf-relsym.ll.
llvm-svn: 146470
2011-12-13 03:50:34 +00:00
86ffb03c79
Don't rely on a particular version string for llvm.
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llvm-svn: 146456
2011-12-13 00:34:14 +00:00
7c0face455
XOP instructions and encoding tests.
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llvm-svn: 146407
2011-12-12 19:37:49 +00:00
735cb8bcdc
Add support for gnu_indirect_function.
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llvm-svn: 146377
2011-12-12 17:34:04 +00:00
1d76d4196a
Don't assume things about the exact details of the LLVM version number,
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such as what VCS information is attached.
llvm-svn: 146333
2011-12-10 21:40:31 +00:00
c7f355b8e1
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
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does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
llvm-svn: 146311
2011-12-10 02:28:43 +00:00
6192b6570d
ARM assembly aliases for BIC<-->AND (immediate).
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When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
llvm-svn: 146283
2011-12-09 22:02:17 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
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Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
7e0a793183
Handle reloc_signed_4byte in here. Not doing so was a regression from my
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previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.
llvm-svn: 146273
2011-12-09 19:57:29 +00:00
e7739d484f
The second part of support for generating dwarf for assembly source files. This
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generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.
The next part will be to get the clang driver to enable this when assembling
a .s file. rdar://9275556
llvm-svn: 146262
2011-12-09 18:09:40 +00:00
0a7f336475
Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a
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symbol difference. This matches gas behavior and fixes PR11513.
We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.
llvm-svn: 146238
2011-12-09 03:03:58 +00:00
db731be7b8
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
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llvm-svn: 146194
2011-12-08 22:19:04 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
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llvm-svn: 146192
2011-12-08 22:06:06 +00:00
3a97d946d2
Tidy up a bit.
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llvm-svn: 146190
2011-12-08 22:04:40 +00:00
Jim Grosbach