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32 Commits

Author SHA1 Message Date
Tom Stellard c5a154db48 AMDGPU: Separate R600 and GCN TableGen files 
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc.  This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself.  This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.

Reviewers: arsenm, nhaehnle, jvesely

Reviewed By: arsenm

Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D46365

llvm-svn: 335942
 2018-06-28 23:47:12 +00:00
Tom Stellard a2be8f4c35 AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic 
Summary: This is no longer used by mesa since its 18.0.0 release.

Reviewers: nhaehnle

Reviewed By: nhaehnle

Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D45988

llvm-svn: 330775
 2018-04-24 21:37:57 +00:00
Matt Arsenault 754dd3eaef AMDGPU: Remove legacy bfe intrinsics 
llvm-svn: 299372
 2017-04-03 18:08:08 +00:00
Matt Arsenault 9417505f7d AMDGPU: Remove llvm.AMDGPU.clamp intrinsic 
llvm-svn: 295789
 2017-02-21 23:46:04 +00:00
Matt Arsenault c2a44e4c3c AMDGPU: Remove llvm.AMDGPU.flbit intrinsic 
llvm-svn: 295754
 2017-02-21 19:27:33 +00:00
Matt Arsenault b95ddd7cea AMDGPU: Remove llvm.AMDGPU.cube intrinsic 
llvm-svn: 295359
 2017-02-16 19:09:04 +00:00
Matt Arsenault eb65cda986 AMDGPU: Remove llvm.AMDGPU.rsq intrinsic 
llvm-svn: 295358
 2017-02-16 19:08:58 +00:00
Jan Vesely b64c8925e9 AMDGPU: Remove read_workdim intrinsic 
Differential revision: https://reviews.llvm.org/D22732

llvm-svn: 276682
 2016-07-25 20:17:02 +00:00
Matt Arsenault c96e1deffa AMDGPU: Add intrinsic for s_flbit_i32/v_ffbh_i32 
llvm-svn: 275871
 2016-07-18 18:35:05 +00:00
Matt Arsenault 4c519d3518 AMDGPU/R600: Replace barrier intrinsics 
llvm-svn: 275870
 2016-07-18 18:34:59 +00:00
Matt Arsenault a65e6b8335 AMDGPU: Remove brev intrinsic 
llvm-svn: 275620
 2016-07-15 21:27:13 +00:00
Matt Arsenault 09b2c4aee8 AMDGPU: Remove legacy rsq.clamped intrinsic 
Mesa still has a use of llvm.AMDGPU.rsq.f64 remaining.

Also fix mismatch with non-IEEE rsq selecting to IEEE rsq.

llvm-svn: 275617
 2016-07-15 21:26:52 +00:00
Matt Arsenault 897eee4187 AMDGPU: Remove unused intrinsics 
llvm-svn: 275371
 2016-07-14 05:23:19 +00:00
Matt Arsenault f071102647 AMDGPU: Remove last AMDIL intrinsics 
llvm-svn: 275309
 2016-07-13 19:42:06 +00:00
Matt Arsenault 92edab2df9 AMDGPU: Remove bfi and bfm intrinsics 
Nothing is using them.

llvm-svn: 260123
 2016-02-08 19:06:01 +00:00
Matt Arsenault 295875efda AMDGPU: Remove 24-bit intrinsics 
The known bit matching code seems to work reasonably well,
so these shouldn't really be needed.

llvm-svn: 259180
 2016-01-29 10:05:16 +00:00
Matt Arsenault bee7575e1a AMDGPU: Move AMDGPU intrinsics only used by R600 
llvm-svn: 258790
 2016-01-26 04:49:24 +00:00
Matt Arsenault 051d6f9fde AMDGPU: Add new amdgcn intrinsics for cube instructions 
More cleanup to try to get all intrinsics using the correct
amdgcn prefix that are as close to the instruction as possible.

llvm-svn: 258786
 2016-01-26 04:29:56 +00:00
Matt Arsenault 0c3e2338fe AMDGPU: Restore AMDGPU prefixed rsq intrinsic for now 
Also move into backend intrinsics to discourage use of the old name.

llvm-svn: 258783
 2016-01-26 04:14:16 +00:00
Matt Arsenault 7713162c32 AMDGPU: Remove more unused intrinsics 
Replace tests with lrp with basic IR expansion

llvm-svn: 258612
 2016-01-23 05:42:38 +00:00
Matt Arsenault bef34e21c7 AMDGPU: Rename intrinsics to use amdgcn prefix 
The intrinsic target prefix should match the target name
as it appears in the triple.

This is not yet complete, but gets most of the important ones.
llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled
for compatability for now.

llvm-svn: 258557
 2016-01-22 21:30:34 +00:00
Matt Arsenault ee0930821a AMDGPU: Remove random TGSI intrinsic 
I don't think this was ever used.

llvm-svn: 258514
 2016-01-22 18:42:44 +00:00
Matt Arsenault 0cbaa1762b AMDGPU: Remove AMDGPU.fract intrinsic 
Mesa doesn't use this, and this is pattern matched already
from fsub x, (ffloor x)

llvm-svn: 258513
 2016-01-22 18:42:38 +00:00
Matt Arsenault 7ba334a7d9 AMDGPU: Remove AMDGPU.trunc intrinsic 
llvm-svn: 258348
 2016-01-20 21:05:53 +00:00
Matt Arsenault 15fbe49daf AMDGPU: Remove AMDIL.fraction intrinsic 
llvm-svn: 258347
 2016-01-20 21:05:49 +00:00
Matt Arsenault 7cccd2672e AMDGPU: Remove AMDIL.round.nearest intrinsic 
llvm-svn: 258346
 2016-01-20 21:05:40 +00:00
Matt Arsenault 1c9e4ef0df AMDGPU: Remove abs intrinsic 
llvm-svn: 258343
 2016-01-20 20:58:29 +00:00
Matt Arsenault f7e6e89718 AMDGPU: Remove min/max intrinsics 
This removes support for mesa 11.0.x

llvm-svn: 258342
 2016-01-20 20:50:19 +00:00
Matt Arsenault 2aed6ca1d3 AMDGPU: Switch barrier intrinsics to using convergent 
noduplicate prevents unrolling of small loops that happen to have
barriers in them. If a loop has a barrier in it, it is OK to duplicate
it for the unroll.

llvm-svn: 256075
 2015-12-19 01:46:41 +00:00
Tom Stellard 45bb48ea19 R600 -> AMDGPU rename 
llvm-svn: 239657
 2015-06-13 03:28:10 +00:00
Tom Stellard 1be1aa84ec Revert "AMDGPU: Add core backend files for R600/SI codegen v6" 
This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.

llvm-svn: 160303
 2012-07-16 18:19:53 +00:00
Tom Stellard bcce80fa95 AMDGPU: Add core backend files for R600/SI codegen v6 
llvm-svn: 160270
 2012-07-16 14:17:08 +00:00