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106 Commits

Author SHA1 Message Date
Venkatraman Govindaraju bac285f588 [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3). 
llvm-svn: 202604
 2014-03-02 02:12:33 +00:00
Venkatraman Govindaraju c86e0f3873 [SparcV9] Add support for parsing branch instructions with prediction. 
llvm-svn: 202602
 2014-03-01 22:03:07 +00:00
Venkatraman Govindaraju 2286874119 [Sparc] Add support for parsing annulled branch instructions. 
llvm-svn: 202599
 2014-03-01 20:08:48 +00:00
Venkatraman Govindaraju e0c5bff720 [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc. 
llvm-svn: 202598
 2014-03-01 18:54:52 +00:00
Venkatraman Govindaraju 2a9c430677 [Sparc] Add missing ALU instruction patterns. 
llvm-svn: 202597
 2014-03-01 17:51:00 +00:00
Venkatraman Govindaraju 256735d485 [Sparc] Add support to decode unimp instruction. 
llvm-svn: 202581
 2014-03-01 09:28:18 +00:00
Venkatraman Govindaraju 484ca1a030 [Sparc] Add support to decode negative simm13 operands in the sparc disassembler. 
llvm-svn: 202578
 2014-03-01 09:11:57 +00:00
Venkatraman Govindaraju 78df2dec0c [Sparc] Add support for decoding call instructions in the sparc disassembler. 
llvm-svn: 202577
 2014-03-01 08:30:58 +00:00
Venkatraman Govindaraju fb54821398 [Sparc] Add support to disassemble sparc memory instructions. 
llvm-svn: 202575
 2014-03-01 07:46:33 +00:00
Benjamin Kramer facca1f049 SPARC: Implement TRAP lowering. Matches what GCC emits. 
llvm-svn: 201994
 2014-02-23 21:43:52 +00:00
Venkatraman Govindaraju ced9226b0f [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding. 
llvm-svn: 200963
 2014-02-07 07:34:49 +00:00
Venkatraman Govindaraju 50f32d949b [SparcV9] Use correct register class (I64RegClass) to hold the address of _GLOBAL_OFFSET_TABLE_ in sparcv9. 
llvm-svn: 200368
 2014-01-29 03:35:08 +00:00
Venkatraman Govindaraju cd4d9ac62a [Sparc] Add support for parsing floating point instructions. 
llvm-svn: 199033
 2014-01-12 04:48:54 +00:00
Venkatraman Govindaraju 0d288d3105 [Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl. 
llvm-svn: 198909
 2014-01-10 01:48:17 +00:00
Venkatraman Govindaraju 6ff62cc539 [Sparc] Multiclass for loads/stores. No functionality change intended. 
llvm-svn: 198893
 2014-01-09 21:49:18 +00:00
Venkatraman Govindaraju b3b7c38983 [Sparc] Add support for parsing branch instructions and conditional moves. 
llvm-svn: 198738
 2014-01-08 06:14:52 +00:00
Venkatraman Govindaraju 0458b599f8 [Sparc] Add support for parsing memory operands in sparc AsmParser. 
llvm-svn: 198658
 2014-01-07 01:49:11 +00:00
Venkatraman Govindaraju dfcccc7db0 [Sparc] Add initial implementation of disassembler for sparc 
llvm-svn: 198591
 2014-01-06 08:08:58 +00:00
Venkatraman Govindaraju 5f1cce50e6 [Sparc] Add initial implementation of MC Code emitter for sparc. 
llvm-svn: 198533
 2014-01-05 02:13:48 +00:00
Venkatraman Govindaraju c2dee7dc74 [Sparc] Add the initial implementation of an asm parser for sparc/sparcv9. 
llvm-svn: 198484
 2014-01-04 11:30:13 +00:00
Venkatraman Govindaraju 9a3da52ea2 [Sparc] Handle atomic loads/stores in sparc backend. 
llvm-svn: 198286
 2014-01-01 22:11:54 +00:00
Venkatraman Govindaraju acf0233a46 [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does. 
llvm-svn: 198280
 2014-01-01 19:00:10 +00:00
Venkatraman Govindaraju 3e3a29a2e9 [SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns. 
This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.

llvm-svn: 198157
 2013-12-29 07:15:09 +00:00
Venkatraman Govindaraju 9c338504e5 [Sparc]: Implement LEA pattern for sparcv9. 
llvm-svn: 195575
 2013-11-24 20:07:35 +00:00
Venkatraman Govindaraju 5ae77f7564 [SparcV9] Handle i64 <-> float conversions in sparcv9 mode. 
llvm-svn: 193957
 2013-11-03 12:28:40 +00:00
Venkatraman Govindaraju 2ea4c2880c [Sparc] Implement JIT for SPARC. 
No new testcases. However, this patch makes all supported JIT testcases in 
test/ExecutionEngine  pass on Sparc.

llvm-svn: 192176
 2013-10-08 07:15:22 +00:00
Venkatraman Govindaraju 8223c553cf [Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead. 
llvm-svn: 192160
 2013-10-08 02:50:29 +00:00
Venkatraman Govindaraju f482d3d338 [Sparc] Do not emit nop after fcmp* instruction with V9. 
llvm-svn: 192056
 2013-10-06 07:06:44 +00:00
Venkatraman Govindaraju 1230342fd2 [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx. 
addx/subx does not modify conditional codes whereas addxcc/subxx does.

llvm-svn: 192053
 2013-10-06 02:11:10 +00:00
Venkatraman Govindaraju 94629eb861 [Sparc] Use correct instruction pattern for CMPri. 
llvm-svn: 191180
 2013-09-22 18:54:54 +00:00
Venkatraman Govindaraju 51270837aa [Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter. 
llvm-svn: 191168
 2013-09-22 09:54:42 +00:00
Venkatraman Govindaraju 709d154d69 [Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended. 
llvm-svn: 191167
 2013-09-22 09:18:26 +00:00
Venkatraman Govindaraju 2fb440fbad [Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended. 
llvm-svn: 191166
 2013-09-22 08:51:55 +00:00
Venkatraman Govindaraju cb1dca602c [Sparc] Add support for TLS in sparc. 
llvm-svn: 191164
 2013-09-22 06:48:52 +00:00
Venkatraman Govindaraju 59039dc1bf [Sparc] Add support for soft long double (fp128). 
llvm-svn: 189780
 2013-09-03 04:11:59 +00:00
Venkatraman Govindaraju 35e0c382d5 [Sparc] Add long double (f128) instructions to sparc backend. 
llvm-svn: 189198
 2013-08-25 18:30:06 +00:00
Jakob Stoklund Olesen 0c00704f27 Use register masks on SPARC call instructions. 
llvm-svn: 189085
 2013-08-23 02:33:47 +00:00
Venkatraman Govindaraju f625773bca [Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions. 
llvm-svn: 188738
 2013-08-20 01:26:14 +00:00
Venkatraman Govindaraju 7dae9ce021 [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. 
llvm-svn: 183613
 2013-06-08 15:32:59 +00:00
Venkatraman Govindaraju dc82ac0dcc [Sparc]: Use cmp instruction instead of subcc to compare integers. 
llvm-svn: 183463
 2013-06-07 00:03:36 +00:00
Venkatraman Govindaraju a54533ed78 Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 
llvm-svn: 183243
 2013-06-04 18:33:25 +00:00
Venkatraman Govindaraju f80d72f149 Sparc: Add support for indirect branch and blockaddress in Sparc backend. 
llvm-svn: 183094
 2013-06-03 05:58:33 +00:00
Venkatraman Govindaraju 774fe2e29a Sparc: When storing 0, use %g0 directly in the store instruction instead of 
using two instructions (sethi and store).

llvm-svn: 183090
 2013-06-03 00:21:54 +00:00
Jakob Stoklund Olesen 4a78c86a6a Implement SPselectfcc for i64 operands. 
Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).

llvm-svn: 182221
 2013-05-19 20:20:54 +00:00
Jakob Stoklund Olesen ead983cec9 Handle i64 FrameIndex nodes in SPARC v9 mode. 
llvm-svn: 182216
 2013-05-19 19:14:24 +00:00
Jakob Stoklund Olesen 65d3287282 Fix the SETHIimm pattern for 64-bit code. 
Don't ignore the high 32 bits of the immediate.

llvm-svn: 179985
 2013-04-21 21:18:03 +00:00
Jakob Stoklund Olesen dc1ed57858 Fix patterns for 64-bit pointers. 
This fixes the pic32 code model for SPARC v9.

llvm-svn: 179469
 2013-04-14 01:53:23 +00:00
Jakob Stoklund Olesen 8cfaffaade Add SPARC v9 support for select on 64-bit compares. 
This requires v9 cmov instructions using the %xcc flags instead of the
%icc flags.

Still missing:
- Select floats on %xcc flags.
- Select i64 on %fcc flags.

llvm-svn: 178737
 2013-04-04 03:08:00 +00:00
Jakob Stoklund Olesen d9bbdfd3cc Add 64-bit compare + branch for SPARC v9. 
The same compare instruction is used for 32-bit and 64-bit compares. It
sets two different sets of flags: icc and xcc.

This patch adds a conditional branch instruction using the xcc flags for
64-bit compares.

llvm-svn: 178621
 2013-04-03 04:41:44 +00:00
Jakob Stoklund Olesen c1d1a4816e Add 64-bit shift instructions. 
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.

This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.

llvm-svn: 178525
 2013-04-02 04:09:12 +00:00