maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
166,511 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

4 Commits

Author SHA1 Message Date
Kevin Qin e0faea11b1 [AArch64 NEON] Expand vector for UDIV/SDIV/UREM/SREM/FREM as neon doesn't support these operations. 
llvm-svn: 199485
 2014-01-17 09:54:30 +00:00
Hao Liu 74107fe526 [AArch64]Fix the problem that can't select mul of v1i64/v2i64 types. 
E.g. Can't select such IR:
     %tmp = mul <2 x i64> %a, %b

llvm-svn: 198188
 2013-12-30 01:38:41 +00:00
Kevin Qin e4ddaa1bd5 Fix Incorrect CHECK message [0-31]+ in test case. 
In regular expression, [0-31]+ equals to [0-3]+, not the number from
0 to 31. So change it to [0-9]+.

llvm-svn: 197113
 2013-12-12 02:19:13 +00:00
Tim Northover 40e9efd725 AArch64: add initial NEON support 
Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

llvm-svn: 187567
 2013-08-01 09:20:35 +00:00