79dbb0c6e4
Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.
...
llvm-svn: 157903
2012-06-03 18:58:46 +00:00
a0396e4583
X86: Rename the CLMUL target feature to PCLMUL.
...
It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.
llvm-svn: 157745
2012-05-31 14:34:17 +00:00
bae0e9ea1d
Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify Bulldozer feature list.
...
llvm-svn: 155897
2012-05-01 06:54:48 +00:00
43518cc55f
Make XOP imply AVX as its needed to legalize the registers types.
...
llvm-svn: 155891
2012-05-01 05:41:41 +00:00
29dd148a71
Make CLMUL and AES imply SSE2 since its needed to legalize the type.
...
llvm-svn: 155888
2012-05-01 05:28:32 +00:00
0eacda5f69
Enable AVX and FMA4 for AMD Bulldozer processors.
...
llvm-svn: 155885
2012-05-01 05:18:13 +00:00
08ccfbe57b
Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei7-avx, core-avx-i, and core-avx2 cpu names.
...
llvm-svn: 155618
2012-04-26 06:40:15 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
...
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
1b81fddd65
Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.
...
llvm-svn: 150008
2012-02-07 22:50:41 +00:00
8523b16ff5
Instruction scheduling itinerary for Intel Atom.
...
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
llvm-svn: 149558
2012-02-01 23:20:51 +00:00
4a6e778aae
Rename X86ATTAsmParser -> X86AsmParser
...
We are using one parser to parse att as well as intel style syntax.
llvm-svn: 148032
2012-01-12 18:03:40 +00:00
67bf992a8f
Add definition for intel asm variant.
...
Right now, this just adds additional entries in match table. The parser does not use them yet.
llvm-svn: 147859
2012-01-10 17:51:54 +00:00
077ae1d760
Add definitions for AMD's bobcat (aka btver1)
...
llvm-svn: 147846
2012-01-10 11:50:02 +00:00
85d684a4d9
Split AsmParser into two components - AsmParser and AsmParserVariant
...
AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.
llvm-svn: 147787
2012-01-09 19:13:28 +00:00
f287a4509e
Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior.
...
llvm-svn: 147770
2012-01-09 09:02:13 +00:00
a5d1fc2cc7
Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal.
...
llvm-svn: 147369
2011-12-30 07:16:00 +00:00
e1bd05128e
Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled.
...
llvm-svn: 147349
2011-12-29 19:46:19 +00:00
a060afb5ba
Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339.
...
llvm-svn: 147347
2011-12-29 18:47:31 +00:00
7bd3305f3e
Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A.
...
llvm-svn: 147339
2011-12-29 15:51:45 +00:00
1280eb1d06
Add XOP feature flag.
...
llvm-svn: 145682
2011-12-02 15:14:37 +00:00
5feb3dab79
X86: Turns out bulldozer also supports sse42 and lzcnt.
...
While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.
llvm-svn: 145494
2011-11-30 15:48:16 +00:00
981f32327d
X86: Add subtargets for AMD's bulldozer.
...
llvm-svn: 145493
2011-11-30 15:27:46 +00:00
228d9131aa
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag.
...
llvm-svn: 143319
2011-10-30 19:57:21 +00:00
49045ddb4c
Remove NaClMode
...
llvm-svn: 142338
2011-10-18 05:29:23 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
...
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
3657fe4b17
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141939
2011-10-14 03:21:46 +00:00
063f55ffdd
Revert r141854 because it was causing failures:
...
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
8cc9388073
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141854
2011-10-13 07:09:14 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
...
llvm-svn: 141651
2011-10-11 06:44:02 +00:00
874c519337
X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge.
...
llvm-svn: 141571
2011-10-10 19:35:07 +00:00
42c0330a79
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
...
llvm-svn: 141563
2011-10-10 18:34:56 +00:00
fe9179fa4f
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
...
llvm-svn: 141505
2011-10-09 07:31:39 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
...
llvm-svn: 141007
2011-10-03 17:28:23 +00:00
73df7e3830
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
...
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
llvm-svn: 139125
2011-09-05 21:51:43 +00:00
5e5704277f
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
...
llvm-svn: 138660
2011-08-26 21:21:21 +00:00
13bcc6c1c7
Add Mode64Bit feature and sink it down to MC layer.
...
llvm-svn: 134641
2011-07-07 21:06:52 +00:00
0bf26746d9
Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility.
...
llvm-svn: 131730
2011-05-20 15:11:26 +00:00
9973738b65
Add pentium{3,4}m cpus. Patch by Alexander Best!
...
llvm-svn: 130749
2011-05-03 03:42:50 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
...
Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
30088ba110
Add 3DNow! intrinsics.
...
llvm-svn: 129551
2011-04-15 00:32:41 +00:00
b88784c185
Fix whitespace and tabs.
...
llvm-svn: 129517
2011-04-14 14:33:36 +00:00
f8b4c0035b
Disable auto-detection of AVX support since AVX codegen support is not ready.
...
llvm-svn: 121677
2010-12-13 04:23:53 +00:00
8b08f5232b
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable.
...
llvm-svn: 121439
2010-12-10 00:26:57 +00:00
2f489236ab
Add patterns for the x86 popcnt instruction.
...
- Also adds a new POPCNT subtarget feature that is currently enabled if the target
supports SSE4.2 (nehalem) or SSE4A (barcelona).
llvm-svn: 120917
2010-12-04 20:32:23 +00:00
4cf25f5ba9
Clean up comments.
...
llvm-svn: 117785
2010-10-30 13:48:28 +00:00
c6e13f7383
Clean up asm writer usage for x86 and msp430 to flag that the writer should
...
use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.
llvm-svn: 115238
2010-09-30 23:40:25 +00:00
167b9d7f30
tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl',
...
target specific parsers can adapt the TargetAsmParser to this.
llvm-svn: 110888
2010-08-12 00:55:32 +00:00
d618c8ac64
Declare CLMUL as a subtarget feature
...
llvm-svn: 109207
2010-07-23 01:22:45 +00:00
b82cd9319b
MC/X86: We now match instructions like "incl %eax" correctly for the arch we are
...
assembling; remove crufty custom cleanup code.
llvm-svn: 108681
2010-07-19 06:14:54 +00:00
9b816a1bb3
MC/X86: Add "support" for matching ATT style mnemonic prefixes.
...
- The idea is that when a match fails, we just try to match each of +'b', +'w',
+'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
it. If all match, we assume it is width generic, and take the 'l' form.
- This would be a horrible hack, if it weren't so simple. Therefore it is an
elegant solution! Chris gets the credit for this particular elegant
solution. :)
- Next step to making this more robust is to have the X86 matcher generate the
mnemonic prefix information. Ideally we would also compute up-front exactly
which mnemonic to attempt to match, but this may require more custom code in
the matcher than is really worth it.
llvm-svn: 103012
2010-05-04 16:12:42 +00:00
b93331f3be
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
...
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
llvm-svn: 100384
2010-04-05 03:10:20 +00:00
2ef63183a5
Separate out the AES-NI instructions from the SSE4.2 instructions. Add
...
a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
llvm-svn: 100231
2010-04-02 21:54:27 +00:00
738b0f9ec7
Nehalem unaligned memory access is fast.
...
llvm-svn: 100089
2010-04-01 05:58:17 +00:00
f8d7eda663
Teach TableGen to understand X.Y notation in the TSFlagsFields strings.
...
Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.
llvm-svn: 99539
2010-03-25 18:52:01 +00:00
49e121d5e4
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
...
On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register
in a different domain than where it was defined. Some instructions have
equvivalents for different domains, like por/orps/orpd.
The SSEDomainFix pass tries to minimize the number of domain crossings by
changing between equvivalent opcodes where possible.
This is a work in progress, in particular the pass doesn't do anything yet. SSE
instructions are tagged with their execution domain in TableGen using the last
two bits of TSFlags. Note that not all instructions are tagged correctly. Life
just isn't that simple.
The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline
issue handled by NEONMoveFixPass. This pass may become target independent to
handle both.
llvm-svn: 99524
2010-03-25 17:25:00 +00:00
63ec093b6e
MC/X86/AsmMatcher: Use the new instruction cleanup routine to implement a
...
temporary workaround for matching inc/dec on x86_64 to the correct instruction.
- This hack will eventually be replaced with a robust mechanism for handling
matching instructions based on the available target features.
llvm-svn: 98858
2010-03-18 20:06:02 +00:00
77f7dba60c
all 64-bit cpus have cmov, this should fix CodeGen/X86/cmov.ll
...
(at least) on non-x86 builders.
llvm-svn: 98520
2010-03-14 22:24:34 +00:00
44ac89f517
revert r95949, it turns out that adding new prefixes is not a
...
great solution for the disassembler, we'll go with "plan b".
llvm-svn: 95957
2010-02-12 01:55:31 +00:00
336f9abb45
add another bit of space for new kinds of instruction prefixes.
...
llvm-svn: 95949
2010-02-12 01:15:16 +00:00
206351a1ff
Implement a feature (-vector-unaligned-mem) to allow targets to
...
ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
llvm-svn: 93151
2010-01-11 16:29:42 +00:00
71d7eaa87e
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
...
llvm-svn: 91910
2009-12-22 17:47:23 +00:00
4cf30b72bf
On recent Intel u-arch's, folding loads into some unary SSE instructions can
...
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
llvm-svn: 91672
2009-12-18 07:40:29 +00:00
04d8cb74f3
Instruction fixes, added instructions, and AsmString changes in the
...
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
llvm-svn: 91638
2009-12-18 00:01:26 +00:00
13306a1fff
remove a temporary hack.
...
llvm-svn: 82395
2009-09-20 07:47:59 +00:00
1cbd3ded33
split MCInst printing out of the X86ATTInstPrinter
...
class into its own X86ATTInstPrinter class. The inst
printer now has just one dependence on the code generator
(TRI).
llvm-svn: 81703
2009-09-13 19:30:11 +00:00
cc8c581a5b
Add support for modeling whether or not the processor has support for
...
conditional moves as a subtarget feature. This is the easy part of
PR4841.
llvm-svn: 80763
2009-09-02 05:53:04 +00:00
e431871851
llvm-mc/AsmParser: Allow target to specific a comment delimiter, which will be
...
used to strip hard coded comments out of .td assembly strings.
llvm-svn: 78716
2009-08-11 20:59:47 +00:00
0033199c50
Match X86 register names to number.
...
llvm-svn: 77404
2009-07-29 00:02:19 +00:00
46b56ffae3
Add processor descriptions for Istanbul and Shanghai.
...
llvm-svn: 74429
2009-06-29 16:54:06 +00:00
8f6f72cc99
Add feature flags for AVX and FMA and fix some SSE4A feature flag
...
initialization problems.
llvm-svn: 74350
2009-06-26 22:46:54 +00:00
5234d3795f
Revert 72707 and 72709, for the moment.
...
llvm-svn: 72712
2009-06-02 03:12:52 +00:00
7fde88cce8
Add missing file.
...
llvm-svn: 72709
2009-06-01 23:48:58 +00:00
96180b5387
Update CPU capabilities for AMD machines
...
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10
New processor names match those used by gcc.
Patch by Paul Redmond!
llvm-svn: 72434
2009-05-26 21:04:35 +00:00
7403751e16
Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has
...
SSE2, however it's possible to disable SSE2, and the subtarget support
code thinks that if 64-bit implies SSE2 and SSE2 is disabled then
64-bit should also be disabled. Instead, just mark all the 64-bit
subtargets as explicitly supporting SSE2.
Also, move the code that makes -march=x86-64 enable 64-bit support by
default to only apply when there is no explicit subtarget. If you
need to specify a subtarget and you want 64-bit code, you'll need to
select a subtarget that supports 64-bit code.
llvm-svn: 63575
2009-02-03 00:04:43 +00:00
6e100a62b1
Add Intel processors core i7 and atom.
...
llvm-svn: 61603
2009-01-03 04:24:44 +00:00
4c91aa3418
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.
...
llvm-svn: 61557
2009-01-02 05:35:45 +00:00
977e7be9d4
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
...
llvm-svn: 59953
2008-11-24 07:34:46 +00:00
28106756af
Accept -march=i586, because gcc does (a synonym
...
for pentium). Fixes
gcc.target/i386/20000720-1.c
gcc.target/i386/pr26826.c
llvm-svn: 57528
2008-10-14 22:06:33 +00:00
2589777f3f
Add ability to override segment (mostly for code emitter purposes).
...
llvm-svn: 57380
2008-10-11 19:09:15 +00:00
0070dd1de3
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
...
llvm-svn: 47795
2008-03-01 13:37:02 +00:00
401a4d72d5
nocona, core2 and penryn support 64 bit.
...
llvm-svn: 47149
2008-02-15 01:22:41 +00:00
e14fdfaecd
SSE 4.1 Intrinsics and detection
...
llvm-svn: 46681
2008-02-03 07:18:54 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
1f0da1fefb
Corrected many typing errors. And removed 'nest' parameter handling
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for fastcc from X86CallingConv.td. This means that nested functions
are not supported for calling convention 'fastcc'.
llvm-svn: 42934
2007-10-12 21:30:57 +00:00
3fb7fdfded
We only need to specify the most-implied feature for an architecture.
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llvm-svn: 37275
2007-05-22 05:15:37 +00:00
f985c492e1
3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX.
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llvm-svn: 36860
2007-05-06 07:56:19 +00:00
e6182267d7
Add an "implies" field to features. This indicates that, if the current
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feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.
llvm-svn: 36756
2007-05-04 20:38:40 +00:00
157d7ee7e5
Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers
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clobbered by a call.
llvm-svn: 36448
2007-04-25 21:31:48 +00:00
f099841573
Add support for our first SSSE3 instruction "pmulhrsw".
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llvm-svn: 35869
2007-04-10 22:10:25 +00:00
5d00a0b8a9
Add a description of the X86-64 calling convention and the return
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conventions. This doesn't do anything yet, but may in the future.
llvm-svn: 34636
2007-02-26 18:17:14 +00:00
ff1beda569
Still need to support -mcpu=<> or cross compilation will fail. Doh.
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llvm-svn: 30764
2006-10-06 09:17:41 +00:00
9274f72e58
Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support.
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llvm-svn: 30763
2006-10-06 08:21:07 +00:00
11b0a5dbd4
Committing X86-64 support.
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llvm-svn: 30177
2006-09-08 06:48:29 +00:00
03524c63ff
ImmMask should be 3 for a two-bit field; Compact X86II
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llvm-svn: 28381
2006-05-18 06:27:15 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
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llvm-svn: 28378
2006-05-18 00:12:58 +00:00
dcec882286
Remove PointerType from class Target
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llvm-svn: 28368
2006-05-17 21:20:27 +00:00
9e350cd6ad
- Use xor to clear integer registers (set R, 0).
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- Added a new format for instructions where the source register is implied
and it is same as the destination register. Used for pseudo instructions
that clear the destination register.
llvm-svn: 25872
2006-02-01 06:13:50 +00:00
c642aa5e1c
* Fix 80-column violations
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* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
llvm-svn: 25854
2006-01-31 19:43:35 +00:00
4ab39e43e8
Fix typo.
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llvm-svn: 25760
2006-01-29 03:45:35 +00:00
cde9e30bc6
x86 CPU detection and proper subtarget support
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llvm-svn: 25679
2006-01-27 08:10:46 +00:00
1240574609
PHI and INLINEASM are now built-in instructions provided by Target.td
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llvm-svn: 25674
2006-01-27 01:46:15 +00:00
54c13da29c
Added preliminary x86 subtarget support.
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llvm-svn: 25645
2006-01-26 09:53:06 +00:00
a0b5e035ea
Get closer to fully working scalar FP in SSE regs. This gets singlesource
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working, and Olden/power.
llvm-svn: 22441
2005-07-15 00:38:55 +00:00
8a0933608a
First round of support for doing scalar FP using the SSE2 ISA extension and
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XMM registers. There are many known deficiencies and fixmes, which will be
addressed ASAP. The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.
The x86 backend will still default to x87 style FP. To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.
An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
Sum += P[i]; return Sum; }
The inner loop looks like the following:
x87:
.LBB_foo_1: # no_exit
fldl (%esp)
faddl (%eax,%ecx,8)
fstpl (%esp)
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
SSE2:
addsd (%eax,%ecx,8), %xmm0
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
llvm-svn: 22340
2005-07-06 18:59:04 +00:00
5683260187
Add support for the -x86-asm-syntax flag, which can be used to choose between
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Intel and AT&T style assembly language. The ultimate goal of this is to
eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission
is not fully operational.
llvm-svn: 16639
2004-10-03 20:36:57 +00:00
eb34c59930
Remove a bunch of ad-hoc target-specific flags that were only used by the
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old asmprinter.
llvm-svn: 15660
2004-08-11 07:12:04 +00:00
27fcf976f2
Eliminate 3 of the X86 printImplicit* flags.
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llvm-svn: 15398
2004-08-01 08:23:17 +00:00
27b2e2cdc0
Add support for the printImplicitDefsBefore flag
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llvm-svn: 12893
2004-04-13 17:18:39 +00:00
10db062d41
Added the llvm.readport and llvm.writeport intrinsics for x86. These do
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I/O port instructions on x86. The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output. This required adjustment to some
methods so that a leading comma would or would not be printed.
llvm-svn: 12782
2004-04-08 20:31:47 +00:00
9fe1646804
Add FP conditional move instructions, which annoyingly have special properties
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that require the asmwriter to be extended (printing implicit uses before the
explicit operands)
llvm-svn: 12574
2004-03-31 22:02:13 +00:00
194939086d
Each instruction now has both an ImmType and a MemType. This describes
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the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).
llvm-svn: 11967
2004-02-28 22:02:05 +00:00
29265fe981
Added LLVM copyright header.
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llvm-svn: 9321
2003-10-21 15:17:13 +00:00
fb2054c40b
Completely eliminate the isVoid TSFlag, shifting over all other fields
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llvm-svn: 7636
2003-08-06 15:32:20 +00:00
22c550e442
There is nothing special about noops anymore
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llvm-svn: 7568
2003-08-04 05:11:37 +00:00
2551080937
transition to using let instead of set
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llvm-svn: 7564
2003-08-04 04:59:56 +00:00
59a4a91703
Add new TableGen instruction definitions
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llvm-svn: 7537
2003-08-03 21:54:21 +00:00
a8c3cff30f
Add Target class for X86 target
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llvm-svn: 7523
2003-08-03 18:19:37 +00:00
5da8e80c46
Initial checkin of X86.td file
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llvm-svn: 7510
2003-08-03 15:47:49 +00:00
Craig Topper