Commit Graph

3330 Commits

Author SHA1 Message Date
Rafael Espindola 9ef844165a Don't lose the thumb bit by using relocations with sections.
This fixes a regression from r205076.

llvm-svn: 206047
2014-04-11 19:18:01 +00:00
Daniel Sanders 4b43e91abc Revert: r205182 - llvm/test/MC/Mips/mips64r2/valid-xfail.s: This REQUIRES asserts. Seems it doesn't fail with -Asserts.
This was most likely caused by an uninitialized value and the relevant code was re-written in r205292. Reverting to see if it still fails on any of the buildbots.

llvm-svn: 206033
2014-04-11 15:33:36 +00:00
Kaelyn Takata f7c12fcd83 Remove the use of "%e" as it is not a valid expansion like "%t".
llvm-svn: 205991
2014-04-10 21:55:58 +00:00
David Blaikie 8019bf815d Reimplement debug info compression by compressing the whole section, rather than a fragment.
To support compressing the debug_line section that contains multiple
fragments (due, I believe, to variation in choices of line table
encoding depending on the size of instruction ranges in the actual
program code) we needed to support compressing multiple MCFragments in a
single pass.

This patch implements that behavior by mutating the post-relaxed and
relocated section to be the compressed form of its former self,
including renaming the section.

This is a more flexible (and less invasive, to a degree) implementation
that will allow for other features such as "use compression only if it's
smaller than the uncompressed data".

Compressing debug_frame would be a possible further extension to this
work, but I've left it for now. The hurdle there is alignment sections -
which might require going as far as to refactor
MCAssembler.cpp:writeFragment to handle writing to a byte buffer or an
MCObjectWriter (there's already a virtual call there, so it shouldn't
add substantial compile-time cost) which could in turn involve
refactoring MCAsmBackend::writeNopData to use that same abstraction...
which involves touching all the backends. This would remove the limited
handling of fragment writing seen in
ELFObjectWriter.cpp:getUncompressedData which would be nice - but it's
more invasive.

I did discover that I (perhaps obviously) don't need to handle
relocations when I rewrite the fragments - since the relocations have
already been applied and computed (and stored into
ELFObjectWriter::Relocations) by this stage (necessarily, because we
need to have written any immediate values or assembly-time relocations
into the data already before we compress it, which we have). The test
case doesn't necessarily cover that in detail - I can add more test
coverage if that's preferred.

llvm-svn: 205990
2014-04-10 21:53:53 +00:00
David Blaikie 4d3b043542 Revert debug info compression support.
To support compression for debug_line and debug_frame a different
approach is required. To simplify review, revert the old implementation
and XFAIL the test case. New implementation to follow shortly.

Reverts r205059 and r204958.

llvm-svn: 205989
2014-04-10 21:53:47 +00:00
Kevin Enderby 488f20b64e For the ARM integrated assembler add checking of the
alignments on vld/vst instructions.  And report errors for
alignments that are not supported.

While this is a large diff and an big test case, the changes
are very straight forward.  But pretty much had to touch
all vld/vst instructions changing the addrmode to one of the
new ones that where added will do the proper checking for
the specific instruction.

FYI, re-committing this with a tweak so MemoryOp's default
constructor is trivial and will work with MSVC 2012. Thanks
to Reid Kleckner and Jim Grosbach for help with the tweak.

rdar://11312406

llvm-svn: 205986
2014-04-10 20:18:58 +00:00
Daniel Sanders ca275d2a14 [mips] Switch the MIPS-III and MIPS-IV assembler tests to use -mcpu=mips4.
Summary:
It is now the smallest superset for these ISA's.

FeatureMips4 now contains FeatureFPIdx since [ls][dw]xc1 were added in MIPS-IV.
Made the FPIdx feature bit lowercase so that it can be used in the -mattr option.

Depends on D3274

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3275

llvm-svn: 205964
2014-04-10 13:16:49 +00:00
Reid Kleckner 2d4a69e9c9 Revert "For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported."
It doesn't build with MSVC 2012, because MSVC doesn't allow union
members that have non-trivial default constructors.  This change added
'SMLoc AlignmentLoc' to MemoryOp, which made MemoryOp's default ctor
non-trivial.

This reverts commit r205930.

llvm-svn: 205944
2014-04-10 00:52:14 +00:00
Kevin Enderby c296ecd96c For the ARM integrated assembler add checking of the
alignments on vld/vst instructions.  And report errors for
alignments that are not supported.

While this is a large diff and an big test case, the changes
are very straight forward.  But pretty much had to touch
all vld/vst instructions changing the addrmode to one of the
new ones that where added will do the proper checking for
the specific instruction.

rdar://11312406

llvm-svn: 205930
2014-04-09 21:32:59 +00:00
Alp Toker 16f98b255d Fix some doc and comment typos
llvm-svn: 205899
2014-04-09 14:47:27 +00:00
Bradley Smith 246b0b617d [ARM64] Change SYS without a register to an alias to make disassembling more consistant.
llvm-svn: 205898
2014-04-09 14:44:58 +00:00
Bradley Smith 2cef19a2e6 [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.
llvm-svn: 205897
2014-04-09 14:44:54 +00:00
Bradley Smith 239120cada [ARM64] Properly support both apple and standard syntax for FMOV
llvm-svn: 205896
2014-04-09 14:44:49 +00:00
Bradley Smith a2308f47d3 [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.
llvm-svn: 205895
2014-04-09 14:44:44 +00:00
Bradley Smith f280e91849 [ARM64] Conditional branches must always print their condition code, even AL.
llvm-svn: 205894
2014-04-09 14:44:39 +00:00
Bradley Smith a19b7e83dc [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.
llvm-svn: 205893
2014-04-09 14:44:36 +00:00
Bradley Smith 70c6acbbfd [ARM64] Add missing shifted register MVN alias to ORN
llvm-svn: 205891
2014-04-09 14:44:26 +00:00
Bradley Smith 403bbf95c0 [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.
llvm-svn: 205890
2014-04-09 14:44:22 +00:00
Bradley Smith 779238a216 [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias.
llvm-svn: 205889
2014-04-09 14:44:18 +00:00
Bradley Smith f823079acd [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types
llvm-svn: 205888
2014-04-09 14:44:12 +00:00
Bradley Smith af2710c96f [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.
llvm-svn: 205887
2014-04-09 14:44:07 +00:00
Bradley Smith a0dce246ed [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions.
llvm-svn: 205886
2014-04-09 14:44:03 +00:00
Bradley Smith 3971d3dc75 [ARM64] Rename LR to the UAL-compliant 'X30'.
llvm-svn: 205885
2014-04-09 14:43:59 +00:00
Bradley Smith 6f1aa59c31 [ARM64] Rename FP to the UAL-compliant 'X29'.
llvm-svn: 205884
2014-04-09 14:43:50 +00:00
Bradley Smith 5511f08055 [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value.
llvm-svn: 205883
2014-04-09 14:43:40 +00:00
Bradley Smith eb4ca04db2 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.
llvm-svn: 205882
2014-04-09 14:43:35 +00:00
Bradley Smith db7b9b17eb [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear.
llvm-svn: 205881
2014-04-09 14:43:31 +00:00
Bradley Smith 7525b47208 [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.
llvm-svn: 205879
2014-04-09 14:43:24 +00:00
Bradley Smith 0243aa33fa [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu.
llvm-svn: 205878
2014-04-09 14:43:20 +00:00
Bradley Smith 8f906a3c5f [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.
llvm-svn: 205877
2014-04-09 14:43:15 +00:00
Bradley Smith 9f29b726d5 [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
llvm-svn: 205876
2014-04-09 14:43:11 +00:00
Bradley Smith e8b4166acc [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.
llvm-svn: 205875
2014-04-09 14:43:06 +00:00
Bradley Smith bc35b1f138 [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.
llvm-svn: 205874
2014-04-09 14:43:01 +00:00
Bradley Smith 16478c4ccf [ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.
llvm-svn: 205871
2014-04-09 14:42:49 +00:00
Bradley Smith fb90df563f [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.
llvm-svn: 205869
2014-04-09 14:42:42 +00:00
Bradley Smith 08c391c156 [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.
llvm-svn: 205868
2014-04-09 14:42:36 +00:00
Bradley Smith 8c0b88c987 [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.
llvm-svn: 205865
2014-04-09 14:42:11 +00:00
Bradley Smith 527bf86e56 [ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)
llvm-svn: 205864
2014-04-09 14:42:07 +00:00
Bradley Smith 6d7af17a3f [ARM64] Add missing 1Q -> 1q vector kind alias
llvm-svn: 205863
2014-04-09 14:42:01 +00:00
Bradley Smith 7d253f29a4 [ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}
llvm-svn: 205862
2014-04-09 14:41:58 +00:00
Bradley Smith 664aa67153 [ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX
llvm-svn: 205861
2014-04-09 14:41:53 +00:00
Bradley Smith 35cadc58c9 [ARM64] STRHro and STRBro were not being decoded at all.
llvm-svn: 205860
2014-04-09 14:41:49 +00:00
Bradley Smith 87c60e00d5 [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.
llvm-svn: 205859
2014-04-09 14:41:45 +00:00
Bradley Smith cd91e5cd0c [ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined.
llvm-svn: 205858
2014-04-09 14:41:38 +00:00
David Majnemer a9bdb32f04 WinCOFF: Emit common symbols as specified in the COFF spec
Summary:
Local common symbols were properly inserted into the .bss section.
However, putting external common symbols in the .bss section would give
them a strong definition.

Instead, encode them as undefined, external symbols who's symbol value
is equivalent to their size.

Reviewers: Bigcheese, rafael, rnk

CC: llvm-commits

Differential Revision: http://reviews.llvm.org/D3324

llvm-svn: 205811
2014-04-08 22:33:40 +00:00
Kevin Enderby d88fec3d3a Fix the ARM VLD3 (single 3-element structure to all lanes)
size 16 double-spaced registers instruction printing.

This:
	vld3.16 {d0[], d2[], d4[]}, [r4]!

was being printed as:

	vld3.16	{d0[], d1[], d2[]}, [r4]!

rdar://16531387

llvm-svn: 205779
2014-04-08 18:00:52 +00:00
NAKAMURA Takumi 35289340de X86MCAsmInfoGNUCOFF: Set PointerSize as 8 for targeting x64. It caused DW_LNE_set_address was misemitted on x64.
FIXME: I haven't investigate whether CalleeSaveStackSlotSize should be 8.
llvm-svn: 205772
2014-04-08 15:28:50 +00:00
Saleem Abdulrasool dd979e6457 ARM: consolidate MachO checks for ARM asm parser
This consolidates the duplicated MachO checks in the directive parsing for
various directives that are unsupported for Mach-O.  The error message change is
unimportant as this restores the behaviour to that prior to the addition of the
new directive handling.  Furthermore, use a more direct check for MachO
targeting rather than an indirect feature check of the assembler.

Also simplify the test execution command to avoid temporary files.  Further more,
perform the check in both object and assembly emission.

Whether all non-applicable directives are handled is another question.  .fnstart
is marked as being unsupported, however, the complementary .fnend is not.  The
additional unwinding directives are also still honoured.  This change does not
change that, though, it would be good to validate and mark them as being
unsupported if they are unsupported for the MachO emission.

llvm-svn: 205678
2014-04-05 22:09:51 +00:00
Kai Nacke 6da86e8529 [mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.
This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.
It is only for the assembler. Test case is included.

Reviewed by: Daniel.Sanders@imgtec.com

llvm-svn: 205631
2014-04-04 16:21:59 +00:00
Stepan Dyatkovskiy 3f1fa3d545 Fix for PR18921 (LDRD/STRD part)::
Removed "GNU Assembler extension (compatibility)" definitions from ARMInstrInfo.td
Fixed ARMAsmParser::ParseInstruction GNU compatability branch, so it also works for thumb mode from now.
Added new tests.

llvm-svn: 205622
2014-04-04 10:17:56 +00:00