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Author SHA1 Message Date
Chris Dewhurst 52adb575e6 This change adds co-processor condition branching and conditional traps to the Sparc back-end. 
This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5".

The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided.

The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals.

Check-in includes many extra unit tests to check this works correctly on both V8 and V9 Sparc processors.

Code Reviewed at http://reviews.llvm.org/D17960.

llvm-svn: 263044
 2016-03-09 18:20:21 +00:00
James Y Knight 26fc9bf682 [SPARC] Repair floating-point condition encodings in assembly parser. 
The encodings for floating point conditions A(lways) and N(ever) were
incorrectly specified for the assembly parser, per Sparc manual v8 page
121. This change corrects that mistake.

Also, strangely, all of the branch instructions already had MC test
cases, except for the broken ones. Added the tests.

Patch by Chris Dewhurst

Differential Revision: http://reviews.llvm.org/D17074

llvm-svn: 260390
 2016-02-10 17:47:20 +00:00
Venkatraman Govindaraju 925ec9b11e [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend. 
llvm-svn: 202670
 2014-03-02 23:39:07 +00:00
Venkatraman Govindaraju 07d3af2821 [Sparc] Add return/rett instruction to Sparc backend. 
llvm-svn: 202666
 2014-03-02 22:55:53 +00:00
Venkatraman Govindaraju b745e67a64 [SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr). 
llvm-svn: 202628
 2014-03-02 09:46:56 +00:00
Venkatraman Govindaraju 600f390bb9 [Sparc] Add support for parsing branches and conditional move instructions with %fcc1-%fcc3 conditional registers. 
llvm-svn: 202616
 2014-03-02 06:28:15 +00:00
Venkatraman Govindaraju c86e0f3873 [SparcV9] Add support for parsing branch instructions with prediction. 
llvm-svn: 202602
 2014-03-01 22:03:07 +00:00
Venkatraman Govindaraju b3b7c38983 [Sparc] Add support for parsing branch instructions and conditional moves. 
llvm-svn: 198738
 2014-01-08 06:14:52 +00:00