Commit Graph

25792 Commits

Author SHA1 Message Date
Akira Hatanaka ee909cc27f [mips] Simplify and optimize code.
No intended functionality change.

llvm-svn: 192213
2013-10-08 18:13:24 +00:00
Reed Kotler 97309af4f4 Let rotr and bswap be handled by expansion for Mips16 since we don't
have native instructions for this.

llvm-svn: 192207
2013-10-08 17:32:33 +00:00
Rafael Espindola a17151ad5a Add a MCTargetStreamer interface.
This patch fixes an old FIXME by creating a MCTargetStreamer interface
and moving the target specific functions for ARM, Mips and PPC to it.

The ARM streamer is still declared in a common place because it is
used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are
completely hidden in the corresponding Target directories.

I will send an email to llvmdev with instructions on how to use this.

llvm-svn: 192181
2013-10-08 13:08:17 +00:00
NAKAMURA Takumi c22f85331c SparcJITInfo.cpp: Prune "default:" label to fix a warning. [-Wcovered-switch-default]
llvm-svn: 192179
2013-10-08 10:29:09 +00:00
NAKAMURA Takumi 2949f670d5 Prune trailing linefeeds.
llvm-svn: 192178
2013-10-08 10:29:03 +00:00
Venkatraman Govindaraju 2ea4c2880c [Sparc] Implement JIT for SPARC.
No new testcases. However, this patch makes all supported JIT testcases in 
test/ExecutionEngine  pass on Sparc.

llvm-svn: 192176
2013-10-08 07:15:22 +00:00
Craig Topper a984729f8a Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building.
llvm-svn: 192175
2013-10-08 06:30:39 +00:00
Craig Topper 72c8cd7bc3 Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
llvm-svn: 192171
2013-10-08 05:53:50 +00:00
Venkatraman Govindaraju 8223c553cf [Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead.
llvm-svn: 192160
2013-10-08 02:50:29 +00:00
Reed Kotler 445d0adc24 Add Mips16 patterns for sign extend byte and sign extend halfword.
llvm-svn: 192130
2013-10-07 20:46:19 +00:00
Manman Ren 5a78755336 Struct byval: use the correct alignment for loads generated to load
from struct byval to registers.

We used to pass 0 which means the alignment of PtrVT. Even when the alignment
of the struct is smaller than 4, the LOADs would have alignment of 4, and
further optimizations could combine the LOADs into a ldm, which would
cause crash.

The fix is to pass the alignment of the struct byval.

rdar://problem/15144402

llvm-svn: 192126
2013-10-07 19:47:53 +00:00
Akira Hatanaka 4c0a71223a [mips] Coding style clean up.
llvm-svn: 192125
2013-10-07 19:33:02 +00:00
Akira Hatanaka 3c0d6afeec [mips] Disable tail merging when long branch pass is enabled.
llvm-svn: 192124
2013-10-07 19:13:53 +00:00
Benjamin Kramer 7b5e159450 X86: Fix type check. Just because an integer type is illegal doesn't mean it's i64.
Fixes PR17495, where an i24 triggered this code. It's intended to
optimize i64 loads on 32 bit x86.

llvm-svn: 192123
2013-10-07 19:11:35 +00:00
Akira Hatanaka a8a05be7d6 [mips] Define method MipsSubtarget::enableLongBranchPass.
llvm-svn: 192122
2013-10-07 19:06:57 +00:00
Akira Hatanaka 16048332f1 [mips] Fix definition of mfhi and mflo instructions to read from the whole
accumulator instead of its sub-registers, $hi and $lo. 

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2     // read lower 32-bit result from $lo.
mtlo $4     // write to $lo. the content of $hi becomes unpredictable.
mfhi $3     // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.

llvm-svn: 192119
2013-10-07 18:49:46 +00:00
Amara Emerson 5035ee0212 [ARM] Improve build attributes emission.
llvm-svn: 192111
2013-10-07 16:55:23 +00:00
Chad Rosier b6ceeb9126 [AArch64] Add support for NEON scalar arithmetic instructions:
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

llvm-svn: 192107
2013-10-07 16:36:15 +00:00
Rafael Espindola e90fd9c5e0 Remove getEHExceptionRegister and getEHHandlerRegister.
They haven't been used for a long time. Patch by MathOnNapkins.

llvm-svn: 192099
2013-10-07 13:39:22 +00:00
Tim Northover f86d1f0b77 ARM: allow cortex-m0 to use hint instructions
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.

rdar://problem/15144406

llvm-svn: 192097
2013-10-07 11:10:47 +00:00
Craig Topper 07ad1b23bb Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.
llvm-svn: 192090
2013-10-07 07:19:47 +00:00
Craig Topper 68d2546ec6 Remove FsMOVAPSrr and friends. They have no patterns and are no longer selected anywhere.
llvm-svn: 192089
2013-10-07 06:10:45 +00:00
Craig Topper a0e0735e6a Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not.
This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this.

llvm-svn: 192088
2013-10-07 05:42:48 +00:00
Craig Topper 2658d89728 Add disassembler support for long encodings for INC/DEC in 32-bit mode.
llvm-svn: 192086
2013-10-07 04:28:06 +00:00
Benjamin Kramer 858a3880d6 X86: Don't fold spills into SSE operations if the stack is unaligned.
Regalloc can emit unaligned spills nowadays, but we can't fold the
spills into SSE ops if we can't guarantee alignment. PR12250.

llvm-svn: 192064
2013-10-06 13:48:22 +00:00
Elena Demikhovsky 2e408aefe0 AVX-512: added scalar convert instructions and intrinsics.
Fixed load folding in VPERM2I instruction.

llvm-svn: 192063
2013-10-06 13:11:09 +00:00
Venkatraman Govindaraju f482d3d338 [Sparc] Do not emit nop after fcmp* instruction with V9.
llvm-svn: 192056
2013-10-06 07:06:44 +00:00
Elena Demikhovsky 462a2d235b AVX-512: fixed shuffle lowering
in case of BLEND and added VSHUFPS patterns.

llvm-svn: 192055
2013-10-06 06:11:18 +00:00
Venkatraman Govindaraju 572d5057e3 [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.
This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.

llvm-svn: 192054
2013-10-06 03:36:18 +00:00
Venkatraman Govindaraju 1230342fd2 [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.
addx/subx does not modify conditional codes whereas addxcc/subxx does.

llvm-svn: 192053
2013-10-06 02:11:10 +00:00
Craig Topper c81e29435a Add TBM instructions to loading folding tables.
llvm-svn: 192046
2013-10-05 20:20:51 +00:00
Nick Lewycky 3be42b8f06 Rename this feature to "cx16" to match gcc's flag name. Apparently these strings
are directly tied to the flag names in clang with no remapping in between?

llvm-svn: 192044
2013-10-05 20:11:44 +00:00
Craig Topper 9a9468ee02 Remove underscores from TBM instruction names for consistency with other instruction naming.
llvm-svn: 192040
2013-10-05 19:27:26 +00:00
Craig Topper 52196640a2 Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient.
llvm-svn: 192039
2013-10-05 19:22:59 +00:00
Craig Topper 80bd135e7a Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x).
llvm-svn: 192037
2013-10-05 17:17:53 +00:00
Rafael Espindola ac4ad25a00 Remove some really nasty uses of hasRawTextSupport.
When MC was first added, targets could use hasRawTextSupport to keep features
working before they were added to the MC interface.

The design goal of MC is to provide an uniform api for printing assembly and
object files. Short of relaxations and other corner cases, a object file is
just another representation of the assembly.

It was never the intention that targets would keep doing things like

if (hasRawTextSupport())
  Set flags in one way.
else
  Set flags in another way.

When they do that they create two code paths and the object file is no longer
just another representation of the assembly. This also then requires testing
with llc -filetype=obj, which is extremelly brittle.

This patch removes some of these hacks by replacing them with smaller ones.
The ARM flag setting is trivial, so I just moved it to the constructor. For
Mips, the patch adds two temporary hack directives that allow the assembly
to represent the same things as the object file was already able to.

The hope is that the mips developers will replace the hack directives with
the same ones that gas uses and drop the -print-hack-directives flag.

I will also try to implement a target streamer interface, so that we can
move this out of the common code.

In summary, for any new work, two rules of the thumb are
  * Don't use "llc -filetype=obj" in tests.
  * Don't add calls to hasRawTextSupport.

llvm-svn: 192035
2013-10-05 16:42:21 +00:00
Jiangning Liu ad242fbb71 Implement aarch64 neon instruction set AdvSIMD (Across).
llvm-svn: 192028
2013-10-05 08:22:10 +00:00
Venkatraman Govindaraju ece63dbd0d [Sparc] Use correct alignment while loading/storing fp128 values.
llvm-svn: 192023
2013-10-05 02:29:47 +00:00
Venkatraman Govindaraju 30781deb1c [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand.
llvm-svn: 192015
2013-10-05 00:31:41 +00:00
Venkatraman Govindaraju 84f1523cac [Sparc] Correct the floating point conditional code mapping in GetOppositeBranchCondition().
llvm-svn: 192006
2013-10-04 23:54:30 +00:00
Jack Carter 215527449d forgot to remove this file as well
llvm-svn: 191993
2013-10-04 22:54:05 +00:00
Jack Carter 13d5f753f8 reverting per request
llvm-svn: 191992
2013-10-04 22:52:31 +00:00
Reed Kotler 1b5b5c95cc Support tblockaddr for static compilation in Mips16.
llvm-svn: 191986
2013-10-04 22:01:40 +00:00
Jack Carter 721726adfc [MC][AsmParser] Hook for post assembly file processing
This patch handles LLVM standalone assembler (llvm-mc) ELF flag setting based on input file
directive processing.

Mips assembly requires processing inline directives that directly and
indirectly affect the output ELF header flags. This patch handles one
".abicalls".

To process these directives we are following the model the code generator
uses by storing state in a container as we go through processing and when
we detect the end of input file processing, AsmParser is notified and we
update the ELF header flags through a MipsELFStreamer method with a call from
MCTargetAsmParser::emitEndOfAsmFile(MCStreamer &OutStreamer).

This patch will allow other targets the same functionality.

Jack

llvm-svn: 191982
2013-10-04 21:26:15 +00:00
Akira Hatanaka 55504b4ac9 [mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing
instructions in delay slots along with the original branch instructions.

llvm-svn: 191978
2013-10-04 20:51:40 +00:00
Matthias Braun 2f169f900b ARM: optimizeSelect has to consider the previous register class
optimizeSelect folds (predicated) copy instructions, it must not ignore
the original register class of the operand when replacing the register
with the copies dest register.

llvm-svn: 191963
2013-10-04 16:52:56 +00:00
Matthias Braun c22630e164 ARM: do not add a regmask for TAILJUMPs
The jump doesn't really kill the registers, the following call does but
we never get back anyway.
This avoids some verify-machineinstrs problems when TAILJUMPs are
if-converted.

llvm-svn: 191962
2013-10-04 16:52:54 +00:00
Matthias Braun da621165ca ARM: preserve undef flag in pseudo instruction expanders
Copy over the whole register machine operand instead of creating a new one
with an incomplete set of flags.

llvm-svn: 191961
2013-10-04 16:52:51 +00:00
Jiangning Liu ac5fd7e5d3 Implement aarch64 neon instruction set AdvSIMD (3V elem).
llvm-svn: 191944
2013-10-04 09:20:44 +00:00
Elena Demikhovsky 85aeffaf5c AVX-512: Fixed encoding of VMOVQ instruction.
llvm-svn: 191889
2013-10-03 12:03:26 +00:00