llvm-project

Commit Graph

Author	SHA1	Message	Date
Tim Northover	4a58db65a5	ARM: fix part of test which actually needed an asserts build This should fix a buildbot failure that occurred after r179977. llvm-svn: 179978	2013-04-21 12:20:19 +00:00
Tim Northover	798697d662	ARM: Use ldrd/strd to spill 64-bit pairs when available. This allows common sp-offsets to be part of the instruction and is probably faster on modern CPUs too. llvm-svn: 179977	2013-04-21 11:57:07 +00:00
Tim Northover	d9d4211fe2	ARM: don't add FrameIndex offset for LDMIA (has no immediate) Previously, when spilling 64-bit paired registers, an LDMIA with both a FrameIndex and an offset was produced. This kind of instruction shouldn't exist, and the extra operand was being confused with the predicate, causing aborts later on. This removes the invalid 0-offset from the instruction being produced. llvm-svn: 179956	2013-04-20 19:31:00 +00:00

Author

SHA1

Message

Date

Tim Northover

4a58db65a5

ARM: fix part of test which actually needed an asserts build

This should fix a buildbot failure that occurred after r179977.

llvm-svn: 179978

2013-04-21 12:20:19 +00:00

Tim Northover

798697d662

ARM: Use ldrd/strd to spill 64-bit pairs when available.

This allows common sp-offsets to be part of the instruction and is
probably faster on modern CPUs too.

llvm-svn: 179977

2013-04-21 11:57:07 +00:00

Tim Northover

d9d4211fe2

ARM: don't add FrameIndex offset for LDMIA (has no immediate)

Previously, when spilling 64-bit paired registers, an LDMIA with both
a FrameIndex and an offset was produced. This kind of instruction
shouldn't exist, and the extra operand was being confused with the
predicate, causing aborts later on.

This removes the invalid 0-offset from the instruction being
produced.

llvm-svn: 179956

2013-04-20 19:31:00 +00:00

3 Commits