bfdc557c8a
Expand unaligned 32 bit loads from an address which is a constant
...
offset from a 32 bit aligned base as follows:
ldw low, base[offset >> 2]
ldw high, base[(offset >> 2) + 1]
shr low_shifted, low, (offset & 0x3) * 8
shl high_shifted, high, 32 - (offset & 0x3) * 8
or result, low_shifted, high_shifted
Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.
llvm-svn: 75902
2009-07-16 10:42:35 +00:00
25b33cb035
Custom lower unaligned 32 bit stores and loads into libcalls. This is
...
a big code size win since before they were expanding to upto 16
instructions.
llvm-svn: 75901
2009-07-16 10:21:18 +00:00
a8edd048c2
Fix pattern for LD16S_3r, add basic tests to check load / store instructions
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are being properly selected.
llvm-svn: 75797
2009-07-15 17:06:59 +00:00
57489b0658
Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs.
...
llvm-svn: 75788
2009-07-15 15:46:56 +00:00
a5b9645c4b
Split the Add, Sub, and Mul instruction opcodes into separate
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integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.
For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.
This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt
llvm-svn: 72897
2009-06-04 22:49:04 +00:00
9030c35eb4
Fix for PR4235: to build a floating-point value from integer parts,
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build an integer and cast that to a float. This fixes a crash
caused by trying to split an f32 into two f16's.
This changes the behavior in test/CodeGen/XCore/fneg.ll because that
testcase now triggers a DAGCombine which converts the fneg into an integer
operation. If someone is interested, it's probably possible to tweak
the test to generate an actual fneg.
llvm-svn: 72162
2009-05-20 06:02:09 +00:00
1e7da23983
testcase for PR3898
...
llvm-svn: 69473
2009-04-18 20:49:22 +00:00
6de96a1b5d
Add the private linkage.
...
llvm-svn: 62279
2009-01-15 20:18:42 +00:00
40119780a8
Don't fold address calculations which use negative offsets into
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the ADDRspii addressing mode.
llvm-svn: 62258
2009-01-15 11:32:30 +00:00
4359325ba8
Add pseudo instructions to the XCore for (load|store|load address) of a
...
frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.
This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.
llvm-svn: 62238
2009-01-14 18:26:46 +00:00
feece7edab
Add support for ISD::TRAP to the XCore backend
...
llvm-svn: 60479
2008-12-03 10:59:16 +00:00
1315f80ea8
Reapply r59464, this time using the correct type
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when softening FNEG.
llvm-svn: 59513
2008-11-18 09:15:03 +00:00
e0d5e67c98
Revert r59464. It was causing this failure:
...
Running /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/dg.exp ...
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/fneg.ll
Failed with signal(SIGABRT) at line 1
while running: llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/fneg.ll | llc -march=xcore > fneg.ll.tmp1.s
Assertion failed: (VT.isFloatingPoint() && "Cannot create integer FP constant!"), function getConstantFP, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/SelectionDAG.cpp, line 913.
0 llc 0x0092115c _ZN4llvm3sys18RemoveFileOnSignalERKNS0_4PathEPSs + 844
1 libSystem.B.dylib 0x9217809b _sigtramp + 43
2 ??? 0xffffffff 0x0 + 4294967295
3 libSystem.B.dylib 0x921f0ec2 raise + 26
4 libSystem.B.dylib 0x9220047f abort + 73
5 libSystem.B.dylib 0x921f2063 __assert_rtn + 101
6 llc 0x005a5b0a _ZN4llvm12SelectionDAG13getConmake[1]: *** [check-local] Error 1
make: *** [check] Error 2
llvm-svn: 59487
2008-11-18 01:49:24 +00:00
f046b50ecd
Add soft float support for a bunch more operations. Original
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patch by Richard Osborne, tweaked and extended by your humble
servant.
llvm-svn: 59464
2008-11-17 20:52:38 +00:00
6751b4a604
Don't produce ADDC/ADDE when expanding SHL unless they are legal
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for the target. This fixes PR3080.
llvm-svn: 59450
2008-11-17 17:34:31 +00:00
5fe5933909
[XCore] Fix expansion of 64 bit add/sub. Don't custom expand
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these operations if ladd/lsub are not available on the current
subtarget.
llvm-svn: 59305
2008-11-14 15:59:19 +00:00
d16b37efae
Add XCore intrinsics for getid (returns thread id) and bitrev (reverses
...
bits in a word).
llvm-svn: 59296
2008-11-14 10:12:16 +00:00
86d68a492a
Add basic test for XCore backend
...
llvm-svn: 58841
2008-11-07 11:24:12 +00:00
Richard Osborne