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10 Commits

Author SHA1 Message Date
Akira Hatanaka e86bd4f652 [mips] Split the DSP control register and define one register for each field of 
its fields.

This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.

llvm-svn: 181041
 2013-05-03 18:37:49 +00:00
Akira Hatanaka 044d028e3c MIPS DSP: add operands to make sure instruction strings are being matched. 
llvm-svn: 164849
 2012-09-28 21:23:16 +00:00
Akira Hatanaka d66f489640 MIPS DSP: other miscellaneous instructions. 
llvm-svn: 164845
 2012-09-28 20:50:31 +00:00
Akira Hatanaka a9183eda74 MIPS DSP: ABSQ_S.PH instruction sub-class. 
llvm-svn: 164787
 2012-09-27 19:09:21 +00:00
Akira Hatanaka 892b1046c6 MIPS DSP: SHLL.QB instruction sub-class. 
llvm-svn: 164786
 2012-09-27 19:05:08 +00:00
Akira Hatanaka 9e4e5a87c4 Test case for r164755 and 164756. 
llvm-svn: 164757
 2012-09-27 04:12:30 +00:00
Akira Hatanaka d09642beb3 MIPS DSP: ADDU.QB instruction sub-class. 
llvm-svn: 164754
 2012-09-27 03:13:59 +00:00
Akira Hatanaka e4bd054f98 MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction. 
llvm-svn: 164751
 2012-09-27 02:15:57 +00:00
Akira Hatanaka 9061a46443 MIPS DSP: all the remaining instructions which read or write accumulators. 
llvm-svn: 164750
 2012-09-27 02:11:20 +00:00
Akira Hatanaka 1babeaa44c MIPS DSP: add support for extract-word instructions. 
llvm-svn: 164749
 2012-09-27 02:05:42 +00:00