Commit Graph

5372 Commits

Author SHA1 Message Date
Asaf Badouh 9a5a83a518 [X86][PKU] Add {RD,WR}PKRU encoding
Differential Revision: http://reviews.llvm.org/D15711

llvm-svn: 256366
2015-12-24 08:25:00 +00:00
Akira Hatanaka 1cb242eb13 Provide a way to specify inliner's attribute compatibility and merging.
This reapplies r256277 with two changes:

- In emitFnAttrCompatCheck, change FuncName's type to std::string to fix
  a use-after-free bug.
- Remove an unnecessary install-local target in lib/IR/Makefile. 

Original commit message for r252949:

Provide a way to specify inliner's attribute compatibility and merging
rules using table-gen. NFC.

This commit adds new classes CompatRule and MergeRule to Attributes.td,
which are used to generate code to check attribute compatibility and
merge attributes of the caller and callee.

rdar://problem/19836465

llvm-svn: 256304
2015-12-22 23:57:37 +00:00
Dan Gohman db70d015ad Add an OperandNamespace field to Target.td's Operand.
For targets to add their own operand types as needed, as advertised in
Operand's comment, they need to be able to specify an alternate namespace
for OperandType names too. This matches the RegisterOperand class.

llvm-svn: 256299
2015-12-22 23:37:37 +00:00
Nico Weber 134b103fc0 lit: Limit number of processes on Windows to 32.
llvm-svn: 256291
2015-12-22 23:12:00 +00:00
Akira Hatanaka 9c05cc5670 Revert r256277 and r256279.
Some of the bots failed again.

llvm-svn: 256280
2015-12-22 20:29:09 +00:00
Akira Hatanaka a61deb249b Provide a way to specify inliner's attribute compatibility and merging.
This reapplies r252990 and r252949. I've added member function getKind
to the Attr classes which returns the enum or string of the attribute.

Original commit message for r252949:

Provide a way to specify inliner's attribute compatibility and merging
rules using table-gen. NFC.

This commit adds new classes CompatRule and MergeRule to Attributes.td,
which are used to generate code to check attribute compatibility and
merge attributes of the caller and callee.

rdar://problem/19836465

llvm-svn: 256277
2015-12-22 20:00:05 +00:00
Chih-Hung Hsieh 7993e18e80 [X86] Part 2 to fix x86-64 fp128 calling convention.
Part 1 was submitted in http://reviews.llvm.org/D15134.
Changes in this part:
* X86RegisterInfo.td, X86RecognizableInstr.cpp: Add FR128 register class.
* X86CallingConv.td: Pass f128 values in XMM registers or on stack.
* X86InstrCompiler.td, X86InstrInfo.td, X86InstrSSE.td:
  Add instruction selection patterns for f128.
* X86ISelLowering.cpp:
  When target has MMX registers, configure MVT::f128 in FR128RegClass,
  with TypeSoftenFloat action, and custom actions for some opcodes.
  Add missed cases of MVT::f128 in places that handle f32, f64, or vector types.
  Add TODO comment to support f128 type in inline assembly code.
* SelectionDAGBuilder.cpp:
  Fix infinite loop when f128 type can have
  VT == TLI.getTypeToTransformTo(Ctx, VT).
* Add unit tests for x86-64 fp128 type.

Differential Revision: http://reviews.llvm.org/D11438

llvm-svn: 255558
2015-12-14 22:08:36 +00:00
Ben Craig 46642ffeeb Reordering fields to reduce padding in LLVM. NFC
llvm-svn: 255554
2015-12-14 21:57:05 +00:00
Hal Finkel cd5f984670 [TableGen] Correct Namespace lookup with AltNames in AsmWriterEmitter
AsmWriterEmitter will generate a getRegisterName function with an alternate
register name index as its second argument if the target makes use of them. The
enum of these values is generated in RegisterInfoEmitter. The getRegisterName
generator would assume the namespace could always be found by reading index 1
of the list of AltNameIndices, but this will fail if this list is sorted such
that the NoRegAltName is at index 1. Because this list is sorted by record name
(in CodeGenTarget::ReadRegAltNameIndices), you only run in to problems if your
MyTargetRegisterInfo.td defines a single RegAltNameIndex that sorts lexically
before NoRegAltName.

For example, if a target has something like

  def AnAltNameIndex : RegAltNameIndex

and defines RegAltNameIndices for some registers then, prior to this change,
AsmWriterEmitter would generate references to

  ::AnAltNameIndex and ::NoRegAltName

Patch by Alex Bradbury!

llvm-svn: 255344
2015-12-11 17:31:27 +00:00
Hans Wennborg e59910cba9 Check in the script for building Win snapshots
llvm-svn: 255318
2015-12-11 00:43:42 +00:00
Alexey Bataev 860435c8e2 [OPENMP] Make -fopenmp to turn on OpenMP support by default.
Patch turns on OpenMP support in clang by default after fixing OpenMP buildbots.
Differential Revision: http://reviews.llvm.org/D13802

llvm-svn: 255222
2015-12-10 05:45:58 +00:00
Craig Topper 15576e1c8f Use make_range to reduce mentions of iterator type. NFC
llvm-svn: 254872
2015-12-06 05:08:07 +00:00
Craig Topper e5e035a3a8 Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.
llvm-svn: 254843
2015-12-05 07:13:35 +00:00
Craig Topper 1282df50c4 [TableGen] Remove an assumption about the order of encodings in the MVT::SimpleValueType enum. Instead of assuming the types are sorted by size, scan the typeset arrays to find the smallest/largest type. NFC
llvm-svn: 254589
2015-12-03 05:57:37 +00:00
Oliver Stannard a34e47066e [AArch64] Add ARMv8.2-A Statistical Profiling Extension
The Statistical Profiling Extension is an optional extension to
ARMv8.2-A. Since it is an optional extension, I have added the
FeatureSPE subtarget feature to control it. The assembler-visible parts
of this extension are the new "psb csync" instruction, which is
equivalent to "hint #17", and a number of system registers.

Differential Revision: http://reviews.llvm.org/D15021

llvm-svn: 254401
2015-12-01 10:48:51 +00:00
Craig Topper 3522ab30db [TableGen] Use SmallString instead of std::string to build up a string to avoid heap allocations. NFC
llvm-svn: 254221
2015-11-28 08:23:02 +00:00
Craig Topper 8985efe546 [TableGen] Sort pattern predicates before concatenating into a string so that different orders of the same set will produce the same string. This can reduce the number of unique predicates in the isel tables. NFC
llvm-svn: 254192
2015-11-27 05:44:04 +00:00
Craig Topper 9a44b3fa58 [SelectionDAG] Add a SDTCisSameSizeAs type constraint that can be used to ensure vector widths match even if the element size and count don't.
llvm-svn: 254138
2015-11-26 07:02:18 +00:00
Craig Topper 25ce6b82c6 [TableGen] Flip reversed comments.
llvm-svn: 254136
2015-11-26 06:30:40 +00:00
Krzysztof Parzyszek b8bb90b744 Add vector types for intrinsics
Author: Ron Lieberman <ronl@codeaurora.org>
llvm-svn: 253992
2015-11-24 16:28:14 +00:00
Krzysztof Parzyszek 47c1baeb1f Add names for the new vector types in CodeGenTarget.cpp
llvm-svn: 253989
2015-11-24 15:50:22 +00:00
Craig Topper 5712d46114 [TableGen] Use std::remove_if instead of manually coded loops that call erase multiple times. NFC
llvm-svn: 253964
2015-11-24 08:20:47 +00:00
Craig Topper 16f1cbd1e4 [TableGen] Use the other version of EnforceVectorEltTypeIs inside the TypeSet version of EnforceVectorEltTypeIs to reduce duplicated code. NFC
llvm-svn: 253963
2015-11-24 08:20:45 +00:00
Craig Topper dbfcc10e44 [TableGen] Fix formatting and use logical OR. NFC
llvm-svn: 253962
2015-11-24 08:20:44 +00:00
Craig Topper fef745c36a [TableGen] Use std::set_intersection to merge TypeSets. NFC
llvm-svn: 253961
2015-11-24 08:20:42 +00:00
Craig Topper 4856c81b46 [TableGen] Use SmallVector::assign instead of a resize and replace element.
llvm-svn: 253960
2015-11-24 08:20:41 +00:00
Craig Topper d324d75102 Revert change that accidentally snuck into r253955.
llvm-svn: 253956
2015-11-24 06:24:06 +00:00
Craig Topper 030418802a [TableGen] Use array_pod_sort. NFC
llvm-svn: 253955
2015-11-24 06:22:43 +00:00
James Y Knight 7c905063c5 Make utils/update_llc_test_checks.py note that the assertions are
autogenerated.

Also update existing test cases which appear to be generated by it and
weren't modified (other than addition of the header) by rerunning it.

llvm-svn: 253917
2015-11-23 21:33:58 +00:00
Craig Topper de2d7593a2 [TableGen] Use std::remove_if instead of manually coded loops that called erase inside them. NFC
llvm-svn: 253857
2015-11-23 07:19:10 +00:00
Craig Topper d2177de61a [TableGen] Use empty() instead of checking if size of vector is greater than or equal to 1.
llvm-svn: 253856
2015-11-23 07:19:08 +00:00
Craig Topper 2f70a7ef57 Revert a portion of r253836 that seems to have broke a couple bots.
llvm-svn: 253838
2015-11-22 22:43:40 +00:00
Craig Topper 306cb12286 [TableGen] Use range-based for loops. NFC
llvm-svn: 253836
2015-11-22 20:46:24 +00:00
Craig Topper 43c414f31b [TableGen] Use std::fill instead of a manually coded loop. NFC
llvm-svn: 253835
2015-11-22 20:46:22 +00:00
David Blaikie fda69dd736 Further simplify from r253832 with some unique_ptr and coalescing conditions
llvm-svn: 253834
2015-11-22 20:11:21 +00:00
David Blaikie b8fc0186c7 Further simplify from r253832, removing unnecessary intermediate lambdas
llvm-svn: 253833
2015-11-22 20:02:58 +00:00
Craig Topper cbdc27eb74 [TableGen] Use std::any_of and std::find instead of manual loops. NFC
llvm-svn: 253832
2015-11-22 19:27:02 +00:00
Simon Pilgrim 76cbfd48de [Utils] Updated shuffle fuzz script to generate more modern (valid) IR.
llvm-svn: 253821
2015-11-22 16:04:32 +00:00
Krzysztof Parzyszek 6753f33388 Avoid dependency between TableGen and CodeGen
Duplicate a few common definitions between DFAPacketizer.cpp and
DFAPacketizerEmitter.cpp to avoid including files from CodeGen
in TableGen.

llvm-svn: 253820
2015-11-22 15:20:19 +00:00
Krzysztof Parzyszek dd1352499c Now fix errors in NDEBUG build.
Hope this won't break any hardware next.

llvm-svn: 253799
2015-11-21 22:46:52 +00:00
Krzysztof Parzyszek 8dd552db29 Fix warnings in NDEBUG build
llvm-svn: 253798
2015-11-21 22:19:50 +00:00
Krzysztof Parzyszek b46557292c Hexagon V60/HVX DFA scheduler support
Extended DFA tablegen to:
  - added "-debug-only dfa-emitter" support to llvm-tblgen

  - defined CVI_PIPE* resources for the V60 vector coprocessor

  - allow specification of multiple required resources
    - supports ANDs of ORs
    - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means:
           (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1)

  - added support for combo resources
    - allows specifying ORs of ANDs
    - e.g. [CVI_XLSHF, CVI_MPY01] means:
           (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1)

  - increased DFA input size from 32-bit to 64-bit
    - allows for a maximum of 4 AND'ed terms of 16 resources

  - supported expressions now include:

    expression     => term [AND term] [AND term] [AND term]
    term           => resource [OR resource]*
    resource       => one_resource | combo_resource
    combo_resource => (one_resource [AND one_resource]*)

Author: Dan Palermo <dpalermo@codeaurora.org>

kparzysz: Verified AMDGPU codegen to be unchanged on all llc
tests, except those dealing with instruction encodings.

Reapply the previous patch, this time without circular dependencies.

llvm-svn: 253793
2015-11-21 20:00:45 +00:00
Krzysztof Parzyszek 4ca21fc1aa Revert r253790: it breaks all builds for some reason.
llvm-svn: 253791
2015-11-21 17:38:33 +00:00
Krzysztof Parzyszek 220a9bc018 Hexagon V60/HVX DFA scheduler support
Extended DFA tablegen to:
  - added "-debug-only dfa-emitter" support to llvm-tblgen

  - defined CVI_PIPE* resources for the V60 vector coprocessor

  - allow specification of multiple required resources
    - supports ANDs of ORs
    - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means:
           (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1)

  - added support for combo resources
    - allows specifying ORs of ANDs
    - e.g. [CVI_XLSHF, CVI_MPY01] means:
           (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1)

  - increased DFA input size from 32-bit to 64-bit
    - allows for a maximum of 4 AND'ed terms of 16 resources

  - supported expressions now include:

    expression     => term [AND term] [AND term] [AND term]
    term           => resource [OR resource]*
    resource       => one_resource | combo_resource
    combo_resource => (one_resource [AND one_resource]*)

Author: Dan Palermo <dpalermo@codeaurora.org>

kparzysz: Verified AMDGPU codegen to be unchanged on all llc
tests, except those dealing with instruction encodings.

llvm-svn: 253790
2015-11-21 17:23:52 +00:00
Dan Liew 26da45c2bb [lit] Fix bug when using Python3 where a failing test would not show
the script when running a ShTest with an external or internal shell.

This bug is caused by use of the ``map`` function in Python 3 which
returns an iterable (rather than a list in Python 2). After the iterable
is exhausted it won't return any more output and consequently when
``_runShTest()`` tries to access the ``script`` which has already been
iterated over it is empty. Converting to a list immediatley after
calling ``map()`` fixes this.

This fixes the ``tests/shtest-format.py`` test when running under
Python3 which was previously failing.

llvm-svn: 253556
2015-11-19 11:35:42 +00:00
Rafael Espindola 55512f9b25 Default SetVector to use a DenseSet.
We use to have an odd difference among MapVector and SetVector. The map
used a DenseMop, but the set used a SmallSet, which in turn uses a
std::set.

I have changed SetVector to use a DenseSet. If you were depending on the
old behaviour you can pass an explicit set type or use SmallSetVector.
The common cases for needing to do it are:

* Optimizing for small sets.
* Sets for types not supported by DenseSet.

llvm-svn: 253439
2015-11-18 06:52:18 +00:00
David Blaikie ff43d69ddf StringRef-ify some Option APIs
Patch by Eugene Kosov!

Differential Revision: http://reviews.llvm.org/D14711

llvm-svn: 253360
2015-11-17 19:00:52 +00:00
Matthias Braun fe9d6f211f Assume lane masks are always precise
Allowing imprecise lane masks in case of more than 32 sub register lanes
lead to some tricky corner cases, and I need another bugfix for another
one. Instead I rather declare lane masks as precise and let tablegen
abort if we do not have enough bits.

This does not affect any in-tree target, even AMDGPU only needs 16 lanes
at the moment. If the 32 lanes turn out to be a problem in the future,
then we can easily change the LaneBitmask typedef to uint64_t.

Differential Revision: http://reviews.llvm.org/D14557

llvm-svn: 253279
2015-11-17 00:50:55 +00:00
Akira Hatanaka bd9fc28444 [MCTargetAsmParser] Move the member varialbes that reference
MCSubtargetInfo in the subclasses into MCTargetAsmParser and define a
member function getSTI.

This is done in preparation for making changes to shrink the size of
MCRelaxableFragment. (see http://reviews.llvm.org/D14346).

llvm-svn: 253124
2015-11-14 05:20:05 +00:00
Matthias Braun 167cbd2167 tablegen: Add a simple heuristic to get better names for pressure sets
Differential Revision: http://reviews.llvm.org/D14597

llvm-svn: 253095
2015-11-13 22:30:27 +00:00