Commit Graph

95704 Commits

Author SHA1 Message Date
Eric Christopher 5f93bb9299 Rename for consistency.
llvm-svn: 190345
2013-09-09 20:03:17 +00:00
Eric Christopher b0e769411d Add the gnu pubnames and pubtypes sections to the mc object file
handling.

llvm-svn: 190344
2013-09-09 20:03:14 +00:00
Eric Christopher add00faa96 Add constant defines for gnu pubnames and gnu pubtypes - they're used
for the gdb index as the names convey.

llvm-svn: 190343
2013-09-09 20:03:11 +00:00
Eric Christopher e5679d8f5b Formatting.
llvm-svn: 190342
2013-09-09 20:03:08 +00:00
Bill Wendling 550c76dbd6 Call generateCompactUnwindEncodings() right before we need to output the frame information.
There are more than one paths to where the frame information is emitted. Place
the call to generateCompactUnwindEncodings() into the method which outputs the
frame information, thus ensuring that the encoding is there for every path. This
involved threading the MCAsmBackend object through to this method.

<rdar://problem/13623355>

llvm-svn: 190335
2013-09-09 19:48:37 +00:00
Manman Ren 116868eadd Debug Info: Use DIScopeRef for DIType::getContext.
In DIBuilder, the context field of a TAG_member is updated to use the
scope reference. Verifier is updated accordingly.
    
DebugInfoFinder now needs to generate a type identifier map to have
access to the actual scope. Same applies for BreakpointPrinter.
    
processModule of DebugInfoFinder is called during initialization phase
of the verifier to make sure the type identifier map is constructed early
enough.
    
We are now able to unique a simple class as demonstrated by the added
testing case.

llvm-svn: 190334
2013-09-09 19:47:11 +00:00
Bob Wilson 6b28b3183e Update CMake file to fix buildbots.
llvm-svn: 190331
2013-09-09 19:25:11 +00:00
Manman Ren 33796c5e98 Debug Info: move DIScope::getContext to DwarfDebug.
DIScope::getContext is a wrapper function that calls the specific getContext
method on each subclass. When we switch DIType::getContext to return DIScopeRef
instead of DIScope, DIScope::getContext can no longer return a DIScope without
a type identifier map.
    
DIScope::getContext is only used by DwarfDebug, so we move it to DwarfDebug
to have easy access to the type identifier map.

llvm-svn: 190330
2013-09-09 19:23:58 +00:00
Bob Wilson e407736a06 Revert patches to add case-range support for PR1255.
The work on this project was left in an unfinished and inconsistent state.
Hopefully someone will eventually get a chance to implement this feature, but
in the meantime, it is better to put things back the way the were.  I have
left support in the bitcode reader to handle the case-range bitcode format,
so that we do not lose bitcode compatibility with the llvm 3.3 release.

This reverts the following commits: 155464, 156374, 156377, 156613, 156704,
156757, 156804 156808, 156985, 157046, 157112, 157183, 157315, 157384, 157575,
157576, 157586, 157612, 157810, 157814, 157815, 157880, 157881, 157882, 157884,
157887, 157901, 158979, 157987, 157989, 158986, 158997, 159076, 159101, 159100,
159200, 159201, 159207, 159527, 159532, 159540, 159583, 159618, 159658, 159659,
159660, 159661, 159703, 159704, 160076, 167356, 172025, 186736

llvm-svn: 190328
2013-09-09 19:14:35 +00:00
Sean Silva 9d1e1a392a [docs] Fix Sphinx warning.
Adornments need to be at least as long as the thing they adorn.

llvm-svn: 190327
2013-09-09 19:13:28 +00:00
Sean Silva 3f93a61125 [docs] Fix some Sphinx toctree warnings.
llvm-svn: 190326
2013-09-09 19:09:00 +00:00
Manman Ren 3eb9dffc89 Debug Info: Move isSubprogramContext from DebugInfo to DwarfDebug.
This helper function needs the type identifier map when we switch
DIType::getContext to return DIScopeRef instead of DIScope.

Since isSubprogramContext is used by DwarfDebug only, We move it to DwarfDebug
to have easy access to the map.

llvm-svn: 190325
2013-09-09 19:05:21 +00:00
Sean Silva 23d2f6989e [docs] Some typographical fixes.
llvm-svn: 190324
2013-09-09 19:05:03 +00:00
Manman Ren 856191b0d1 Debug Info: Rename DITypeRef to DIScopeRef.
A reference to a scope is more general than a reference to a type since
DIType is a subclass of DIScope.

A reference to a type can be either an identifier for the type or
the DIType itself, while a reference to a scope can be either an
identifier for the type (when the scope is indeed a type) or the
DIScope itself. A reference to a type and a reference to a scope
will be resolved in the same way. The only difference is in the
verifier when a field is a reference to a type (i.e. the containing
type field of a DICompositeType) or a field is a reference to a scope
(i.e. the context field of a DIType).

This is to get ready for switching DIType::getContext to return
DIScopeRef instead of DIScope.

Tighten up isTypeRef and isScopeRef to make sure the identifier is not
empty and the MDNode is DIType for TypeRef and DIScope for ScopeRef.

llvm-svn: 190322
2013-09-09 19:03:51 +00:00
Manman Ren 473c198863 Debug Info: Update isScope to make sure DIType is a scope and
TAG_file_type is also a scope.

llvm-svn: 190321
2013-09-09 19:00:55 +00:00
Akira Hatanaka 9cf069f60a [mips] When double precision loads and stores are split into two i32 loads and
stores, make sure the load or store that accesses the higher half does not have
an alignment that is larger than the offset from the original address.

llvm-svn: 190318
2013-09-09 17:59:32 +00:00
Benjamin Kramer d93817ffe0 [stackprotector] Modernize code with IRBuilder
llvm-svn: 190317
2013-09-09 17:38:01 +00:00
Joey Gouly a5153cb025 [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.
IT blocks can only be one instruction lonf, and can only contain a subset of
the 16 instructions.

Patch by Artyom Skrobov!

llvm-svn: 190309
2013-09-09 14:21:49 +00:00
Aaron Ballman 83d81784df A better way to silence the warning in MSVC (replaces r190304).
llvm-svn: 190308
2013-09-09 14:17:30 +00:00
Aaron Ballman c4280dd977 Silencing a warning about control flow reaching the end of a non-void function.
llvm-svn: 190304
2013-09-09 13:22:45 +00:00
Robert Lytton 3d3194bf06 XCore handling of thread local lowering
Fix XCoreLowerThreadLocal trying to initialise globals
which have no initializer.

Add handling of const expressions containing thread local variables.
These need to be replaced with instructions, as the thread ID is
used to access the thread local variable.

llvm-svn: 190300
2013-09-09 10:42:11 +00:00
Robert Lytton 4809ea41e6 XCore target: change to Sched::Source
This sidesteps a bug in PrescheduleNodesWithMultipleUses() which
does not check if callResources will be affected by the transformation.

llvm-svn: 190299
2013-09-09 10:42:05 +00:00
Robert Lytton e453888379 XCore target: fix weak linkage attribute handling
llvm-svn: 190298
2013-09-09 10:41:57 +00:00
Bill Wendling 58e2d3d856 Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.

Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.

<rdar://problem/13623355>

llvm-svn: 190290
2013-09-09 02:37:14 +00:00
Jiangning Liu 2878dc8fe7 Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL

llvm-svn: 190288
2013-09-09 02:20:27 +00:00
Manman Ren 7e9448f728 Debug Info Testing: use null instead of an empty string in context field.
llvm-svn: 190284
2013-09-09 00:12:17 +00:00
Renato Golin d24899bfc2 Cross-compilation doc
llvm-svn: 190282
2013-09-08 20:44:48 +00:00
Sylvestre Ledru 65ebb58524 Bring back the build of libprofile_rt on Sparc. It is now working correctly. See:
https://buildd.debian.org/status/fetch.php?pkg=llvm-toolchain-3.3&arch=sparc&ver=1%3A3.3-9&stamp=1378398308

Thanks to Luca Falavigna for the patch

llvm-svn: 190273
2013-09-08 09:15:09 +00:00
Manman Ren b09878728f Revert r190269 to fix dragonegg failures.
llvm-svn: 190271
2013-09-08 06:02:56 +00:00
Manman Ren 8ddddadb0b Debug Info: use null instead of "i32 0" in DIBuilder.
For context field of subroutine_type and when creating artificial types.

llvm-svn: 190270
2013-09-08 06:00:42 +00:00
Manman Ren 93da987ea4 Debug Info: pass in DIScope instead of DIDescriptor in createMemberType.
Improve readability. No functionality change.

llvm-svn: 190269
2013-09-08 04:07:59 +00:00
Manman Ren f2a88f3622 Debug Info Testing: update context from empty string to null.
Context should be either null or MDNode.

llvm-svn: 190267
2013-09-08 03:11:54 +00:00
Craig Topper adbb9a121f Add neverHasSideEffects=1 on a couple move instructions.
llvm-svn: 190259
2013-09-08 00:50:45 +00:00
Craig Topper 0a63e1da92 Using popcount should check the popcount feature flag not the SSE41 feature flag.
llvm-svn: 190258
2013-09-08 00:47:31 +00:00
Bill Wendling d14f153a7e Run clang-format on these header files. Part of a WIP.
llvm-svn: 190250
2013-09-07 11:55:36 +00:00
Akira Hatanaka 9f9bc4f770 [mips] Fix typos.
llvm-svn: 190236
2013-09-07 01:14:42 +00:00
Akira Hatanaka 6379121694 [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.

llvm-svn: 190235
2013-09-07 00:52:30 +00:00
Akira Hatanaka 92ec3bd50b [mips] Place parentheses around && to silence warning.
llvm-svn: 190234
2013-09-07 00:26:26 +00:00
Richard Smith d9e5ff24e6 Remove verifier check that attribute 'builtin' is only applied to calls to
functions marked 'nobuiltin'. That approach doesn't play well with LTO, and
there's no harm in marking a call as 'builtin' if it was going to be a builtin
regardless.

llvm-svn: 190233
2013-09-07 00:25:48 +00:00
Akira Hatanaka 6a3fe57444 [mips] Add definition of instruction "drotr32" (double rotate right plus 32).
llvm-svn: 190232
2013-09-07 00:18:01 +00:00
Manman Ren c4ae9b3aeb Debug Info: Use identifier to reference DIType in containing type field of
a DISubprogram.
    
Verifier is updated accordingly.

llvm-svn: 190229
2013-09-07 00:04:05 +00:00
Akira Hatanaka 3121353c99 [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
into a 5-bit or 6-bit field.

llvm-svn: 190226
2013-09-07 00:02:02 +00:00
Manman Ren 275520608b Debug Info: pass in VTableHolder as DIType instead of MDNode *.
Remove one cast and improve readability. No functionality change.

llvm-svn: 190225
2013-09-06 23:54:23 +00:00
Akira Hatanaka 79e38cde37 [mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".
llvm-svn: 190224
2013-09-06 23:52:46 +00:00
Akira Hatanaka 50eebac68b [mips] Delete unused classes and defs.
llvm-svn: 190221
2013-09-06 23:42:58 +00:00
Akira Hatanaka 2c544d8ed5 [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
equivalent to "beq $zero, $zero, offset".

llvm-svn: 190220
2013-09-06 23:40:15 +00:00
Akira Hatanaka dffc542123 [mips] Set instruction itineraries of loads, stores and conditional moves.
llvm-svn: 190219
2013-09-06 23:28:24 +00:00
Manman Ren d8c68b1852 TBAA: add isTBAAVtableAccess to MDNode so clients can call the function
instead of having its own implementation.

The implementation of isTBAAVtableAccess is in TypeBasedAliasAnalysis.cpp
since it is related to the format of TBAA metadata.

The path for struct-path tbaa will be exercised by
test/Instrumentation/ThreadSanitizer/read_from_global.ll, vptr_read.ll, and
vptr_update.ll when struct-path tbaa is on by default.

llvm-svn: 190216
2013-09-06 22:47:05 +00:00
Manman Ren deeafd8a58 Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.
Field 2 of DIType (Context), field 9 of DIDerivedType (TypeDerivedFrom),
field 12 of DICompositeType (ContainingType), fields 2, 7, 12 of DISubprogram
(Context, Type, ContainingType).

llvm-svn: 190205
2013-09-06 21:03:58 +00:00
Aaron Watry 372cecf642 R600: Add support for LDS atomic subtract
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 190200
2013-09-06 20:17:42 +00:00
Manman Ren d8f798ea97 Debug Info: Use identifier to reference DIType in containing type field of
a DICompositeType.
    
Verifier is updated accordingly.

llvm-svn: 190190
2013-09-06 18:46:00 +00:00
Manman Ren 277206fa28 Debug Info: Move a helper function getTypeIdentifier from DIBuilder to be part
of DIType.
    
Implement DIType::generateRef to return a type reference. This function will be
used in setContaintingType and in DIBuilder to generete the type reference.
    
No functionality change.

llvm-svn: 190188
2013-09-06 18:27:00 +00:00
Manman Ren 4c12bf5ac7 Debug Info Testing: Updated to use null instead of "i32 0" for containing-type
field of DICompositeType.

This will help the follow-on patch of using DITypeRef for containing-type field.

llvm-svn: 190187
2013-09-06 18:13:59 +00:00
Adrian Prantl e8010fa54c debuginfo-tests: Add support for an lldb wrapper script
to be used on darwin in lieu of gdb.

llvm-svn: 190186
2013-09-06 18:12:01 +00:00
Andrew Trick b248b4a1de mi-sched: cleanup register pressure update, remove a FIXME.
llvm-svn: 190181
2013-09-06 17:32:47 +00:00
Andrew Trick c573cd905a mi-sched: improve regpressure tracing.
llvm-svn: 190180
2013-09-06 17:32:44 +00:00
Andrew Trick 7609b7d1b5 mi-sched: print tree size in -view-misched-dags
llvm-svn: 190179
2013-09-06 17:32:42 +00:00
Andrew Trick ffdbefb90c mi-sched: register pressure update tracing.
llvm-svn: 190178
2013-09-06 17:32:39 +00:00
Andrew Trick ddffae9027 mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.
The latency based scheduling could induce spills in some cases.

llvm-svn: 190177
2013-09-06 17:32:36 +00:00
Andrew Trick 75e411cc8e Added MachineSchedPolicy.
Allow subtargets to customize the generic scheduling strategy.
This is convenient for targets that don't need to add new heuristics
by specializing the strategy.

llvm-svn: 190176
2013-09-06 17:32:34 +00:00
Hans Wennborg 8df6417683 msbuild integration: provide separate files for VS2010 and VS2012
The previous msbuild integration only worked if VS2010 was installed. This patch
renames the current integration to LLVM-vs2010 and adds LLVM-vs2012.

Differential Revision: http://llvm-reviews.chandlerc.com/D1614

llvm-svn: 190173
2013-09-06 17:05:46 +00:00
Matthias Braun 305ef7f5b0 avoid unnecessary direct access to LiveInterval::ranges
llvm-svn: 190170
2013-09-06 16:44:32 +00:00
Matthias Braun 90e0d3c03a remove unused argument from LiveRanges::join()
llvm-svn: 190169
2013-09-06 16:44:29 +00:00
Matthias Braun c0ad7bfa62 remove pointless assert
The if above it ensures the property anyway.

llvm-svn: 190168
2013-09-06 16:44:27 +00:00
Matthias Braun b348d9703c fix comment
There's no 'B3' in the example.

llvm-svn: 190167
2013-09-06 16:44:25 +00:00
Matthias Braun 9804f81fde fix typo in comment
llvm-svn: 190165
2013-09-06 16:19:22 +00:00
Daniel Sanders af7f805b96 [mips][msa] Indentation
llvm-svn: 190156
2013-09-06 13:25:06 +00:00
Daniel Sanders 636f72fc08 [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.

llvm-svn: 190155
2013-09-06 13:15:05 +00:00
Vladimir Medic b936da159e This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
llvm-svn: 190154
2013-09-06 13:08:00 +00:00
Daniel Sanders 563e5eabe5 [mips][msa] Made the operand register sets optional for the VEC formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190153
2013-09-06 13:01:47 +00:00
Vladimir Medic 457ba56b05 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
llvm-svn: 190152
2013-09-06 12:53:21 +00:00
Daniel Sanders 41fb2c0d0e [mips][msa] Made the operand register sets optional for the ELM_INSVE formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190151
2013-09-06 12:50:52 +00:00
Daniel Sanders fa1b0fa77e [mips][msa] Made the operand register sets optional for the 3RF_4RF format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190150
2013-09-06 12:44:13 +00:00
Vladimir Medic e0fbb44a48 This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
llvm-svn: 190148
2013-09-06 12:41:17 +00:00
Tim Northover 950fcc0577 SelectionDAG: create correct BooleanContent constants
Occasionally DAGCombiner can spot that a SETCC operation is completely
redundant and reduce it to "all true" or "all false". If this happens to a
vector, the value produced has to take account of what a normal comparison
would have produced, which may be an all-1s bitmask.

The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in
TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when
triggered so there are no tests. However, I believe it's still clearly the
right change and may save someone else some hassle if it suddenly becomes
reachable. So I'm doing it anyway.

llvm-svn: 190147
2013-09-06 12:38:12 +00:00
Daniel Sanders d719f5281c [mips][msa] Made the operand register sets optional for the 3RF formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190146
2013-09-06 12:32:57 +00:00
Daniel Sanders b2b7c0a044 [mips][msa] Made the operand register sets optional for the 3R_4R format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190145
2013-09-06 12:30:43 +00:00
Vladimir Medic dde3d582a2 This patch adds support for microMIPS disassembler and disassembler make check tests.
llvm-svn: 190144
2013-09-06 12:30:36 +00:00
Daniel Sanders 2322f5d090 [mips][msa] Made the operand register sets optional for the 2RF format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190143
2013-09-06 12:28:13 +00:00
Daniel Sanders 9148218cbe [mips][msa] Made the operand register sets optional for the I8 format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190142
2013-09-06 12:25:47 +00:00
Daniel Sanders 92c40a5796 [mips][msa] Made the operand register sets optional for the I5 and SI5 formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190141
2013-09-06 12:23:19 +00:00
Daniel Sanders 13d5e2f376 [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190140
2013-09-06 12:10:24 +00:00
Richard Sandiford 5bc670bb55 [SystemZ] Tweak integer comparison code
The architecture has many comparison instructions, including some that
extend one of the operands.  The signed comparison instructions use sign
extensions and the unsigned comparison instructions use zero extensions.
In cases where we had a free choice between signed or unsigned comparisons,
we were trying to decide at lowering time which would best fit the available
instructions, taking things like extension type into account.  The code
to do that was getting increasingly hairy and was also making some bad
decisions.  E.g. when comparing the result of two LLCs, it is better to use
CR rather than CLR, since CR can be fused with a branch while CLR can't.

This patch removes the lowering code and instead adds an operand to
integer comparisons to say whether signed comparison is required,
whether unsigned comparison is required, or whether either is OK.
We can then leave the choice of instruction up to the normal isel code.

llvm-svn: 190138
2013-09-06 11:51:39 +00:00
Daniel Sanders 63b97d5ae5 [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size
No functional change

llvm-svn: 190134
2013-09-06 11:01:38 +00:00
Daniel Sanders 02a3007608 [mips][msa] Made the operand register sets optional for the 3R format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190133
2013-09-06 10:59:24 +00:00
Daniel Sanders db12ab7b7c [mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment.
No functional change

llvm-svn: 190131
2013-09-06 10:55:15 +00:00
Richard Sandiford 4943bc393a [SystemZ] Use XC for a memset of 0
llvm-svn: 190130
2013-09-06 10:25:07 +00:00
Matt Arsenault 8227b9f69c Use type helper functions.
llvm-svn: 190113
2013-09-06 00:37:24 +00:00
Matt Arsenault 37d42ecaff Teach CodeGenPrepare about address spaces
llvm-svn: 190112
2013-09-06 00:18:43 +00:00
Tom Stellard 8bc633ac09 R600: Coding style
llvm-svn: 190110
2013-09-05 23:55:13 +00:00
Juergen Ributzka 53d0b492f5 [X86] Perform VSELECT DAG combines also before DAG type legalization.
If the DAG already has only legal types, then the second round of DAG combines
is skipped. In this case VSELECT+SETCC patterns that match a more efficient
instruction (e.g. min/max) are never recognized.

This fix allows VSELECT+SETCC combines if the types are already legal before DAG
type legalization.

Reviewer: Nadav
llvm-svn: 190105
2013-09-05 23:02:56 +00:00
Kevin Enderby 09cdb4385f Fixed a crash in the integrated assembler for Mach-O when a symbol difference
expression uses an assembler temporary symbol from an assignment.  In this case
the symbol does not have a fragment so the use of getFragment() would be NULL
and caused a crash. In the case of an assembler temporary symbol we want to use
the AliasedSymbol (if any) which will create a local relocation entry, but if
it is not an assembler temporary symbol then let it use that symbol with an
external relocation entry.

rdar://9356266

llvm-svn: 190096
2013-09-05 20:25:06 +00:00
Matt Arsenault e6db76071c Consistently use dbgs() in debug printing
llvm-svn: 190093
2013-09-05 19:48:28 +00:00
Manman Ren 8e3275c22b Trying to un-break the bots.
llvm-svn: 190092
2013-09-05 19:44:52 +00:00
Matt Arsenault 6f24379974 R600: Fix i64 to i32 trunc on SI
llvm-svn: 190091
2013-09-05 19:41:10 +00:00
Rafael Espindola d21ac19bda Remove unused argument.
llvm-svn: 190090
2013-09-05 19:15:21 +00:00
Yunzhong Gao 8c0f5067cc Improve handling of .file, .include and .incbin directives to
allow escaped octal character sequences.

The patch was discussed in Phabricator. See:
http://llvm-reviews.chandlerc.com/D1289

llvm-svn: 190089
2013-09-05 19:14:26 +00:00
Manman Ren 60352032bf Debug Info: Use identifier to reference DIType in base type field of
ptr_to_member.

We introduce a new class DITypeRef that represents a reference to a DIType.
It wraps around a Value*, which can be either an identifier in MDString
or an actual MDNode. The class has a helper function "resolve" that
finds the actual MDNode for a given DITypeRef.

We specialize getFieldAs to return a field that is a reference to a
DIType. To correctly access the base type field of ptr_to_member,
getClassType now calls getFieldAs<DITypeRef> to return a DITypeRef.

Also add a typedef for DITypeIdentifierMap and a helper
generateDITypeIdentifierMap in DebugInfo.h. In DwarfDebug.cpp, we keep
a DITypeIdentifierMap and call generateDITypeIdentifierMap to actually
populate the map.

Verifier is updated accordingly.

llvm-svn: 190081
2013-09-05 18:48:31 +00:00
Tom Stellard 13c68ef88b R600: Add support for local memory atomic add
llvm-svn: 190080
2013-09-05 18:38:09 +00:00
Tom Stellard 53f2f90eb4 R600: Expand SELECT nodes rather than custom lowering them
llvm-svn: 190079
2013-09-05 18:38:03 +00:00
Tom Stellard de60e25278 R600: Fix incorrect LDS size calculation
GlobalAdderss nodes that appeared in more than one basic block were
being counted twice.

llvm-svn: 190078
2013-09-05 18:37:57 +00:00
Tom Stellard d50bb3c8d4 R600/SI: Don't emit S_WQM_B64 instruction for compute shaders
llvm-svn: 190077
2013-09-05 18:37:52 +00:00
Tom Stellard 624741fded R600: Fix segfault in R600TextureIntrinsicReplacer
This pass was segfaulting when it ran into a non-intrinsic function
call.  Function calls are not supported, so now instead of segfaulting,
we will get an assertion failure with a nice error message.

I'm not sure how to test this using lit.

llvm-svn: 190076
2013-09-05 18:37:45 +00:00
Eric Christopher cf7289f6d9 Move accelerator table defines and constants to Dwarf.h since
we're proposing it for DWARF5.

No functional change intended.

llvm-svn: 190074
2013-09-05 18:20:16 +00:00
Eric Christopher 05a102a303 Rename enums to match convention and remove superfluous "dwarf" in names.
llvm-svn: 190067
2013-09-05 16:55:35 +00:00
Eric Christopher b4e2cc49ef Reformat.
llvm-svn: 190064
2013-09-05 16:46:43 +00:00
Joey Gouly c209d6aa3e [ARMv8] Add some missing tests for DSB/DMB.
llvm-svn: 190060
2013-09-05 16:05:45 +00:00
Joey Gouly 926d3f5809 [ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.

llvm-svn: 190055
2013-09-05 15:35:24 +00:00
Richard Barton 8d519fe015 Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.

The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.

HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.

Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.

llvm-svn: 190053
2013-09-05 14:14:19 +00:00
Tilmann Scheller 841a9ccfed Reverting 190043 for now.
Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code.
Test case doesn't trigger the added functionality.

llvm-svn: 190047
2013-09-05 11:59:43 +00:00
Tilmann Scheller a1787a5835 ARM: Add GPR register class excluding LR for use with the ADR instruction.
This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target.

Patch by Daniel Stewart!
   

llvm-svn: 190043
2013-09-05 11:10:31 +00:00
Richard Sandiford 178273a174 [SystemZ] Add NC, OC and XC
For now these are just used to handle scalar ANDs, ORs and XORs in which
all operands are memory.

llvm-svn: 190041
2013-09-05 10:36:45 +00:00
Nick Lewycky 2c88067a46 Declare missing dependency on AliasAnalysis. Patch by Liu Xin!
llvm-svn: 190035
2013-09-05 08:19:58 +00:00
Nick Lewycky 62ae892bad Fix typos in assert message.
llvm-svn: 190034
2013-09-05 06:53:59 +00:00
Venkatraman Govindaraju 55ecb10e99 [Sparc] Correctly handle call to functions with ReturnsTwice attribute.
In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores
the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7)
using the stored %fp and register windows. However, this does not guarantee that the longjmp
will restore the registers, as they were when the setjmp was called. This is because these
registers may be clobbered after returning from setjmp, but before calling longjmp.

This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask.  

llvm-svn: 190033
2013-09-05 05:32:16 +00:00
Reid Kleckner 6ad0686da8 msbuild: Add clang's compiler-rt libs to the LibraryPath
This allows linking libraries like the asan RTL.

llvm-svn: 190028
2013-09-05 02:09:34 +00:00
Bill Wendling 3af441f1af Fix comments to reflect reality.
llvm-svn: 190021
2013-09-05 00:54:52 +00:00
Eric Christopher 4202633ea6 Formatting.
llvm-svn: 190019
2013-09-05 00:22:35 +00:00
Eric Christopher 5c30024fd4 Clean up some whitespace and comment formatting.
llvm-svn: 190015
2013-09-05 00:01:17 +00:00
Andrew Trick ed20075d19 mi-sched: Force bottom up scheduling for generic targets.
Fast register pressure tracking currently only takes effect during
bottom up scheduling. Forcing this is a bit faster and simpler for
targets that don't have many scheduling constraints and don't need
top-down scheduling.

llvm-svn: 190014
2013-09-04 23:54:00 +00:00
Nick Kledzik fe6813f0e1 Add names for mach-o permissions bits and use the symbol names in place of magic numbers
llvm-svn: 190013
2013-09-04 23:53:44 +00:00
Eric Christopher 146d6b3f35 Move default dwarf version enum into the llvm dwarf constants rather
than the spec dwarf constants.

llvm-svn: 190011
2013-09-04 23:38:29 +00:00
Nick Kledzik 1df64b081b fix typo in enum name
llvm-svn: 190009
2013-09-04 23:27:21 +00:00
Bill Wendling b1e21831b7 Add missing header line.
llvm-svn: 190004
2013-09-04 22:35:41 +00:00
Bill Wendling 10543925bd Use ArrayRef instead of explicit container.
llvm-svn: 190003
2013-09-04 22:35:29 +00:00
Eric Christopher e31e072c33 Remove hack ensuring that darwin didn't produce dwarf > 3 for modules
without a limiting factor.

Update all testcases accordingly.

llvm-svn: 190002
2013-09-04 22:21:24 +00:00
Eric Christopher c9f1e785d5 Revert "Revert r189902 as the workaround shouldn't be necessary anymore."
Needs testcase updates.

llvm-svn: 190000
2013-09-04 21:36:52 +00:00
Eric Christopher b72ef638f4 Revert r189902 as the workaround shouldn't be necessary anymore.
llvm-svn: 189999
2013-09-04 21:26:56 +00:00
Eric Christopher 888af62c1b Expand and rewrite comment.
llvm-svn: 189998
2013-09-04 21:23:23 +00:00
Andrew Trick b05db8e0b9 comment typo
llvm-svn: 189997
2013-09-04 21:12:05 +00:00
Andrew Trick 2a749ee0b9 Remove dead subtree limit code.
llvm-svn: 189995
2013-09-04 21:00:20 +00:00
Andrew Trick 856ecd9ab3 -view-misched-dags, better pruning.
llvm-svn: 189994
2013-09-04 21:00:18 +00:00
Andrew Trick ef54c59490 mi-sched: DEBUG cleanup, call tracePick for unidirectional scheduling.
llvm-svn: 189993
2013-09-04 21:00:16 +00:00
Andrew Trick 1ab16d9ecf 80 columns
llvm-svn: 189992
2013-09-04 21:00:13 +00:00
Andrew Trick 66c3dfbf8c mi-sched: Suppress register pressure tracking when the scheduling window is too small.
If the instruction window is < NumRegs/2, pressure tracking is not
likely to be effective. The scheduler has to process a very large
number of tiny blocks. We want this to be fast.

llvm-svn: 189991
2013-09-04 21:00:11 +00:00
Andrew Trick a6e877707f mi-sched: Load clustering is a bit to expensive to enable unconditionally.
llvm-svn: 189990
2013-09-04 21:00:08 +00:00
Andrew Trick 8c699c93b2 mi-sched: Reuse an invalid HazardRecognizer to save compile time.
llvm-svn: 189989
2013-09-04 21:00:05 +00:00
Andrew Trick 310190e21f mi-sched: bypass heuristic checks when regpressure tracking is disabled.
llvm-svn: 189988
2013-09-04 21:00:02 +00:00
Andrew Trick b6e74712b6 Added -misched-regpressure option.
Register pressure tracking is half the complexity of the
scheduler. It's useful to be able to turn it off for compile time and
performance comparisons.

llvm-svn: 189987
2013-09-04 20:59:59 +00:00
Arnold Schwaighofer eefa7f5d15 Change swift/vldm test case to be less dependent on allocation order
'Force' values in registers using the calling convention. Now, we only depend on
the calling convention and that the allocator performs copy coalescing.

llvm-svn: 189985
2013-09-04 20:51:06 +00:00
Rafael Espindola b7c0b4a327 Rename some variables to match the style guide.
I am about to patch this code, and this makes the diff far more readable.

llvm-svn: 189982
2013-09-04 20:08:46 +00:00
Vincent Lejeune 744efa4dca R600: Use shared op optimization when checking cycle compatibility
llvm-svn: 189981
2013-09-04 19:53:54 +00:00
Vincent Lejeune 7e2c83256b R600: Non vector only instruction can be scheduled on trans unit
llvm-svn: 189980
2013-09-04 19:53:46 +00:00
Vincent Lejeune 4d5c5e53d0 R600: Use SchedModel enum for is{Trans,Vector}Only functions
llvm-svn: 189979
2013-09-04 19:53:30 +00:00
Vincent Lejeune 0c00503ca7 R600: Remove fmul.v4f32.ll test which is redundant with fmul.ll
llvm-svn: 189978
2013-09-04 19:53:22 +00:00
Eric Christopher 9adc55faa7 Unify and clean up.
llvm-svn: 189977
2013-09-04 19:53:21 +00:00
Rafael Espindola 75a3ccd177 Merge these 2 tests in a single file.
llvm-svn: 189975
2013-09-04 19:19:32 +00:00
Jim Grosbach 13654dd303 ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.
These instructions, such as vmul.f32, require the second source operand to
be in D0-D15 rather than the full D0-D31. When optimizing, make sure to
account for that by constraining the register class of a replacement virtual
register to be compatible with the virtual register(s) it's replacing.

I've been unsuccessful in creating a non-fragile regression test. This issue
was detected by the LLVM nightly test suite running on an A15 (Bullet).

PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093
llvm-svn: 189972
2013-09-04 19:08:44 +00:00
Rafael Espindola b832d49822 Small simplification given that insert of an empty range is a nop.
llvm-svn: 189971
2013-09-04 18:53:21 +00:00
Bill Wendling d07097b598 Remove 'param' label from comments. They aren't used properly here.
llvm-svn: 189970
2013-09-04 18:48:12 +00:00