llvm-project

Commit Graph

Author	SHA1	Message	Date
NAKAMURA Takumi	74ed5a8c15	llvm/test/MC/Mips/macro-ld-sd.s: Sweep a spurious character \xA0 in the test file. It might crash FileCheck. llvm-svn: 284587	2016-10-19 13:41:12 +00:00
Simon Dardis	aff4d141b9	[mips] Macro expansion for ld, sd for O32 ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads or stores using the specified source or destination register and the next register. This patch does not add support for the cases where the offset is greater than a 16 bit signed immediate as that would lead to a wrong/misleading error message as the assembler would report "instruction requires a CPU feature not currently enabled" for ld & sd for MIPS64 when their offset is not a signed 16 bit number. This fixes PR/29159. Thanks to Sean Bruno for reporting this issue! Reviewers: vkalintiris, seanbruno, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24556 llvm-svn: 284481	2016-10-18 14:28:00 +00:00

Author

SHA1

Message

Date

NAKAMURA Takumi

74ed5a8c15

llvm/test/MC/Mips/macro-ld-sd.s: Sweep a spurious character \xA0 in the test file.

It might crash FileCheck.

llvm-svn: 284587

2016-10-19 13:41:12 +00:00

Simon Dardis

aff4d141b9

[mips] Macro expansion for ld, sd for O32

ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads
or stores using the specified source or destination register and the next
register.

This patch does not add support for the cases where the offset is greater than
a 16 bit signed immediate as that would lead to a wrong/misleading error
message as the assembler would report "instruction requires a CPU feature
not currently enabled" for ld & sd for MIPS64 when their offset is not a signed
16 bit number.

This fixes PR/29159.

Thanks to Sean Bruno for reporting this issue!

Reviewers: vkalintiris, seanbruno, zoran.jovanovic

Differential Review: https://reviews.llvm.org/D24556

llvm-svn: 284481

2016-10-18 14:28:00 +00:00

2 Commits