llvm-project

Commit Graph

Author	SHA1	Message	Date
Simon Pilgrim	0c0336e003	[X86] Split WriteADC/WriteADCRMW scheduler classes For integer ALU instructions taking eflags as an input (ADC/SBB/ADCX/ADOX) llvm-svn: 332605	2018-05-17 12:43:42 +00:00
Simon Pilgrim	8a83f16ccd	[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388	2018-04-06 11:00:51 +00:00
Simon Pilgrim	14318c5b31	[X86] Move ADX schedule tests out of schedule-x86_64.ll llvm-svn: 320637	2017-12-13 21:49:09 +00:00

Author

SHA1

Message

Date

Simon Pilgrim

0c0336e003

[X86] Split WriteADC/WriteADCRMW scheduler classes

For integer ALU instructions taking eflags as an input (ADC/SBB/ADCX/ADOX)

llvm-svn: 332605

2018-05-17 12:43:42 +00:00

Simon Pilgrim

8a83f16ccd

[X86][SandyBridge] SBWriteResPair +5cy Memory Folds

As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions.

I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent.

As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests...

Differential Revision: https://reviews.llvm.org/D44654

llvm-svn: 329388

2018-04-06 11:00:51 +00:00

Simon Pilgrim

14318c5b31

[X86] Move ADX schedule tests out of schedule-x86_64.ll

llvm-svn: 320637

2017-12-13 21:49:09 +00:00

3 Commits