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14943 Commits

Author SHA1 Message Date
Bob Wilson 411dfad981 Allow more cases of undef shuffle indices and add tests for them. 
llvm-svn: 111226
 2010-08-17 05:54:34 +00:00
Eric Christopher 09f757d4bc Copy over some overridden MI wrappers for ARM fast-isel. This is where 
we're adding predicates and optional defs to the MachineInstrs.

llvm-svn: 111222
 2010-08-17 01:25:29 +00:00
Eric Christopher 663f49900d Make arm fast-isel possible to enable via command line. 
llvm-svn: 111219
 2010-08-17 00:46:57 +00:00
Bob Wilson c350e7a509 Ignore undef shuffle indices when checking for a VTRN shuffle. Radar 8290937. 
llvm-svn: 111208
 2010-08-16 23:37:17 +00:00
Bob Wilson 804f6159f1 Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee 
that the high halfword is zero.  The shift need not be exactly 16 bits.

llvm-svn: 111196
 2010-08-16 22:26:55 +00:00
Eli Friedman 2444da0652 Comment out some broken/unused/useless instructions which mess up disassembly. 
llvm-svn: 111185
 2010-08-16 21:18:51 +00:00
Eli Friedman 51ec745509 Don't attempt to SimplifyShortMoveForm in 64-bit mode. 
llvm-svn: 111182
 2010-08-16 21:03:32 +00:00
Matt Fleming f751d856f0 Hookup ELF support for X86. 
llvm-svn: 111173
 2010-08-16 18:36:14 +00:00
Bob Wilson 481d7a9ab4 Rename sat_shift operand to shift_imm, in preparation for using it for other 
instructions besides saturate instructions.  No functional changes.

llvm-svn: 111168
 2010-08-16 18:27:34 +00:00
Jakob Stoklund Olesen 2cd00737c0 Partially revert r111155. It looks like MSVC is calling an operator<() that 
clang says is unused.

llvm-svn: 111167
 2010-08-16 18:24:54 +00:00
Jakob Stoklund Olesen b7f872197a Remove unused functions. 
llvm-svn: 111155
 2010-08-16 17:18:18 +00:00
Bob Wilson 8303fbbcf9 Remove unused code. 
llvm-svn: 111154
 2010-08-16 17:06:03 +00:00
Argyrios Kyrtzidis d0fcc9a818 Revert r111082. No warnings for this common pattern. 
llvm-svn: 111102
 2010-08-15 10:27:23 +00:00
Eric Christopher 54194bd127 Rework how the non-sse2 memory barrier is lowered so that the 
encoding is correct for the built-in assembler.

Based on a patch from Chris.

llvm-svn: 111083
 2010-08-14 21:51:50 +00:00
Argyrios Kyrtzidis 7c09ddf0ae Add ATTRIBUTE_UNUSED to methods that are not supposed to be used. 
llvm-svn: 111082
 2010-08-14 21:35:10 +00:00
Chris Lattner 2f6c3434ac improve indentation 
llvm-svn: 111073
 2010-08-14 17:26:09 +00:00
Bob Wilson bffc757df7 T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern. 
llvm-svn: 111068
 2010-08-14 03:18:29 +00:00
Bob Wilson 4577f37d49 Add a Thumb2 t2RSBrr instruction for disassembly only. 
This fixes another part of PR7792.

llvm-svn: 111057
 2010-08-13 23:24:25 +00:00
Bob Wilson 3c9ed76ba5 Temporarily disable tail calls on ARM to work around some linker problems. 
llvm-svn: 111050
 2010-08-13 22:43:33 +00:00
Bob Wilson 15b3c3d0ac Move the Thumb2 SSAT and USAT optional shift operator out of the 
instruction opcode.  This fixes part of PR7792.

llvm-svn: 111047
 2010-08-13 21:48:10 +00:00
Bruno Cardoso Lopes 160be2936b Add comments to some pattern fragments in x86 
llvm-svn: 111041
 2010-08-13 20:39:01 +00:00
Bob Wilson d3a828ce68 Refactor the code for disassembling Thumb2 saturate instructions along the 
same lines as the change I made for ARM saturate instructions.

llvm-svn: 111029
 2010-08-13 19:04:21 +00:00
Dale Johannesen 8d3c89e765 Revert 110491. While not wrong, it was based on a 
misanalysis and is undesirable.

llvm-svn: 111028
 2010-08-13 18:43:45 +00:00
Bruno Cardoso Lopes 081861b6b7 Fix comment to reflect code, and remove an unused argument 
llvm-svn: 111022
 2010-08-13 17:50:47 +00:00
Bruno Cardoso Lopes 1187e3f09b Improve comment to make explicit why not to touch this could before JIT goes MC 
llvm-svn: 111021
 2010-08-13 17:44:10 +00:00
Eric Christopher 6e5b67ccc4 Revert last patch and r110954 as I meant to. 
llvm-svn: 111001
 2010-08-13 02:37:50 +00:00
Eric Christopher 5e027fe113 Revert r110954 for now, pseudo instructions can't make it through to the JIT. 
llvm-svn: 111000
 2010-08-13 02:30:00 +00:00
Bruno Cardoso Lopes cc20fe5937 Some small clean-up: use of pseudo instructions 
llvm-svn: 110954
 2010-08-12 20:55:18 +00:00
Johnny Chen 8e8f1c133a Cleaned up the for-disassembly-only entries in the arm instruction table so that 
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951
 2010-08-12 20:46:17 +00:00
Evan Cheng 44a320dafa Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637 
llvm-svn: 110947
 2010-08-12 20:30:05 +00:00
Bruno Cardoso Lopes 7f704b31a9 - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. 
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.

llvm-svn: 110946
 2010-08-12 20:20:53 +00:00
Bruno Cardoso Lopes 7e1a30c0d3 Define AVX 128-bit pattern versions of SET0PS/PD. 
llvm-svn: 110937
 2010-08-12 18:20:59 +00:00
Bruno Cardoso Lopes 1401e040eb Fix comment order 
llvm-svn: 110898
 2010-08-12 02:08:52 +00:00
Bruno Cardoso Lopes 7306c86886 Begin to support some vector operations for AVX 256-bit intructions. The long 
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.

llvm-svn: 110897
 2010-08-12 02:06:36 +00:00
Johnny Chen 74491bb52c The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td 
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894
 2010-08-12 01:40:54 +00:00
Daniel Dunbar 7d7b4d1b0f MC/X86/AsmParser: Give an explicit error message when we reject an instruction 
because it could have an ambiguous suffix.

llvm-svn: 110890
 2010-08-12 00:55:42 +00:00
Daniel Dunbar 2ecc3bb4f7 MC/AsmParser: Push the burdon of emitting diagnostics about unmatched 
instructions onto the target specific parser, which can do a better job.

llvm-svn: 110889
 2010-08-12 00:55:38 +00:00
Daniel Dunbar 167b9d7f30 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl', 
target specific parsers can adapt the TargetAsmParser to this.

llvm-svn: 110888
 2010-08-12 00:55:32 +00:00
Johnny Chen d59c73f998 Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. 
Added two test cases to arm-tests.txt.

llvm-svn: 110880
 2010-08-11 23:35:12 +00:00
Bob Wilson add513112a Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875
 2010-08-11 23:10:46 +00:00
Jakob Stoklund Olesen 9c473e46f3 Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk. 
When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

llvm-svn: 110874
 2010-08-11 23:08:22 +00:00
Dan Gohman a5a25036bb Don't use unsigned char for alignments in TargetData. There aren't 
that many of these things, so the memory savings isn't significant,
and there are now situations where there can be alignments greater
than 128.

llvm-svn: 110836
 2010-08-11 18:15:01 +00:00
Dan Gohman 5531aa4de1 Use ISD::ADD instead of ISD::SUB with a negated constant. This 
avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.

Also, use getCopyFromReg instead of getRegister to read a
physical register's value.

llvm-svn: 110835
 2010-08-11 18:14:00 +00:00
Jim Grosbach 4d5dc3e7e5 cortex m4 has floating point support, but only single precision. 
llvm-svn: 110810
 2010-08-11 15:44:15 +00:00
Bill Wendling 6a98131468 Consider this code snippet: 
float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00

llvm-svn: 110799
 2010-08-11 08:43:16 +00:00
Evan Cheng 5190f09291 Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. 
llvm-svn: 110798
 2010-08-11 07:17:46 +00:00
Evan Cheng 163b624b4e ArchV7M implies HW division instructions. 
llvm-svn: 110797
 2010-08-11 07:00:16 +00:00
Evan Cheng 1c3c0009bd ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON. 
llvm-svn: 110796
 2010-08-11 06:57:53 +00:00
Evan Cheng 40921a4e62 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) 
llvm-svn: 110795
 2010-08-11 06:51:54 +00:00
Daniel Dunbar 188b47b214 MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. 
llvm-svn: 110794
 2010-08-11 06:37:20 +00:00