839a06e9d7
Make ComputeDemandedBits return a deterministic result when computing an AssertZext value.
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In the added testcase the constant 55 was behind an AssertZext of type i1, and ComputeDemandedBits
reported that some of the bits were both known to be one and known to be zero.
Together with Michael Kuperstein <michael.m.kuperstein@intel.com>
llvm-svn: 160305
2012-07-16 18:34:53 +00:00
f2bc464f37
tsan: add platform suffix to Go runtime library
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llvm-svn: 160304
2012-07-16 18:25:43 +00:00
1be1aa84ec
Revert "AMDGPU: Add core backend files for R600/SI codegen v6"
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This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.
llvm-svn: 160303
2012-07-16 18:19:53 +00:00
adf452260f
Revert "include/llvm: Add R600 Intrinsics v6"
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This reverts commit 600f7a90f3eef4c5108179b43e27cfd9e5de7cdc.
llvm-svn: 160302
2012-07-16 18:19:48 +00:00
95bd0be903
Revert "Build script changes for R600/SI Codegen v6"
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This reverts commit e3013202259ed1e006c21817c63cf25d75982721.
llvm-svn: 160301
2012-07-16 18:19:46 +00:00
fc3db614c0
Revert "test/CodeGen/R600: Add some basic tests v6"
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This reverts commit 11d3457afcda7848448dd7f11b2ede6552ffb9ea.
llvm-svn: 160300
2012-07-16 18:19:43 +00:00
151dc338e4
Revert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>"
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This reverts commit 0258a6bdd30802f5cc0e8e57c8e768fde2aef590.
llvm-svn: 160299
2012-07-16 18:19:41 +00:00
1bd3012505
Revert "Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCommonTableGen."
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This reverts commit ebc934ba32ee71abbb8f0f2eb6a0fbaa613ba0d2.
llvm-svn: 160298
2012-07-16 18:19:40 +00:00
781853e11f
Revert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional operator..."
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This reverts commit 29f28bc14ad5a907f5dc849f004fafeec0aab33a.
llvm-svn: 160297
2012-07-16 18:19:38 +00:00
2e007de42d
Revert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn function, instead of assert(0)."
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This reverts commit 4ba4acc1bc2561b944a571edbb6a2dc78e357dfe.
llvm-svn: 160296
2012-07-16 18:19:37 +00:00
f65e78b2fa
Revert "Target/AMDGPU: Fix includes, or msvc build failed."
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This reverts commit fef4aa1b16fcf7a472559abbbcf4c1adc9eb5ca6.
llvm-svn: 160295
2012-07-16 18:19:32 +00:00
99504c577c
make ConstantRange::getSetSize() properly compute the size of wrapped and full sets.
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Make it always return APInts with the same bitwidth for the same ConstantRange bitwidth to simply clients
llvm-svn: 160294
2012-07-16 18:08:12 +00:00
10e8207c9e
With r160248 in place this code is no longer needed.
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llvm-svn: 160293
2012-07-16 17:42:13 +00:00
c4ce5dfe2d
[asan] a bit more refactoring, addressed some of the style comments from chandlerc, partially implemented crash callback merging (under flag)
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llvm-svn: 160290
2012-07-16 17:12:07 +00:00
3abd096370
tsan: treat malloc() as memory access in Go
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llvm-svn: 160289
2012-07-16 16:55:01 +00:00
5bfac97ff9
tsan: use dynamic shadow stack for Go
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llvm-svn: 160288
2012-07-16 16:44:47 +00:00
6c7dbf5858
modern objective-c translator: conditionally include
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<string.h>. // rdar://11847319
llvm-svn: 160287
2012-07-16 16:21:45 +00:00
ed9b0a9114
MSVC's implementation of isalnum will assert on characters > 255, so we need to use an unsigned char to ensure the integer promotion happens properly. This fixes an assert in debug builds with CodeGen\X86\utf8.ll
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llvm-svn: 160286
2012-07-16 16:18:18 +00:00
403845ba75
Relax the complete-type checks that are happening under __invokable<Fp, Args...> to only check Fp, and not Args... . This should be sufficient to give the desired high quality diagnostics under both bind and function. And this allows a test reported by Rich E on cfe-dev to pass. Tracked by <rdar://problem/11880602>.
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llvm-svn: 160285
2012-07-16 16:17:34 +00:00
874dae6119
[asan] refactor instrumentation to allow merging the crash callbacks (not fully implemented yet, no functionality change except the BB order)
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llvm-svn: 160284
2012-07-16 16:15:40 +00:00
dc36d69b6a
tsan: increase number of dead threads for Go
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llvm-svn: 160283
2012-07-16 16:03:16 +00:00
9270eaf1f2
tsan: Go runtime: support goroutine end event
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llvm-svn: 160282
2012-07-16 16:01:08 +00:00
1206a91155
Fixing an MSVC warning -- the compiler did not like the cast added to work around a g++ bug (it would claim to possibly emit incorrect code).
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llvm-svn: 160281
2012-07-16 15:45:33 +00:00
96cc5e5bf9
Target/AMDGPU: Fix includes, or msvc build failed.
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llvm-svn: 160280
2012-07-16 15:43:50 +00:00
dc4261794f
Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn function, instead of assert(0).
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llvm-svn: 160279
2012-07-16 15:43:09 +00:00
5f5fd8e545
Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional operator...
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llvm-svn: 160278
2012-07-16 15:42:35 +00:00
f649043aa5
Doubleword Shift Left Logical Plus 32
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Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63
Here is a description of DSLL:
Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits
Description: GPR[rd] <- GPR[rt] << (sa+32)
The 64-bit doubleword contents of GPR rt are shifted left, inserting
zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.
This patch implements the direct object output of these instructions.
llvm-svn: 160277
2012-07-16 15:14:51 +00:00
bb42a5e2cf
Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCommonTableGen.
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llvm-svn: 160276
2012-07-16 15:09:11 +00:00
3128d26124
Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>
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llvm-svn: 160275
2012-07-16 15:08:47 +00:00
893d3d336a
Fix tests that failed on i686-win32 after r160248:
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1. FileCheck-ize epilogue.ll and allow another asm instruction to restore %rsp.
2. Remove check in widen_arith-3.ll that was hitting instruction in epilogue instead of
vector add.
llvm-svn: 160274
2012-07-16 14:33:36 +00:00
6693fbe3eb
test/CodeGen/R600: Add some basic tests v6
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llvm-svn: 160273
2012-07-16 14:17:19 +00:00
812e652b43
Build script changes for R600/SI Codegen v6
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llvm-svn: 160272
2012-07-16 14:17:16 +00:00
ee1812b94f
include/llvm: Add R600 Intrinsics v6
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llvm-svn: 160271
2012-07-16 14:17:14 +00:00
bcce80fa95
AMDGPU: Add core backend files for R600/SI codegen v6
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llvm-svn: 160270
2012-07-16 14:17:08 +00:00
4273bb05d1
[asan] initialize asan error callbacks in runOnModule instead of doing that on-demand
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llvm-svn: 160269
2012-07-16 14:09:42 +00:00
277f6cf805
Fixing an obvious bug in a test.
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llvm-svn: 160268
2012-07-16 13:31:37 +00:00
5e5e36712b
tsan: fix build
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llvm-svn: 160267
2012-07-16 13:25:47 +00:00
c40c00767c
tsan: port Go runtime to Darwin
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llvm-svn: 160266
2012-07-16 13:02:40 +00:00
f2f82550fd
The new clang-ast-dump tool for selective AST dumping. Moved common command-line tool stuff to CommandLineClangTool
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llvm-svn: 160265
2012-07-16 12:46:48 +00:00
b45e7e9191
Add two more missing parameters in diagnostics.
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llvm-svn: 160264
2012-07-16 12:12:45 +00:00
1c2f27c062
Fix diagnostic adding missing parameter.
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llvm-svn: 160263
2012-07-16 11:51:49 +00:00
d77fbba74a
[Sanitizer] implement straightforward nlogn sorting, as qsort() may call malloc, which leads to deadlock in ASan allocator
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llvm-svn: 160262
2012-07-16 11:27:17 +00:00
25184fe925
Allow cast instructions within scops
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Cast instruction do not have side effects and can consequently be part of a
scop. We special cased them earlier, as they may be problematic within array
subscripts or loop bounds. However, the scalar evolution validator already
checks for them such that there is no need to also check the instructions within
the basic blocks. Checking them is actually overly conservative as the precence
of casts may invalidate a scop, even though scalar evolution is not influenced
by it.
llvm-svn: 160261
2012-07-16 10:57:32 +00:00
4968e45b9f
Fix a bug in the 3-address conversion of LEA when one of the operands is an
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undef virtual register. The problem is that ProcessImplicitDefs removes the
definition of the register and marks all uses as undef. If we lose the undef
marker then we get a register which has no def, is not marked as undef. The
live interval analysis does not collect information for these virtual
registers and we crash in later passes.
Together with Michael Kuperstein <michael.m.kuperstein@intel.com>
llvm-svn: 160260
2012-07-16 10:52:25 +00:00
263efd8f05
tsan: allow to pass CFLAGS to Go runtime build script
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llvm-svn: 160259
2012-07-16 10:36:39 +00:00
2dac24a42b
tsan: add missing test for Go runtime
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llvm-svn: 160258
2012-07-16 10:34:57 +00:00
6b5a4fcc07
Prevent unused-variable warning in optimized builds.
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llvm-svn: 160257
2012-07-16 10:25:15 +00:00
8b540ab337
Revert r160254 temporarily.
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It turns out that ASan relied on the at-the-end block insertion order to
(purely by happenstance) disable some LLVM optimizations, which in turn
start firing when the ordering is made more "normal". These
optimizations in turn merge many of the instrumentation reporting calls
which breaks the return address based error reporting in ASan.
We're looking at several different options for fixing this.
llvm-svn: 160256
2012-07-16 10:01:02 +00:00
7e22282b68
Add refactoring callbacks to make common kinds of refactorings easy.
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llvm-svn: 160255
2012-07-16 09:18:17 +00:00
3dd6c81492
Teach AddressSanitizer to create basic blocks in a more natural order.
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This is particularly useful to the backend code generators which try to
process things in the incoming function order.
Also, cleanup some uses of IRBuilder to be a bit simpler and more clear.
llvm-svn: 160254
2012-07-16 08:58:53 +00:00
Nadav Rotem