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458 Commits

Author SHA1 Message Date
Jim Grosbach ed561fc850 NEON VLD4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148762
 2012-01-24 00:43:17 +00:00
Jim Grosbach 17bacab475 Fix typo. 
llvm-svn: 148757
 2012-01-24 00:12:39 +00:00
Jim Grosbach d3d36d9315 NEON VST3(single element from one lane) assembly parsing. 
llvm-svn: 148755
 2012-01-24 00:07:41 +00:00
Jim Grosbach 1a74724fc9 NEON VST3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148748
 2012-01-23 23:45:44 +00:00
Jim Grosbach ac2af3ffab NEON VLD3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148745
 2012-01-23 23:20:46 +00:00
Jim Grosbach a8b444b08b NEON VLD3 lane-indexed assembly parsing and encoding. 
llvm-svn: 148734
 2012-01-23 21:53:26 +00:00
Jim Grosbach d28ef9ac46 Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
 2012-01-23 19:39:08 +00:00
Anton Korobeynikov 5482b9f535 Add fused multiple+add instructions from VFPv4. 
Patch by Ana Pazos!

llvm-svn: 148658
 2012-01-22 12:07:33 +00:00
Bob Wilson 6c7aaec077 ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651> 
We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

llvm-svn: 148568
 2012-01-20 20:59:56 +00:00
Jim Grosbach 90f5780fc1 VST2 four-register w/ update pseudos for fixed/register update. 
rdar://10724489

llvm-svn: 148560
 2012-01-20 19:16:00 +00:00
Jim Grosbach a9d36fbca7 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
 2012-01-20 18:09:51 +00:00
Jim Grosbach 74ac7d50a1 ARM updating VST2 pseudo-lowering fixed vs. register update. 
rdar://10663487

llvm-svn: 147876
 2012-01-10 21:11:12 +00:00
Jim Grosbach 2b80dad572 ARM NEON mnemonic aliase for vrecpeq. 
llvm-svn: 147109
 2011-12-21 23:52:37 +00:00
Jim Grosbach 260b4b336a ARM NEON optional data type on VSWP instructions. 
llvm-svn: 147103
 2011-12-21 23:09:28 +00:00
Jim Grosbach a50e24fcb3 ARM NEON mnemonic aliases for vzipq and vswpq. 
llvm-svn: 147102
 2011-12-21 23:04:33 +00:00
Jim Grosbach c80a264386 ARM NEON assmebly parsing for VLD2 to all lanes instructions. 
llvm-svn: 147069
 2011-12-21 19:40:55 +00:00
Jim Grosbach c5af54ec89 ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
llvm-svn: 147025
 2011-12-21 00:38:54 +00:00
Jim Grosbach 2c59052984 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
llvm-svn: 146990
 2011-12-20 20:46:29 +00:00
Jim Grosbach 75e2ab5db2 ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
llvm-svn: 146983
 2011-12-20 19:21:26 +00:00
Jim Grosbach 045b6c71a6 ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates. 
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"

rdar://10603913

llvm-svn: 146925
 2011-12-19 23:51:07 +00:00
Jim Grosbach 64f4de29e0 ARM NEON two-operand aliases for VPADD. 
rdar://10602276

llvm-svn: 146895
 2011-12-19 19:51:03 +00:00
Jim Grosbach 9ae4fc035b ARM NEON implied destination aliases for VMAX/VMIN. 
llvm-svn: 146885
 2011-12-19 18:57:38 +00:00
Jim Grosbach cef98cddbe ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

llvm-svn: 146884
 2011-12-19 18:31:43 +00:00
Jim Grosbach a7d2421603 Tidy up. 
llvm-svn: 146882
 2011-12-19 18:11:17 +00:00
Jim Grosbach 4a29971f02 ARM NEON aliases for vmovq.f* 
llvm-svn: 146714
 2011-12-16 00:12:22 +00:00
Jim Grosbach a47294e24d ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
llvm-svn: 146699
 2011-12-15 22:56:33 +00:00
Jim Grosbach 4a5c887370 ARM NEON VTBL/VTBX assembly parsing and encoding. 
llvm-svn: 146691
 2011-12-15 22:27:11 +00:00
Jim Grosbach da51104282 ARM NEON better assembly operand range checking for lane indices of VLD/VST. 
llvm-svn: 146608
 2011-12-14 23:35:06 +00:00
Jim Grosbach a8aa30b620 ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
llvm-svn: 146605
 2011-12-14 23:25:46 +00:00
Jim Grosbach bb18fb4f52 ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

llvm-svn: 146594
 2011-12-14 21:49:24 +00:00
Jim Grosbach 8e987f5e25 Nuke old code. Missed in last commit. 
llvm-svn: 146590
 2011-12-14 21:41:32 +00:00
Jim Grosbach 88ac761aa4 ARM NEON refactor VST2 w/ writeback instructions. 
In addition to improving the representation, this adds support for assembly
parsing of these instructions.

llvm-svn: 146588
 2011-12-14 21:32:11 +00:00
Jim Grosbach b7ec06c5c9 ARM NEON improve factoring a bit. No functional change. 
llvm-svn: 146585
 2011-12-14 20:59:15 +00:00
Jim Grosbach 8d24618975 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

llvm-svn: 146579
 2011-12-14 19:35:22 +00:00
Jim Grosbach 4b0844e191 ARM NEON two-operand aliases for VQDMULH. 
llvm-svn: 146514
 2011-12-13 20:40:37 +00:00
Jim Grosbach 9227f39c53 ARM add more 'gas' compatibility aliases for NEON instructions. 
llvm-svn: 146507
 2011-12-13 20:08:32 +00:00
Jim Grosbach 8be2f6577e ARM add some pre-UAL VFP mnemonics for convenience when porting old code. 
llvm-svn: 146296
 2011-12-09 23:34:09 +00:00
Jim Grosbach ea1b353e67 ARM NEON data type aliases for VBIC(register). 
llvm-svn: 146281
 2011-12-09 21:46:04 +00:00
Jim Grosbach d146a02c79 ARM assembly parsing and encoding for VLD2 with writeback. 
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278
 2011-12-09 21:28:25 +00:00
Jim Grosbach 8a4009dab2 Tidy up. Better base class factoring. 
llvm-svn: 146267
 2011-12-09 19:07:20 +00:00
Jim Grosbach b076e6f3d5 Tidy up. Better base class factoring. 
llvm-svn: 146266
 2011-12-09 18:54:11 +00:00
Jim Grosbach db731be7b8 ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough. 
llvm-svn: 146194
 2011-12-08 22:19:04 +00:00
Jim Grosbach ba7d6ed05d ARM VSHR implied destination operand form aliases. 
llvm-svn: 146192
 2011-12-08 22:06:06 +00:00
Jim Grosbach ab9c8bb45b ARM VSUB implied destination operand form aliases. 
llvm-svn: 146182
 2011-12-08 20:56:26 +00:00
Jim Grosbach 66c9ad7642 ARM VQADD implied destination operand form aliases. 
llvm-svn: 146179
 2011-12-08 20:49:43 +00:00
Jim Grosbach e9ee1092e1 ARM a few more VMUL implied destination operand form aliases. 
llvm-svn: 146177
 2011-12-08 20:42:35 +00:00
Jim Grosbach 00326406d4 ARM NEON two-operand aliases for VSHL(immediate). 
llvm-svn: 146125
 2011-12-08 01:30:04 +00:00
Jim Grosbach f10a635eb4 ARM NEON two-operand aliases for VSHL(register). 
llvm-svn: 146123
 2011-12-08 01:12:35 +00:00
Jim Grosbach 0dd1bc9c79 Fix copy/past-o. 
llvm-svn: 146120
 2011-12-08 01:02:26 +00:00
Jim Grosbach 31a462c02c ARM NEON two-operand aliases for VMUL. 
llvm-svn: 146119
 2011-12-08 00:59:47 +00:00