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9 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes a72a505a80 Added support for fround, fextend and FP_TO_SINT 
llvm-svn: 72483
 2009-05-27 17:23:44 +00:00
Bruno Cardoso Lopes 9b9586a5ae Removed AFGR32 register class 
Handle odd registers allocation in FGR32.

llvm-svn: 67422
 2009-03-21 00:05:07 +00:00
Bruno Cardoso Lopes 2ca70df58b Handle i32->f32 bitconvert results. 
llvm-svn: 54315
 2008-08-04 06:44:31 +00:00
Bruno Cardoso Lopes 2d7ddea240 Added pattern for floating point zero immediate (avoiding a constant pool 
access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.

llvm-svn: 54229
 2008-07-30 19:00:31 +00:00
Bruno Cardoso Lopes e683bbabc7 Added floating point lowering for select. 
llvm-svn: 54167
 2008-07-29 19:05:28 +00:00
Bruno Cardoso Lopes bcaf6e5243 Added floating point lowering for setcc and brcond. 
Fixed COMM asm directive usage.
ConstantPool using custom FourByteConstantSection.

llvm-svn: 54139
 2008-07-28 19:11:24 +00:00
Bruno Cardoso Lopes 7ceec57703 Fixe typos and 80 column size problems 
llvm-svn: 53272
 2008-07-09 04:45:36 +00:00
Bruno Cardoso Lopes 5f18582c2e fixed 32-bit fp_to_sint pattern 
llvm-svn: 53192
 2008-07-07 19:11:24 +00:00
Bruno Cardoso Lopes c9c3f49993 Several changes to Mips backend, experimental fp support being the most 
important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.

llvm-svn: 53146
 2008-07-05 19:05:21 +00:00