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Author SHA1 Message Date
Dan Gohman 26ef7c7ab7 Fix memdep's code for reasoning about dependences between two calls. A Ref 
response from getModRefInfo is not useful here. Instead, check for identical
calls only in the NoModRef case.

Reapply r110270, and strengthen it to compensate for the memdep changes.
When both calls are readonly, there is no dependence between them.

llvm-svn: 110382
 2010-08-05 22:09:15 +00:00
Devang Patel cc3f3b341d Move x86 specific tests into test/CodeGen/X86. 
llvm-svn: 110372
 2010-08-05 20:25:37 +00:00
Bob Wilson 72de307116 Add an ARM RSCrr instruction for disassembly only. 
Partial fix for PR7792.

llvm-svn: 110361
 2010-08-05 18:59:36 +00:00
Bob Wilson adb93e56a3 Add an ARM RSBrr instruction for disassembly only. 
Partial fix for PR7792.

llvm-svn: 110358
 2010-08-05 18:23:43 +00:00
Dan Gohman c53ee449a5 Move x86-specific tests out of test/Transforms/LoopStrengthReduce and 
into test/CodeGen/X86, so that they aren't run when the x86 target is
not enabled.

Fix uglygep.ll to not be x86-specific.

llvm-svn: 110343
 2010-08-05 17:04:15 +00:00
Daniel Dunbar e62e664656 tests: CodeGen/X86/GC tests require X86. 
llvm-svn: 110338
 2010-08-05 15:45:33 +00:00
Daniel Dunbar 57e3f71538 tests: Mark MC/AsmParser tests as requiring x86 for now -- almost all of them 
rely on using a specific x86 triple to test what they want to test.

llvm-svn: 110337
 2010-08-05 15:44:15 +00:00
Rafael Espindola 5bca58a290 check-lit was failing again on F13 64 bits :-( 
llvm-svn: 110311
 2010-08-05 03:35:01 +00:00
Dan Gohman 554b012f67 Revert r110270 for now. It appears to uncover a memdep bug. 
llvm-svn: 110293
 2010-08-05 00:43:10 +00:00
Bob Wilson 97886d59d1 ARM "rrx" shift operands do not have an immediate. PR7790. 
llvm-svn: 110292
 2010-08-05 00:34:42 +00:00
Dan Gohman 109561845b The trouble with testing for "ModRef" and "NoModRef" is that 
one is a suffix of the other, and FileCheck accepts superstrings.
Adjust the output to avoid this problem.

llvm-svn: 110280
 2010-08-04 23:37:55 +00:00
Bill Wendling ca1cb13646 The lower invoke pass needs to have unreachable code elimination run after it 
because it could create such things. This fixes a MingW buildbot test failure.

llvm-svn: 110279
 2010-08-04 23:36:02 +00:00
Dan Gohman bd33dab633 The two-callsite form of AliasAnalysis::getModRefInfo is documented 
to return Ref if the left callsite only reads memory read or written
by the right callsite; fix BasicAliasAnalysis to implement this.

Add AliasAnalysisEvaluator support for testing the two-callsite
form of getModRefInfo.

llvm-svn: 110270
 2010-08-04 22:56:29 +00:00
Eli Friedman 39d0f57cab PR7814: Truncates cannot be ignored for signed comparisons. 
llvm-svn: 110268
 2010-08-04 22:40:58 +00:00
Stuart Hastings 49af1ebf2e Test case for r110250. Radar 8264670. Test case by Fariborz Jahanian! 
llvm-svn: 110254
 2010-08-04 22:05:38 +00:00
Bill Wendling 26feb849a4 Testcase for r110248. 
llvm-svn: 110249
 2010-08-04 21:56:30 +00:00
Devang Patel 5c1f56b78f Test case for combination of r110234 & r110235. 
llvm-svn: 110238
 2010-08-04 18:42:46 +00:00
Dan Gohman 6786a04d0d These tests are no longer stored in *CVS*. 
llvm-svn: 110201
 2010-08-04 15:58:01 +00:00
Stuart Hastings cba0d06b7c call-imm.ll test case regex fix. Patch by Dimitry Andric! 
llvm-svn: 110199
 2010-08-04 15:31:35 +00:00
Kalle Raiskila 8b2f70125f Make SPU backend handle insertelement and 
store for "half vectors"

llvm-svn: 110198
 2010-08-04 13:59:48 +00:00
Bob Wilson 79daf7e0ae Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA 
(absolute difference with accumulate) intrinsics.  Radar 8228576.

llvm-svn: 110170
 2010-08-04 00:12:08 +00:00
Dan Gohman 3619660529 Make instcombine set explicit alignments on load or store 
instructions with alignment 0, so that subsequent passes don't
need to bother checking the TargetData ABI size manually.

llvm-svn: 110128
 2010-08-03 18:20:32 +00:00
Jakob Stoklund Olesen 011ff9bec9 OK, that's it. This test is going away now. But don't worry, I am taking it to a 
nice farm in the country where it can play with other tests. And bunnies.

It is not clear what is being tested, and the revision history shows a bunch of
random changes to the expected instruction count. Clearly, we are just fudging
it to pass whenever it fails.

llvm-svn: 110118
 2010-08-03 17:21:14 +00:00
Peter Collingbourne ddaaf40d24 Add an atomic lowering pass 
llvm-svn: 110113
 2010-08-03 16:19:16 +00:00
Michael J. Spencer 54cfd42c33 MC: Fix symbol fragment offsets in COFF. 
Patch by Cameron Esfahani!

llvm-svn: 110104
 2010-08-03 05:02:46 +00:00
Michael J. Spencer d32764c8a0 Revert "MC: Fix symbol fragment offsets in COFF." 
This reverts commit r110100

Wrong path caps.

llvm-svn: 110103
 2010-08-03 04:53:28 +00:00
Michael J. Spencer cf3d8b4ec4 MC: Fix symbol fragment offsets in COFF. 
Patch by Cameron Esfahani!

llvm-svn: 110100
 2010-08-03 04:43:24 +00:00
Stuart Hastings 460a356bf6 Diabolical hack to make a test compatible with clang. (Thanks to Dale!) Radar 8246180. 
llvm-svn: 110081
 2010-08-02 23:29:03 +00:00
Dan Gohman d8968da2c5 Add a lint check for indirectbr with no successors. 
llvm-svn: 110074
 2010-08-02 23:06:43 +00:00
Stuart Hastings 0e6e8858ff Testcase for r110043. Radar 8246180. 
llvm-svn: 110070
 2010-08-02 22:09:53 +00:00
Kalle Raiskila 77558b7d13 More SPU v2f32 stuff added: insertelement and shuffle. 
llvm-svn: 110038
 2010-08-02 11:22:10 +00:00
Kalle Raiskila 68b3886678 Add preliminary v2f32 support for SPU. Like with v2i32, we just 
duplicate the instructions and operate on half vectors. 

Also reorder code in SPUInstrInfo.td for better coherency.

llvm-svn: 110037
 2010-08-02 10:25:47 +00:00
Owen Anderson 8f306a779b Re-apply the infamous r108614, with a fix pointed out by Dirk Steinke. 
llvm-svn: 110036
 2010-08-02 09:32:13 +00:00
Kalle Raiskila 622f8eb981 Add preliminary v2i32 support for SPU backend. As there are no 
such registers in SPU, this support boils down to "emulating" 
them by duplicating instructions on the general purpose registers. 

This adds the most basic operations on v2i32: passing parameters,
addition, subtraction, multiplication and a few others.

llvm-svn: 110035
 2010-08-02 08:54:39 +00:00
Daniel Dunbar 1465d7cffa Fix comment. 
llvm-svn: 110006
 2010-08-02 01:25:20 +00:00
Daniel Dunbar 5eeae48783 tests: Kill off custom targets which were just there for TestRunner.sh. 
llvm-svn: 110003
 2010-08-02 00:52:44 +00:00
Daniel Dunbar 4b77d23d40 tests: Deprecate TestRunner.sh, and have it just invoke 'llvm-lit' (which will 
need to be in your path). Please move to using 'llvm-lit' if you are still using
TestRunner.sh.

llvm-svn: 110002
 2010-08-02 00:52:41 +00:00
Eli Friedman 7595ce05a2 PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR. 
llvm-svn: 109998
 2010-08-02 00:18:19 +00:00
Daniel Dunbar b1af605e58 tests: Make 'lit' the default test tool. You can still use 'make check-dg' to 
run the tests using DejaGNU, but not for much longer. This is a last call for
DejaGNU supporters, if no one complains soon the DejaGNU support is going to
die.

llvm-svn: 109997
 2010-08-02 00:05:18 +00:00
Eli Friedman 1b2bc1b844 PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually 
improves the generated code in some cases.

llvm-svn: 109985
 2010-08-01 21:13:28 +00:00
Bob Wilson 66161f5eb4 Revert new AVX intrinsic tests. They are breaking buildbots and Bruno is 
away from a computer now.
--- Reverse-merging r109881 into '.':
D    test/CodeGen/X86/avx-intrinsics-x86.ll
D    test/CodeGen/X86/avx-intrinsics-x86_64.ll

llvm-svn: 109959
 2010-07-31 22:36:03 +00:00
Daniel Dunbar 0b636a24c7 Speculatively revert r108614, "Another attempt at getting the clang self-host to 
like my instcombine patch.", in an attempt to fix Clang i386 bootstrap.
 - Also PR7719.

llvm-svn: 109953
 2010-07-31 19:51:11 +00:00
Bob Wilson cd5fc7bef1 Add support for disassembling VMVN (immediate) instructions. PR7747. 
llvm-svn: 109946
 2010-07-31 05:57:44 +00:00
Dale Johannesen cf0287e56d PPC doesn't supported VLA with large alignment. This was 
formerly rejected by the FE, so asserted in the BE; now the FE only
warns, so we treat it as a legitimate fatal error in PPC BE.
This means the test for the feature won't pass, so it's xfail'd.

llvm-svn: 109892
 2010-07-30 21:09:48 +00:00
Bruno Cardoso Lopes 92941fdb26 A *bunch* of tests for AVX intrinsics 
llvm-svn: 109881
 2010-07-30 19:57:56 +00:00
Bob Wilson 964179cb58 Attempt to fix the llvm-gcc-powerpc-darwin9 buildbot. 
llvm-svn: 109876
 2010-07-30 18:52:47 +00:00
Eli Friedman ffe64c06ef Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctly 
check the range of the constant when optimizing a comparison between a
constant and a sign_extend_inreg node.

llvm-svn: 109854
 2010-07-30 06:44:31 +00:00
Jim Grosbach d343166a0b Many Thumb2 instructions can reference the full ARM register set (i.e., 
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
  mls r0,r9,r0,sp
instead of:
  mov r2, sp
  mls r0, r9, r0, r2

This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.

PR7499

llvm-svn: 109842
 2010-07-30 02:41:01 +00:00
Eric Christopher 2e276485cb Fix this up per llvm-gcc r109819. 
llvm-svn: 109820
 2010-07-29 23:20:29 +00:00
Benjamin Kramer d9624e2d2e Remove XFAIL, test doesn't leak anymore. 
llvm-svn: 109801
 2010-07-29 20:36:36 +00:00
Dale Johannesen 2bff50546c Implement vector constants which are splat of 
integers with mov + vdup.  8003375.  This is
currently disabled by default because LICM will
not hoist a VDUP, so it pessimizes the code if
the construct occurs inside a loop (8248029).

llvm-svn: 109799
 2010-07-29 20:10:08 +00:00
Dan Gohman 390914cbe8 Make GlobalValue alignment consistent with load, store, and alloca 
alignment, fixing silent truncation of alignment values.

llvm-svn: 109653
 2010-07-28 20:56:48 +00:00
Dan Gohman a7e5a24093 Define a maximum supported alignment value for load, store, and 
alloca instructions (constrained by their internal encoding),
and add error checking for it. Fix an instcombine bug which
generated huge alignment values (null is infinitely aligned).
This fixes undefined behavior noticed by John Regehr.

llvm-svn: 109643
 2010-07-28 20:12:04 +00:00
Nate Begeman 53afc8f06a Implement a vectorized algorithm for <16 x i8> << <16 x i8> 
This is about 4x faster and smaller than the existing scalarization.

llvm-svn: 109566
 2010-07-28 00:21:48 +00:00
Stuart Hastings a7f1d4a2ba Testcase for r109556. Radar 8198362. 
llvm-svn: 109557
 2010-07-27 23:15:25 +00:00
Nate Begeman 269a6da023 ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller types coming in future patches. 
For:

define <2 x i64> @shl(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
entry:
  %shl = shl <4 x i32> %r, %a                     ; <<4 x i32>> [#uses=1]
  %tmp2 = bitcast <4 x i32> %shl to <2 x i64>     ; <<2 x i64>> [#uses=1]
  ret <2 x i64> %tmp2
}

We get:

_shl:                                   ## @shl
	pslld	$23, %xmm1
	paddd	LCPI0_0, %xmm1
	cvttps2dq	%xmm1, %xmm1
	pmulld	%xmm1, %xmm0
	ret

Instead of:

_shl:                                   ## @shl
	pshufd	$3, %xmm0, %xmm2
	movd	%xmm2, %eax
	pshufd	$3, %xmm1, %xmm2
	movd	%xmm2, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	pshufd	$1, %xmm0, %xmm3
	movd	%xmm3, %eax
	pshufd	$1, %xmm1, %xmm3
	movd	%xmm3, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm3
	punpckldq	%xmm2, %xmm3
	movd	%xmm0, %eax
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	movhlps	%xmm0, %xmm0
	movd	%xmm0, %eax
	movhlps	%xmm1, %xmm1
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm0
	punpckldq	%xmm0, %xmm2
	movdqa	%xmm2, %xmm0
	punpckldq	%xmm3, %xmm0
	ret

llvm-svn: 109549
 2010-07-27 22:37:06 +00:00
Devang Patel bd32256e25 Update tests to not rely on input file's absolute path. 
llvm-svn: 109521
 2010-07-27 18:13:53 +00:00
Nate Begeman 317b969ac5 Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself 
recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR.

llvm-svn: 109519
 2010-07-27 18:02:18 +00:00
Tobias Grosser 731b079edb Make coff-dump.py executable and add python as executable for this script. 
This fixes the MC/COFF/basic-coff.ll test case.

llvm-svn: 109497
 2010-07-27 09:01:26 +00:00
Michael J. Spencer f8270bdb2d Make MC use Windows COFF on Windows and add tests. 
llvm-svn: 109494
 2010-07-27 06:46:15 +00:00
Anton Korobeynikov 6bcea068db Currently EH lowering code expects typeinfo to be global only. 
This assumption is not satisfied due to global mergeing.
Workaround the issue by temporary disablinge mergeing of const globals.
Also, ignore LLVM "special" globals. This fixes PR7716

llvm-svn: 109423
 2010-07-26 18:45:39 +00:00
Owen Anderson bb4c4b59a4 Fix a test with malformed IR. Not sure why this didn't fail before. 
llvm-svn: 109422
 2010-07-26 18:44:56 +00:00
Dan Gohman cd83870faf Fix SCEVExpander::visitAddRecExpr so that it remembers the induction variable 
it inserted rather than using LoopInfo::getCanonicalInductionVariable to
rediscover it, since that doesn't work on non-canonical loops. This fixes
infinite recurrsion on such loops; PR7562.

llvm-svn: 109419
 2010-07-26 18:28:14 +00:00
Dan Gohman b0961f2443 Avoid depending on LCSSA implicitly pulling in LoopSimplify. 
llvm-svn: 109410
 2010-07-26 18:00:43 +00:00
Bruno Cardoso Lopes 306a1f9721 Support x86 "eiz" and "riz" pseudo index registers in the assembler. 
llvm-svn: 109295
 2010-07-24 00:06:39 +00:00
Matt Fleming fbd7f65248 Consolidate the ELF section directive tests into a single file as 
suggested by Chris Lattner.

llvm-svn: 109290
 2010-07-23 23:40:41 +00:00
Evan Cheng df907f4594 - Allow target to specify when is register pressure "too high". In most cases, 
it's too late to start backing off aggressive latency scheduling when most
  of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
  For ARM, this is almost always a win on # of instructions. It's runtime
  neutral for most of the tests. But for some kernels with high register
  pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
  54 and sped up by 20%.

llvm-svn: 109279
 2010-07-23 22:39:59 +00:00
Bruno Cardoso Lopes 6f38011196 Move AVX encoding tests to different files 
llvm-svn: 109269
 2010-07-23 21:25:26 +00:00
Dan Gohman 55e244698a Use the proper type for shift counts. This fixes a bootstrap error. 
llvm-svn: 109265
 2010-07-23 21:08:12 +00:00
Stuart Hastings caf8e3a2db Test case to insure template function declaration refers to correct filename. Radar 8063111. 
llvm-svn: 109258
 2010-07-23 20:15:49 +00:00
Bruno Cardoso Lopes ea0e05a3ce Add AVX version of CLMUL instructions 
llvm-svn: 109248
 2010-07-23 18:41:12 +00:00
Dan Gohman 0818684a70 DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 
are not demanded. This often allows the anyext to be folded away.

llvm-svn: 109242
 2010-07-23 18:03:30 +00:00
Bruno Cardoso Lopes acd9230b1b Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual 
llvm-svn: 109204
 2010-07-23 00:54:35 +00:00
Bruno Cardoso Lopes 0710c74f29 Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step 
llvm-svn: 109168
 2010-07-22 21:18:49 +00:00
Tobias Grosser 336734aca6 Add new RegionInfo pass. 
The RegionInfo pass detects single entry single exit regions in a function,
where a region is defined as any subgraph that is connected to the remaining
graph at only two spots.
Furthermore an hierarchical region tree is built.
Use it by calling "opt -regions analyze" or "opt -view-regions".

llvm-svn: 109089
 2010-07-22 07:46:31 +00:00
Eric Christopher 9a77382685 Custom lower the memory barrier instructions and add support 
for lowering without sse2.  Add a couple of new testcases.

Fixes a few libgomp tests and latent bugs.  Remove a few todos.

llvm-svn: 109078
 2010-07-22 02:48:34 +00:00
Evan Cheng 285903853f More register pressure aware scheduling work. 
llvm-svn: 109064
 2010-07-21 23:53:58 +00:00
Bruno Cardoso Lopes e3acfd4d58 Add more 256-bit forms for a bunch of regular AVX instructions 
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)

llvm-svn: 109063
 2010-07-21 23:53:50 +00:00
Eric Christopher 84bdfd80df Baby steps towards ARM fast-isel. 
llvm-svn: 109047
 2010-07-21 22:26:11 +00:00
Bruno Cardoso Lopes 6238c1d102 Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it 
llvm-svn: 109039
 2010-07-21 21:37:59 +00:00
Dan Gohman 093cb79d4b Disallow null as a named metadata operand. 
Make MDNode::destroy private.
Fix the one thing that used MDNode::destroy, outside of MDNode itself.

One should never delete or destroy an MDNode explicitly. MDNodes
implicitly go away when there are no references to them (implementation
details aside).

llvm-svn: 109028
 2010-07-21 18:54:18 +00:00
Rafael Espindola 4277e14dc4 Fix calling convention on ARM if vfp2+ is enabled. 
llvm-svn: 109009
 2010-07-21 11:38:30 +00:00
Bruno Cardoso Lopes cdbec62510 Add AVX only vzeroall and vzeroupper instructions 
llvm-svn: 109002
 2010-07-21 08:56:24 +00:00
Eric Christopher 690aa72437 Turn this test on again after the llvm-gcc change in r108986. 
llvm-svn: 108987
 2010-07-21 04:54:06 +00:00
Eric Christopher 8d95d26eb1 Update this to use a "valid" alignment. 
llvm-svn: 108985
 2010-07-21 04:51:24 +00:00
Bruno Cardoso Lopes 3499934da6 Add new AVX vpermilps, vpermilpd and vperm2f128 instructions 
llvm-svn: 108984
 2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes 3ceaf7a0a2 Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it 
llvm-svn: 108983
 2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes e706501975 Add new AVX vextractf128 instructions 
llvm-svn: 108964
 2010-07-20 23:19:02 +00:00
Matt Fleming c3eb5e3d4b Include some tests for the recently committed ELF section directive 
handlers.

llvm-svn: 108938
 2010-07-20 21:37:30 +00:00
Eric Christopher 3f696ff489 Testcase for llvm-gcc commit r108910. 
llvm-svn: 108918
 2010-07-20 20:32:47 +00:00
Bruno Cardoso Lopes 3b505848fd Add new AVX instruction vinsertf128 
llvm-svn: 108892
 2010-07-20 19:44:51 +00:00
Dan Gohman 625fd2292d Fix SCEV denormalization of expressions where the exit value from 
one loop is involved in the increment of an addrec for another
loop. This fixes rdar://8168938.

llvm-svn: 108863
 2010-07-20 17:06:20 +00:00
Jim Grosbach badf087e45 update tests for smarter BIC usage 
llvm-svn: 108846
 2010-07-20 16:16:48 +00:00
Duncan Sands 2e839de377 The same problem was being tracked in PR7652. 
llvm-svn: 108843
 2010-07-20 15:52:32 +00:00
Bruno Cardoso Lopes 160695fecb Fix PR7174, a couple o Mips fixes: 
- Fix a typo for PIC check during jmp table lowering
- Also fix the "first jump table basic block is not
considered only reachable by fall through" problem, use this
ad-hoc solution until I come up with something better.

Patch by stetorvs@gmail.com

llvm-svn: 108820
 2010-07-20 08:37:04 +00:00
Bruno Cardoso Lopes ea7863647b Fix Mips PR7473. Patch by stetorvs@gmail.com 
llvm-svn: 108816
 2010-07-20 07:58:51 +00:00
Bruno Cardoso Lopes 6c8041ea34 x86_32 tests for vbroadcast 
llvm-svn: 108789
 2010-07-20 00:11:50 +00:00
Bruno Cardoso Lopes 14c5fd437c Add AVX vbroadcast new instruction 
llvm-svn: 108788
 2010-07-20 00:11:13 +00:00
Bruno Cardoso Lopes 9de0ca73d4 Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions! 
llvm-svn: 108769
 2010-07-19 23:32:44 +00:00
Dan Gohman b5e918dc05 After a custom inserter, in a block which has constant instructions, 
update the current basic block in addition to the current insert
position, so that they remain consistent. This fixes rdar://8204072.

llvm-svn: 108765
 2010-07-19 22:48:56 +00:00
Daniel Dunbar 9db7d0addd X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same 
instruction, we only want to allow the one for the current subtarget.
 - This also fixes suffix matching for jmp instructions, because it eliminates
   the ambiguity between 'jmpl' and 'jmpq'.

llvm-svn: 108746
 2010-07-19 20:44:16 +00:00
Dale Johannesen d4e389441d Testcase for 108732 (8195660). 
llvm-svn: 108733
 2010-07-19 18:22:40 +00:00
Devang Patel 18efced1a2 Fix PR 7662. 
Do not try to insert local variable info to a DIE used for function declaration.

llvm-svn: 108731
 2010-07-19 17:53:55 +00:00
Owen Anderson 3ccd81864f Testcase for r108687. 
llvm-svn: 108689
 2010-07-19 08:14:26 +00:00
Owen Anderson 9c271e2835 Remove r108639 now that it is handled by InstCombine instead. 
llvm-svn: 108688
 2010-07-19 08:10:24 +00:00
Daniel Dunbar 9aefb8ee4c X86-64: Mark WINCALL and more tail call instructions as code gen only. 
llvm-svn: 108685
 2010-07-19 07:21:07 +00:00
Daniel Dunbar b82cd9319b MC/X86: We now match instructions like "incl %eax" correctly for the arch we are 
assembling; remove crufty custom cleanup code.

llvm-svn: 108681
 2010-07-19 06:14:54 +00:00
Daniel Dunbar af75e1923c tests: Force another triple. 
llvm-svn: 108666
 2010-07-19 00:43:58 +00:00
Daniel Dunbar 3b4621103a tests: Force triples. 
llvm-svn: 108658
 2010-07-18 21:16:10 +00:00
Daniel Dunbar 40a564f09f MC/AsmParser: Fix .abort and .secure_log_unique to accept arbitrary token 
sequences, not just strings.

llvm-svn: 108655
 2010-07-18 20:15:59 +00:00
Daniel Dunbar 6fb1c3ad8a MC/AsmParser: Add macro argument substitution support. 
llvm-svn: 108654
 2010-07-18 19:00:10 +00:00
Daniel Dunbar 4323571efb MC/AsmParser: Add basic support for macro instantiation. 
llvm-svn: 108653
 2010-07-18 18:54:11 +00:00
Daniel Dunbar c1f58ec83c MC/AsmParser: Add basic parsing support for .macro definitions. 
llvm-svn: 108652
 2010-07-18 18:47:21 +00:00
Chris Lattner ede90a2a58 daniel doesn't hate me, he hates macpython 2.5, which 
is a very reasonable position on life!

llvm-svn: 108650
 2010-07-18 18:42:18 +00:00
Daniel Dunbar 828984ff4e MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don't 
support macros.

llvm-svn: 108649
 2010-07-18 18:38:02 +00:00
Owen Anderson 41670a11a8 Add a testcase for r108639. 
llvm-svn: 108640
 2010-07-18 08:57:19 +00:00
Owen Anderson 7d2818b073 Another attempt at getting the clang self-host to like my instcombine patch. 
llvm-svn: 108614
 2010-07-17 06:56:35 +00:00
Jim Grosbach b97e2bbe32 Add combiner patterns to more effectively utilize the BFI (bitfield insert) 
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.

llvm-svn: 108608
 2010-07-17 03:30:54 +00:00
Eli Friedman ceb16a5ce9 Test for ELF .size directive. 
llvm-svn: 108607
 2010-07-17 03:15:24 +00:00
Jim Grosbach 11013eda5a Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction 
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.

llvm-svn: 108570
 2010-07-16 23:05:05 +00:00
Bill Wendling bf8370ff36 Consider this function: 
void foo() { __builtin_unreachable(); }

It will output the following on Darwin X86:

_func1:
Leh_func_begin0:
        pushq %rbp
Ltmp0:
        movq %rsp, %rbp
Ltmp1:
Leh_func_end0:

This prolog adds a new Call Frame Information (CFI) row to the FDE with an
address that is not within the address range of the code it describes -- part is
equal to the end of the function -- and therefore results in an invalid EH
frame. If we emit a nop in this situation, then the CFI row is now within the
address range.

llvm-svn: 108568
 2010-07-16 22:51:10 +00:00
Jakob Stoklund Olesen c30b4ddc58 Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill 
pass that inserted it.

It is no longer necessary to limit the live ranges of FP registers to a single
basic block.

llvm-svn: 108536
 2010-07-16 17:41:44 +00:00
Benjamin Kramer 50729ad717 Feed the right output into FileCheck. 
llvm-svn: 108523
 2010-07-16 10:58:02 +00:00
Nick Lewycky 375efe3157 Arrays and vectors with different numbers of elements are not equivalent. 
llvm-svn: 108517
 2010-07-16 06:31:12 +00:00
Tobias Grosser 3d84c9c793 LoopSimplify does not update domfrontier correctly. 
This fixes PR7649.

llvm-svn: 108513
 2010-07-16 05:59:45 +00:00
Jakob Stoklund Olesen 37c42a3d02 Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. 
TII::isMoveInstr is going tobe completely removed.

llvm-svn: 108507
 2010-07-16 04:45:42 +00:00
Jakob Stoklund Olesen b1671271ab Add forgotten test case. 
llvm-svn: 108506
 2010-07-16 04:45:35 +00:00
Dan Gohman 103c4ebea5 Use the source-order scheduler instead of the "fast" scheduler at -O0, 
because it's more likely to keep debug line information in its original
order.

llvm-svn: 108496
 2010-07-16 02:01:19 +00:00
Eric Christopher 15a81cddb4 Also revert 108422, it's causing some test failures. 
Working on testcases for Owen.

llvm-svn: 108494
 2010-07-16 01:36:12 +00:00
Dan Gohman c6eefe4d4e Fix this test. 
llvm-svn: 108491
 2010-07-16 01:28:45 +00:00
Dale Johannesen bfd4fd7bb7 The SelectionDAGBuilder's handling of debug info, on rare 
occasions, caused code to be generated in a different order.
All cases I've seen involved float softening in the type
legalizer, and this could be perhaps be fixed there, but
it's better not to generate things differently in the first
place.  7797940 (6/29/2010..7/15/2010).

llvm-svn: 108484
 2010-07-16 00:02:08 +00:00
Bill Wendling 4bda1c8e68 Revert. This isn't the correct way to go. 
llvm-svn: 108478
 2010-07-15 23:42:21 +00:00
Dan Gohman fbbdfcaea7 Fix the order that SCEVExpander considers add operands in so that 
it doesn't miss an opportunity to form a GEP, regardless of the
relative loop depths of the operands. This fixes rdar://8197217.

llvm-svn: 108475
 2010-07-15 23:38:13 +00:00
Bill Wendling 973dc3b1d8 Handle code gen for the unreachable instruction if it's the only instruction in 
the function. We'll just turn it into a "trap" instruction instead.

The problem with not handling this is that it might generate a prologue without
the equivalent epilogue to go with it:

$ cat t.ll
define void @foo() {
entry:
  unreachable
}
$ llc -o - t.ll -relocation-model=pic -disable-fp-elim -unwind-tables
        .section        __TEXT,__text,regular,pure_instructions
        .globl  _foo
        .align  4, 0x90
_foo:                                   ## @foo
Leh_func_begin0:
## BB#0:                                ## %entry
        pushq   %rbp
Ltmp0:
        movq    %rsp, %rbp
Ltmp1:
Leh_func_end0:
...

The unwind tables then have bad data in them causing all sorts of problems.

Fixes <rdar://problem/8096481>.

llvm-svn: 108473
 2010-07-15 23:32:40 +00:00
Evan Cheng 55f0c6b9fc Split -enable-finite-only-fp-math to two options: 
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.

llvm-svn: 108465
 2010-07-15 22:07:12 +00:00
Chris Lattner 60b131654b fix the definitions of ConstTextCoalSection/ConstDataCoalSection 
to keep "Text" in sync with the "pure instructions" section attribute.
Lack of this attribute was preventing the assembler from emitting
multibyte noops instructions for templates (and inlines, and other
coalesced stuff) and was causing the assembler to mismatch .o files.

This fixes rdar://8018335

llvm-svn: 108461
 2010-07-15 21:22:00 +00:00
Devang Patel df09db62e2 Fix crash reported in PR7653. 
llvm-svn: 108441
 2010-07-15 18:45:27 +00:00
Dan Gohman 4afd412d6b Watch out for a constant offset cancelling out a base register, forming 
a zero. This situation arrises in Fortran code with induction variables
that start at 1 instead of 0. This fixes PR7651.

llvm-svn: 108424
 2010-07-15 15:14:45 +00:00
Owen Anderson 7151dfd48a Reapply r108378, with bugfixes, testcase, and improved comment formatting. 
This now passes LIT, nighty test, and llvm-gcc bootstrap on my machine.

llvm-svn: 108422
 2010-07-15 15:00:23 +00:00
Chris Lattner 19eff2a9f6 Fix PR7647, handling the case when 'To' ends up being 
mutated by recursive simplification.  This also enhances
ReplaceAndSimplifyAllUses to actually do a real RAUW
at the end of it, which updates any value handles
pointing to "From" to start pointing to "To".  This
seems useful for debug info and random other VH users.

llvm-svn: 108415
 2010-07-15 06:36:08 +00:00
Chris Lattner e985a63bbf see comment. 
llvm-svn: 108409
 2010-07-15 05:17:36 +00:00
Eric Christopher 25e72a8920 Temporarily disable this test. 
llvm-svn: 108371
 2010-07-14 23:12:58 +00:00
Devang Patel 29168baf4b Make it a .ll test case. 
llvm-svn: 108370
 2010-07-14 23:12:52 +00:00
Eric Christopher e34b383e71 Add a testcase for the vla and stack realignment warning. 
llvm-svn: 108365
 2010-07-14 22:26:35 +00:00
Dale Johannesen 6fe8c37a01 Tests for llvm-gcc commit 108360. 
llvm-svn: 108362
 2010-07-14 21:22:35 +00:00
Jim Grosbach a90af1ba38 Improve 64-subtraction of immediates when parts of the immediate can fit 
in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284

llvm-svn: 108339
 2010-07-14 17:45:16 +00:00
Dan Gohman 042523340b Delete fast-isel's trivial load optimization; it breaks debugging because 
it can look past points where a debugger might modify user variables.

llvm-svn: 108336
 2010-07-14 17:25:37 +00:00
Bob Wilson bb57896f8e Fix test to appease the buildbots. 
llvm-svn: 108334
 2010-07-14 16:43:47 +00:00
Evan Cheng a8e8874552 Fix for PR7193 was overly conservative. The only case where sibcall callee 
address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.

This fixes PR7610.

llvm-svn: 108327
 2010-07-14 06:44:01 +00:00
Bob Wilson bad47f62f6 Add support for NEON VMVN immediate instructions. 
llvm-svn: 108324
 2010-07-14 06:31:50 +00:00