af66980d8a
Fix whitespace.
...
llvm-svn: 128370
2011-03-27 01:44:40 +00:00
e466345675
Use individual register classes when spilling snippets.
...
The main register class may have been inflated by live range splitting, so that
register class is not necessarily valid for the snippet instructions.
Use the original register class for the stack slot interval.
llvm-svn: 128351
2011-03-26 22:16:41 +00:00
355ce07425
Turn SelectionDAGBuilder::GetRegistersForValue into a local function.
...
It couldn't be used outside of the file because SDISelAsmOperandInfo
is local to SelectionDAGBuilder.cpp. Making it a static function avoids
a weird linkage dance.
llvm-svn: 128342
2011-03-26 16:35:10 +00:00
8d2227373d
Make helper static.
...
llvm-svn: 128338
2011-03-26 12:38:19 +00:00
b5139920d6
Simplification noticed by Frits.
...
llvm-svn: 128333
2011-03-26 09:32:07 +00:00
19f33b9393
Rework the logic that determines if a store completely overlaps an ealier store.
...
There are two ways that a later store can comletely overlap a previous store:
1. They both start at the same offset, but the earlier store's size is <= the
later's size, or
2. The earlier store's offset is > the later's offset, but it's offset + size
doesn't extend past the later's offset + size.
llvm-svn: 128332
2011-03-26 08:02:59 +00:00
d4174ee43e
Fix a typo and add a test.
...
llvm-svn: 128331
2011-03-26 04:58:50 +00:00
9a624fa993
Collect and coalesce DBG_VALUE instructions before emitting the function.
...
Correctly terminate the range of register DBG_VALUEs when the register is
clobbered or when the basic block ends.
The code is now ready to deal with variables that are sometimes in a register
and sometimes on the stack. We just need to teach emitDebugLoc to say 'stack
slot'.
llvm-svn: 128327
2011-03-26 02:19:36 +00:00
923f3dac01
Fixed the t2PLD and friends disassembly and add two test cases.
...
llvm-svn: 128322
2011-03-26 01:32:48 +00:00
d553096688
Fix the bfi handling for or (and a mask) (and b mask). We need the two
...
masks to match inversely for the code as is to work. For the example given
we actually want:
bfi r0, r2, #1 , #1
not #0 , however, given the way the pattern is written it's not possible
at the moment.
Fixes rdar://9177502
llvm-svn: 128320
2011-03-26 01:21:03 +00:00
db40b5c899
PR9561: A store with a negative offset (via GEP) could erroniously say that it
...
completely overlaps a previous store, thus mistakenly deleting that store. Check
for this condition.
llvm-svn: 128319
2011-03-26 01:20:37 +00:00
d077a857cc
Remove the files for r128308 as it is causing a buildbot failure.
...
llvm-svn: 128309
2011-03-26 00:23:05 +00:00
c8b4078654
Adding a C API to the disassembler for use by such tools as Darwin's otool(1).
...
This is a work in progress as the interface for producing symbolic operands is
not done. But a hacked prototype using information from the object file's
relocation entiries and replacing immediate operands with MCExpr's has been
shown to work with no changes to the instrucion printer. These APIs will be
moved into a dynamic library at some point.
llvm-svn: 128308
2011-03-26 00:06:33 +00:00
49316e40ba
Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
...
Also add some test cases.
rdar://problem/9189829
llvm-svn: 128304
2011-03-25 22:19:07 +00:00
aaf2c69400
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
...
rdar://problem/9182892
llvm-svn: 128299
2011-03-25 19:35:37 +00:00
b35548f44d
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
...
t2LDREX/t2STREX instructions. Add two test cases.
llvm-svn: 128293
2011-03-25 18:29:49 +00:00
6f4c9425eb
MC: Improve some diagnostics on uses of '.' pseudo-symbol.
...
llvm-svn: 128289
2011-03-25 17:47:17 +00:00
3f56104be1
Tidyness.
...
llvm-svn: 128288
2011-03-25 17:47:14 +00:00
dc0082b087
Add a note.
...
llvm-svn: 128286
2011-03-25 17:32:40 +00:00
aa84d41dfc
Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.
...
rdar://problem/9184053
llvm-svn: 128285
2011-03-25 17:31:16 +00:00
1886a4c823
Emit less labels for debug info and stop emitting .loc directives for DBG_VALUEs.
...
The .dot directives don't need labels, that is a leftover from when we created
line number info manually.
Instructions following a DBG_VALUE can share its label since the DBG_VALUE
doesn't produce any code.
llvm-svn: 128284
2011-03-25 17:20:59 +00:00
757ca69770
Also need to handle invalid imod values for CPS2p.
...
rdar://problem/9186136
llvm-svn: 128283
2011-03-25 17:03:12 +00:00
3bd8b7a388
Fix for -pre-RA-sched=source.
...
Yet another case of unchecked NULL node (for physreg copy).
May fix PR9509.
llvm-svn: 128266
2011-03-25 06:40:55 +00:00
0e25c8b364
No functionality change, just adjust some whitespace for coding style compliance.
...
llvm-svn: 128257
2011-03-25 06:05:50 +00:00
d73218e4a3
No functionality change. Fix up some whitespace and switch out "" for '' when
...
printing a single character.
llvm-svn: 128256
2011-03-25 06:04:26 +00:00
a1e3156ebd
Ignore special ARM allocation hints for unexpected register classes.
...
Add an assertion to linear scan to prevent it from allocating registers outside
the register class.
<rdar://problem/9183021>
llvm-svn: 128254
2011-03-25 01:48:18 +00:00
a52143bff3
Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
...
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.
llvm-svn: 128252
2011-03-25 01:09:48 +00:00
303e3161bb
Suppress an unused variable warning in -asserts builds
...
llvm-svn: 128244
2011-03-24 22:05:48 +00:00
9302df0ad9
Handle the added VBICiv*i* NEON instructions, too.
...
llvm-svn: 128243
2011-03-24 22:04:39 +00:00
02e59ad506
Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!
...
llvm-svn: 128241
2011-03-24 21:42:55 +00:00
6469ca0c33
T2 Load/Store Multiple:
...
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add a test case.
llvm-svn: 128240
2011-03-24 21:36:56 +00:00
dd9eb21c3f
Plug a leak in the arm disassembler and put the tests back.
...
llvm-svn: 128238
2011-03-24 21:14:28 +00:00
f170f8bff6
Add asm parsing support w/ testcases for strex/ldrex family of instructions
...
llvm-svn: 128236
2011-03-24 21:04:58 +00:00
8bbc12824a
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
...
Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
llvm-svn: 128234
2011-03-24 20:42:48 +00:00
e01b75cb89
Keep track of directory namd and fIx regression caused by Rafael's patch r119613.
...
A better approach would be to move source id handling inside MC.
llvm-svn: 128233
2011-03-24 20:30:50 +00:00
a3df87fb01
Clean up assembly statement separator support.
...
The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.
llvm-svn: 128227
2011-03-24 18:46:34 +00:00
c5207f7167
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
...
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
llvm-svn: 128226
2011-03-24 18:40:38 +00:00
1dd041083d
Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
...
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.
llvm-svn: 128220
2011-03-24 17:04:22 +00:00
a4ec5b2c19
revert r128199 until it can be made to work with Frontend/dependency-gen.c.
...
llvm-svn: 128218
2011-03-24 16:43:37 +00:00
74157ab3e5
Debug intrinsics must be skipped at the beginning and ends of blocks, lest they
...
affect the generated code.
llvm-svn: 128217
2011-03-24 16:34:59 +00:00
2edfe778ec
It is enough for the CallInst to have no uses to be made a tail call with a ret
...
void; it doesn't need to have a void type.
llvm-svn: 128212
2011-03-24 15:54:11 +00:00
8f606d7b9b
s/UpdateDT/ModifiedDT/g
...
llvm-svn: 128211
2011-03-24 15:35:25 +00:00
521eb7c11e
Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.
...
FIXME: Some cleanups would be needed.
llvm-svn: 128206
2011-03-24 07:07:00 +00:00
f098bf1199
Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry
...
entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.
rdar://9125354
llvm-svn: 128203
2011-03-24 06:20:03 +00:00
e42162ad59
Remove all uses of PATH_MAX and MAXPATHLEN from PathV2.
...
llvm-svn: 128199
2011-03-24 05:23:40 +00:00
4649f17db1
Do early taildup of ret in CodeGenPrepare for potential tail calls that have a
...
void return type. This fixes PR9487.
llvm-svn: 128197
2011-03-24 04:52:10 +00:00
0e331c05ae
Use an early return instead of a long if block.
...
llvm-svn: 128196
2011-03-24 04:52:07 +00:00
dd84bcce8f
When UpdateDT is set, DT is invalid, which could cause problems when trying to
...
use it later. I couldn't make a test that hits this with the current code.
llvm-svn: 128195
2011-03-24 04:52:04 +00:00
47e7175fe9
Check for TLI so that -codegenprepare can be used from opt.
...
llvm-svn: 128194
2011-03-24 04:51:51 +00:00
a75d158c41
CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function.
...
Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)
Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
Before:
cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!
After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^
llvm-svn: 128192
2011-03-24 02:24:36 +00:00
NAKAMURA Takumi