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9 Commits

Author SHA1 Message Date
Evan Cheng a20a773654 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode. 
Before:
_main:
        subq    $8, %rsp
        leaq    _X(%rip), %rax
        movsd   8(%rax), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret
Now:
_main:
        subq    $8, %rsp
        movsd   _X+8(%rip), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret

Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl    %ecx, %ecx
movl    %ecx, %eax

llvm-svn: 46850
 2008-02-07 08:53:49 +00:00
Nate Begeman e14fdfaecd SSE 4.1 Intrinsics and detection 
llvm-svn: 46681
 2008-02-03 07:18:54 +00:00
Evan Cheng 084a1cdcdd Work in progress. This patch *fixes* x86-64 calls which are modelled as StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results. 
Status: This only works for direct calls, and only the caller side is done. Disabled for now.

llvm-svn: 46527
 2008-01-29 19:34:22 +00:00
Duncan Sands 95d46ef887 The last pieces needed for loading arbitrary 
precision integers.  This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on.  While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.

llvm-svn: 46280
 2008-01-23 20:39:46 +00:00
Chris Lattner 806dd0e2ac remove xchg and shift-reg-by-1 instructions, which are dead. 
llvm-svn: 45870
 2008-01-11 18:00:50 +00:00
Evan Cheng 8c51394e01 Rename Int_CVTSI642SSr* to Int_CVTSI2SS64r* for naming consistency and remove unused instructions. 
llvm-svn: 45861
 2008-01-11 07:37:44 +00:00
Chris Lattner 9283173061 more flags set right 
llvm-svn: 45860
 2008-01-11 07:18:17 +00:00
Chris Lattner 317332fc2a Start inferring side effect information more aggressively, and fix many bugs in the 
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects.  It would be really nice if we could
write patterns for copy instructions.

I have audited all the x86 instructions down to MOVDQAmr.  The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.

llvm-svn: 45829
 2008-01-10 07:59:24 +00:00
Chris Lattner 2e38f2458c rename X86InstrX86-64.td -> X86Instr64bit.td 
llvm-svn: 45826
 2008-01-10 05:50:42 +00:00