4 Commits

Author	SHA1	Message	Date
Simon Pilgrim	0afe97f480	[X86][SSE] Dropped -mcpu from vector shift tests ... Use triple and attribute only for consistency llvm-svn: 306662	2017-06-29 11:09:53 +00:00
Simon Pilgrim	ba325e3a73	[X86][SSE] Don't blend vector shifts with MOVSS/MOVSD directly, lower from generic shuffle ... Shuffle lowering will correctly lower to MOVSS/MOVSD/PBLEND, improving commutation opportunities llvm-svn: 281471	2016-09-14 14:08:18 +00:00
Simon Pilgrim	f1f55198c1	[X86][SSE] Regenerate vector shift lowering tests ... llvm-svn: 278232	2016-08-10 15:13:49 +00:00
Andrea Di Biagio	aac2eac4c2	[X86] Improve the lowering of packed shifts by constant build_vector. ... This patch teaches the backend how to efficiently lower logical and arithmetic packed shifts on both SSE and AVX/AVX2 machines. When possible, instead of scalarizing a vector shift, the backend should try to expand the shift into a sequence of two packed shifts by immedate count followed by a MOVSS/MOVSD. Example (v4i32 (srl A, (build_vector < X, Y, Y, Y>))) Can be rewritten as: (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>))) [with X and Y ConstantInt] The advantage is that the two new shifts from the example would be lowered into X86ISD::VSRLI nodes. This is always cheaper than scalarizing the vector into four scalar shifts plus four pairs of vector insert/extract. llvm-svn: 206316	2014-04-15 19:30:48 +00:00