ad677b64db
Add PPC 440 scheduler and some associated tests (new files)
...
llvm-svn: 142171
2011-10-17 04:03:55 +00:00
6fa5697af0
Add PPC 440 scheduler and some associated tests
...
llvm-svn: 142170
2011-10-17 04:03:49 +00:00
3e8aa65bc2
Add a routine to swap branch instruction operands, and update any
...
profile metadata at the same time. Use it to preserve metadata attached
to a branch when re-writing it in InstCombine.
Add metadata to the canonicalize_branch InstCombine test, and check that
it is tranformed correctly.
Reviewed by Nick Lewycky!
llvm-svn: 142168
2011-10-17 01:11:57 +00:00
91f4faf877
Delete a dead member. Dunno if this was ever used, but the current code
...
directly manipulates the weights inside of the BranchProbabilityInfo
that is passed in.
llvm-svn: 142163
2011-10-16 22:27:54 +00:00
47e1db1e59
Add a proper LLVM banner to this file.
...
llvm-svn: 142162
2011-10-16 22:15:07 +00:00
486ff59a9f
Enable element promotion type legalization by deafault.
...
Changed tests which assumed that vectors are legalized by widening them.
llvm-svn: 142152
2011-10-16 20:31:33 +00:00
0a7e9ccf04
When looking for dependencies on the src pointer, scan the src pointer. Scanning
...
on the memcpy call will pull up other unrelated stuff. Fixes PR11142.
llvm-svn: 142150
2011-10-16 20:13:32 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
...
llvm-svn: 142141
2011-10-16 16:50:08 +00:00
cc863b2bb6
Let printf do the formatting instead aligning strings ourselves.
...
While at it, merge some format strings.
llvm-svn: 142140
2011-10-16 16:30:34 +00:00
cb6b02a086
Twinify better.
...
llvm-svn: 142139
2011-10-16 15:46:29 +00:00
1930b003fe
Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing.
...
<stdin>:1:12: error: register %rax is only available in 64-bit mode
incl %rax
^~~~
llvm-svn: 142137
2011-10-16 12:10:27 +00:00
d416bae5f2
X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands.
...
<stdin>:1:4: error: invalid instruction mnemonic 'abc'
abc incl %edi
^~~
llvm-svn: 142135
2011-10-16 11:28:29 +00:00
47f5e30e78
PR11143: Save the old diagnostic handler and call it when munging diagnostics for #line directives.
...
This reenables proper inline asm diagnostics in clang
llvm-svn: 142132
2011-10-16 10:48:29 +00:00
bc25b6eb67
Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
...
no pattern.
llvm-svn: 142130
2011-10-16 10:02:06 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
...
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
...
llvm-svn: 142117
2011-10-16 07:05:40 +00:00
434b3bff44
Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.
...
These missing flags show up as errors when running -verify-coalescing on
test-suite.
llvm-svn: 142111
2011-10-16 06:38:10 +00:00
08ca5d35bd
Fix an obvious typo found when looking at nearby code.
...
llvm-svn: 142110
2011-10-16 06:38:06 +00:00
7284526aff
remove the dead 'ShowLine' argument from SMDiagnostic.
...
llvm-svn: 142108
2011-10-16 05:47:55 +00:00
03b80a4027
Make SMDiagnostic a little more sane. Instead of passing around note/warning/error as a
...
string, pass it around as an enum.
llvm-svn: 142107
2011-10-16 05:43:57 +00:00
a3a0681083
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
...
the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
llvm-svn: 142106
2011-10-16 04:47:35 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
...
llvm-svn: 142105
2011-10-16 03:51:13 +00:00
6c8879e3ab
Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7.
...
llvm-svn: 142089
2011-10-16 00:21:51 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
...
llvm-svn: 142082
2011-10-15 20:46:47 +00:00
45f0f87af5
The CELL backend cannot select patterns for vector trunc-store and shl on v2i64; CellSPU/shift_ops.ll fails when promoting elements.
...
llvm-svn: 142081
2011-10-15 20:05:17 +00:00
097106b77a
ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when promoting elements.
...
llvm-svn: 142080
2011-10-15 20:03:12 +00:00
5fb5e3b384
SmallVector -> array
...
llvm-svn: 142073
2011-10-15 13:28:31 +00:00
f537a6edd4
Don't replace all dominated uses if there is only one use, since that
...
use can't be dominated, saving one domtree lookup.
llvm-svn: 142066
2011-10-15 11:13:42 +00:00
4d681d7dc4
Add a bad char heuristic to StringRef::find.
...
Based on Horspool's simplified version of Boyer-Moore. We use a constant-sized table of
uint8_ts to keep cache thrashing low, needles bigger than 255 bytes are uncommon anyways.
The worst case is still O(n*m) but we do a lot better on the average case now.
llvm-svn: 142061
2011-10-15 10:08:31 +00:00
ebe13bc3f1
Move the legalization of vector loads and stores into LegalizeVectorOps. In some
...
cases we need the second type-legalization pass in order to support all cases.
llvm-svn: 142060
2011-10-15 07:41:10 +00:00
fd4ca0f4ac
Fix SCEVExpander assert during LSR: "argument of incompatible type".
...
Just because we're dealing with a GEP doesn't mean we can assert the
SCEV has a pointer type. The fix is simply to ignore the SCEV pointer
type, which we really didn't need.
Fixes PR11138 webkit crash.
llvm-svn: 142058
2011-10-15 06:19:55 +00:00
ea97a05fc5
Revert r142046, "Fix for llvm::sys::getHostTriple on Windows. Instead of relying on the triple"
...
It extremely breaks builds when optimization is enabled. Twine should not hold temporary objects.
By the way, I might feel sad if I saw "i786-" "i1586-" or "iF86-".
llvm-svn: 142055
2011-10-15 04:29:36 +00:00
559b8f2ae9
Fix for llvm::sys::getHostTriple on Windows. Instead of relying on the triple
...
from config.h, it discovers the triple based on the execution environment.
Patch by Aaron Ballman <aaron@aaronballman.com>
llvm-svn: 142046
2011-10-15 02:10:06 +00:00
7bc976a8ef
Windows/Memory.inc: Support the ability to allocate memory "near" another block of memory on Win32. It has fixed FIXME.
...
Thanks to Aaron Ballman!
llvm-svn: 142039
2011-10-15 01:58:16 +00:00
d50861c831
Fix indvars randomness by removing iteration over a map.
...
I rewrote the algorithm a while back so it doesn't require map lookup,
but neglected to change the data structure. This was caught by
llvm-gcc self host, not because there's anything special about
llvm-gcc, but because it is the only test for nondeterminism we
currently have. Unit tests don't work well for everything; we should
always try to have a nondeterminism stress test running.
Fixes PR11133: llvm-gcc self host .o mismatch after enable-iv-rewrite=false
llvm-svn: 142036
2011-10-15 01:38:14 +00:00
2730a0099a
Clear out the landing pad to call site map for each function.
...
This isn't put into the 'clear()' method because the information needs to stick
around (at least for a little bit) after the selection DAG is built.
llvm-svn: 142032
2011-10-15 01:00:26 +00:00
dd2b39d989
Mark tADDrSPi as having side effects again.
...
It really doesn't, but when r141929 removed the hasSideEffects flag from
this instruction, it caused miscompilations. I am guessing that it got
moved across a stack pointer update.
Also clear isRematerializable after checking that this instruction is
in fact never rematerialized in the nightly test suite.
llvm-svn: 142030
2011-10-15 00:57:13 +00:00
1809d6c0d5
Thumb1 does not support dynamic stack realignment.
...
rdar://10288916 is tracking this fix.
In the past, instcombine and other passes were promoting alloca alignment past
the natural alignment, resulting in dynamic stack realignment. Lang's work now
prevents this from happening (LLVM commit r141599). Now that this really
shouldn't happen report a fatal error rather than silently generate bad code.
llvm-svn: 142028
2011-10-15 00:28:24 +00:00
9c1019c6c7
Mark registers as DEAD because they're really just clobbers.
...
llvm-svn: 142027
2011-10-15 00:27:44 +00:00
74d1da5a05
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
...
llvm-svn: 142022
2011-10-14 23:58:49 +00:00
9e0cd1ee17
Make sure that the register is in the register class before adding it as a machine op.
...
llvm-svn: 142021
2011-10-14 23:55:44 +00:00
6f3f9a391e
Mark the invoke call instruction as implicitly defining the callee-saved registers.
...
The callee-saved registers cannot be live across an invoke call because the
control flow may continue along the exceptional edge. When this happens, all of
the callee-saved registers are no longer valid.
llvm-svn: 142018
2011-10-14 23:34:37 +00:00
8a038652f2
constify array itself, don't iterate multiple times.
...
llvm-svn: 142013
2011-10-14 22:50:21 +00:00
ea166d44e7
Allow the source module to be materialized during the linking process.
...
llvm-svn: 142010
2011-10-14 22:17:46 +00:00
8b478360ef
Fix a non-firing assert. Change:
...
assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
llvm-svn: 142000
2011-10-14 20:50:26 +00:00
ab6158e2e3
ocaml bindings: add getopcode for constant and instruction, and int64_of_const.
...
llvm-svn: 141990
2011-10-14 20:37:49 +00:00
2e9affec15
bindings: tab and indentation fixes of my previous commits
...
llvm-svn: 141989
2011-10-14 20:37:42 +00:00
06fdaeb5d9
A few 80-col violations.
...
llvm-svn: 141988
2011-10-14 20:36:23 +00:00
4a49dee221
Disable code/data region symbols on ELF targets, where different mapping symbols are used for ARM/Thumb mode code. This should only be re-enabled once we have a solution to properly distinguish these.
...
llvm-svn: 141984
2011-10-14 20:28:57 +00:00
450128a68c
Add an implementation of the CanLowerReturn function to the PPC backend
...
llvm-svn: 141981
2011-10-14 19:51:36 +00:00
44419bfd54
Add f128 to datalayout string.
...
llvm-svn: 141978
2011-10-14 19:14:50 +00:00
4903379088
initial test commit (remove whitespace)
...
llvm-svn: 141972
2011-10-14 18:54:13 +00:00
06b6ccfe90
Update live-in lists when splitting critical edges.
...
Fixes PR10814. Patch by Jan Sjödin!
llvm-svn: 141960
2011-10-14 17:25:46 +00:00
62b34a65f9
Revert r141932, r141936 and r141937.
...
llvm-svn: 141959
2011-10-14 17:16:39 +00:00
400907cc41
Fix typo. "__sync_fetch_and-xor_4" should be "__sync_fetch_and_xor_4".
...
Pointed out by George Russell.
llvm-svn: 141956
2011-10-14 15:53:48 +00:00
a447e0f38f
An instruction's operands aren't necessarily instructions or constants. They
...
could be arguments, for example.
No testcase because this is a bug-fix broken out of a larger optimization patch.
llvm-svn: 141951
2011-10-14 09:38:46 +00:00
965de2c197
Add X86 ANDN instruction. Including instruction selection.
...
llvm-svn: 141947
2011-10-14 07:06:56 +00:00
3657fe4b17
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141939
2011-10-14 03:21:46 +00:00
d9ea7c8c31
Definition of function getMipsRegisterNumbering.
...
Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141938
2011-10-14 03:04:24 +00:00
1742a2c093
Add definition of class MipsELFWriterInfo.
...
Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141937
2011-10-14 02:55:47 +00:00
0fc7d7af5a
Add missing relocation types.
...
Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141936
2011-10-14 02:47:50 +00:00
769fc971b4
Fixup enumerations.
...
Patch by Jack Carter at Mips.
llvm-svn: 141934
2011-10-14 02:38:56 +00:00
4e2bfe0770
Add more Mips relocation types.
...
Patch by Jack Carter at Mips.
llvm-svn: 141932
2011-10-14 02:17:30 +00:00
d9444d455e
Ban rematerializable instructions with side effects.
...
TableGen infers unmodeled side effects on instructions without a
pattern. Fix some instruction definitions where that was overlooked.
Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.
llvm-svn: 141929
2011-10-14 01:00:49 +00:00
eafa9d50c2
V_SET0 has no side effects.
...
TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.
This was part of the cause for PR11125, but the real bug was fixed
in r141923.
llvm-svn: 141924
2011-10-14 00:39:50 +00:00
7fb5632e73
Add value numbers when spilling dead defs.
...
When spilling around an instruction with a dead def, remember to add a
value number for the def.
The missing value number wouldn't normally create problems since there
would be an incoming live range as well. However, due to another bug
we could spill a dead V_SET0 instruction which doesn't read any values.
The missing value number caused an empty live range to be created which
is dangerous since it doesn't interfere with anything.
This fixes part of PR11125.
llvm-svn: 141923
2011-10-14 00:34:31 +00:00
b46345d7c1
Avoid undefined behavior in negation in LSR. Patch by Ahmed Charles.
...
Someone more familiar with LSR should double-check that the extra cast is actually doing the right thing in the overflow cases; I'm not completely confident that's that case.
llvm-svn: 141916
2011-10-13 23:48:33 +00:00
a7ad9f3932
Fix undefined shift. Patch by Ahmed Charles.
...
llvm-svn: 141914
2011-10-13 23:36:06 +00:00
a5abd03a8d
Simplify assertion, and avoid undefined shift. Based on patch by Ahmed Charles.
...
llvm-svn: 141912
2011-10-13 23:27:48 +00:00
a7a90bfdab
Support/Windows: Add support modifying memory permissions on Windows. Patch by Aaron Ballman!
...
llvm-svn: 141910
2011-10-13 23:16:01 +00:00
92734d6f46
Fix undefined shifts and abs in Alpha backend. Based on patch by Ahmed Charles.
...
llvm-svn: 141909
2011-10-13 23:13:35 +00:00
0084615924
Support/Windows: Add efficent RW mutex on Windows. Patch by Aaron Ballman!
...
llvm-svn: 141907
2011-10-13 23:10:56 +00:00
53ba208c72
Avoid undefined behavior in signed integer negation. Patch by Ahmed Charles.
...
llvm-svn: 141905
2011-10-13 22:49:56 +00:00
aa6ec39056
Simplify and avoid undefined shift. Based on patch by Ahmed Charles.
...
llvm-svn: 141903
2011-10-13 22:40:23 +00:00
834bd602e6
ELF: Fix the section that relocations apply to. Add test to verify. Patch by Danil Malyshev!
...
llvm-svn: 141901
2011-10-13 22:30:10 +00:00
c1702c8f22
Enhance the memdep interface so that users can tell the difference between a dependency which cannot be calculated and a path reaching the entry point of the function. This patch introduces isNonFuncLocal, which replaces isUnknown in some cases.
...
Patch by Xiaoyi Guo.
llvm-svn: 141896
2011-10-13 22:14:57 +00:00
870c1a3f15
Reapply r141870, SCEV expansion of post-inc.
...
Speculatively reapply to see if this test case still crashes on
linux. I may have fixed it in my last checkin.
llvm-svn: 141895
2011-10-13 21:55:29 +00:00
76933f4c0b
Don't forget to reconstruct D after changing the scope that we're
...
looking at.
llvm-svn: 141892
2011-10-13 21:43:44 +00:00
9a28851e52
COFF: Implement sectionContainsSymbol for relocatable files only.
...
llvm-svn: 141884
2011-10-13 20:36:54 +00:00
7e442569dc
Fix memory corruption I introduced a few checkins ago.
...
Self-review easily caught this obvious bug.
llvm-svn: 141880
2011-10-13 18:49:23 +00:00
44f76eafae
SETEND is not allowed in an IT block.
...
llvm-svn: 141874
2011-10-13 17:58:39 +00:00
41c253c35c
Revert r141870. The test case crashes on linux with data corruption. A deeper issue was exposed.
...
llvm-svn: 141873
2011-10-13 17:58:24 +00:00
e15d6e14e3
LSR: Reuse the post-inc expansion of expressions.
...
This avoids unnecessary expansion of expressions and allows the SCEV
expander to work on expression DAGs, not just trees.
Fixes PR11090.
llvm-svn: 141870
2011-10-13 17:31:47 +00:00
1393ec29af
SCEV: Rewrite TrandformForPostIncUse to handle expression DAGs, not
...
just expression trees.
Partially fixes PR11090. Test case will be with the full fix.
llvm-svn: 141868
2011-10-13 17:21:09 +00:00
adfe72b33c
Slightly more useful tracing.
...
llvm-svn: 141867
2011-10-13 17:06:38 +00:00
3815de8d50
Mark 'branch indirect' instruction as an indirect branch.
...
Not having it confused assembly printing of jumptables.
llvm-svn: 141862
2011-10-13 11:40:03 +00:00
25f6d3e321
More closely follow libgcc, which has code after the `ret' instruction to
...
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.
llvm-svn: 141859
2011-10-13 08:24:19 +00:00
063f55ffdd
Revert r141854 because it was causing failures:
...
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
22a690e3db
Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.
...
llvm-svn: 141856
2011-10-13 07:42:32 +00:00
86f7d3556c
Use an existing method.
...
llvm-svn: 141855
2011-10-13 07:36:41 +00:00
8cc9388073
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141854
2011-10-13 07:09:14 +00:00
2fdcb1f045
Add 'implicit EFLAGS' to patterns for popcnt and lzcnt
...
llvm-svn: 141853
2011-10-13 06:18:52 +00:00
d3043965b9
Elf_Word is not POD! Stop using it in a DenseMap.
...
llvm-svn: 141851
2011-10-13 03:30:21 +00:00
594a545821
If MI is deleted then remove it from the set. If a new MI is created, it could
...
have the same address as the one we deleted, and we don't want that in the set
yet. Noticed by inspection.
llvm-svn: 141849
2011-10-13 02:16:18 +00:00
404feb9973
Tabs to spaces.
...
llvm-svn: 141844
2011-10-13 01:09:50 +00:00
8488225984
Add missing braces to pacify GCC's -Wparentheses.
...
llvm-svn: 141842
2011-10-13 00:54:59 +00:00
068dc91de9
Also inflate register classes around inline asm.
...
Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.
This fixes PR11078.
llvm-svn: 141836
2011-10-12 23:37:40 +00:00
35b362fab2
Add MachineInstr::getRegClassConstraint().
...
Most instructions have some requirements for their register operands.
Usually, this is expressed as register class constraints in the
MCInstrDesc, but for inline assembly the constraints are encoded in the
flag words.
llvm-svn: 141835
2011-10-12 23:37:36 +00:00
1e73716eae
Extract a method for finding the inline asm flag operand.
...
llvm-svn: 141834
2011-10-12 23:37:33 +00:00
24abd9d9b6
Encode register class constreaints in inline asm instructions.
...
The inline asm operand constraint is initially encoded in the virtual
register for the operand, but that register class may change during
coalescing, and the original constraint is lost.
Encode the original register class as part of the flag word for each
inline asm operand. This makes it possible to recover the actual
constraint required by inline asm, just like we can for normal
instructions.
llvm-svn: 141833
2011-10-12 23:37:29 +00:00
Hal Finkel