Commit Graph

2131 Commits

Author SHA1 Message Date
Oscar Fuentes f4202ba475 Changes for building Clang and others using LLVM as an external
library.

Installs tblgen (required by Clang).

Translates handling of user settings and platform-dependant options to
its own file, where it can included by another project.

Installs the .cmake files required by projects like Clang.

llvm-svn: 124816
2011-02-03 20:57:36 +00:00
Kevin Enderby 96f6e379e2 Changed the TableGen created MatchInstructionImpl() setting of ErrorInfo.
The algorithm for identifying which operand is invalid will now always point to
some operand and not the mnemonic sometimes.  The change is now that ErrorInfo
is the index of the highest operand that does not match for any of the matching
mnemonics records.  And no longer the ~0U value when the mnemonic matches and
not every record with a matching mnemonic has the same mismatching operand
index.

llvm-svn: 124734
2011-02-02 18:20:55 +00:00
David Greene 433c6180ab [AVX] Implement EnforceSmallerThan for mixed int/fp type lists. This
makes type checking for extract_subvector and insert_subvector more
robust and will allow stricter typechecking of more patterns in the
future.

This change handles int and fp as disjoint sets so that it will
enforce integer types to be smaller than the largest integer type and
fp types to be smaller than the largest fp type.  There is no attempt
to check type sizes across the int/fp sets.

llvm-svn: 124672
2011-02-01 19:12:32 +00:00
Bob Wilson f9bab3a47a Fix a comment typo.
llvm-svn: 124450
2011-01-27 23:08:52 +00:00
Douglas Gregor dd02d62594 Clang: separate the access-control diagnostics from other diagnostics that do not have SFINAE behavior.
llvm-svn: 124440
2011-01-27 21:06:17 +00:00
Bob Wilson 770681d7b6 Add a MnemonicIsValid method to the asm matcher.
Patch by Bill Wendling.

llvm-svn: 124328
2011-01-26 21:43:46 +00:00
Bob Wilson 2c1562ebd3 Fix spelling of CouldMatchAmbiguouslyWith method name.
llvm-svn: 124324
2011-01-26 21:26:21 +00:00
Bob Wilson f4ee9e515c Whitespace and 80-column fixes.
llvm-svn: 124323
2011-01-26 21:26:19 +00:00
Bob Wilson b9b2422e89 Improve the AsmMatcher's ability to handle suboperands.
When an operand class is defined with MIOperandInfo set to a list of
suboperands, the AsmMatcher has so far required that operand to also define
a custom ParserMatchClass, and InstAlias patterns have not been able to
set the individual suboperands separately.  This patch removes both of those
restrictions.  If a "compound" operand does not override the default
ParserMatchClass, then the AsmMatcher will now parse its suboperands
separately.  If an InstAlias operand has the same class as the corresponding
compound operand, then it will be handled as before; but if that check fails,
TableGen will now try to match up a sequence of InstAlias operands with the
corresponding suboperands.

llvm-svn: 124314
2011-01-26 19:44:55 +00:00
NAKAMURA Takumi 31aafbd501 TableGen: PointerLikeRegClass can be accepted to operand.
llvm-svn: 124271
2011-01-26 02:03:48 +00:00
NAKAMURA Takumi 9d29eff198 Fix whitespace.
llvm-svn: 124270
2011-01-26 02:03:37 +00:00
Daniel Dunbar 83381d001b tblgen/AsmMatcherEmitter: Fix alias handling to honor -match-prefix.
llvm-svn: 124154
2011-01-24 23:26:31 +00:00
David Greene 127fd1d540 [AVX] Add type checking support for vector/subvector type constraints.
This will be used to check patterns referencing a forthcoming
INSERT_SUBVECTOR SDNode.  INSERT_SUBVECTOR in turn is very useful for
matching to VINSERTF128 instructions and complements the already
existing EXTRACT_SUBVECTOR SDNode.

llvm-svn: 124145
2011-01-24 20:53:18 +00:00
Bill Wendling a01ea89fb6 ARM uses '.' in their tokens. Give it a name instead of a numeric value.
llvm-svn: 124026
2011-01-22 09:44:32 +00:00
Peter Collingbourne 4fbd74ba02 tblgen: Add support for non-inheritable attributes
This patch makes the necessary changes to TableGen to support
non-inheritable attributes.

llvm-svn: 123958
2011-01-21 02:08:26 +00:00
Bob Wilson a48eacc0b6 Move InstAlias check of argument types to a separate loop.
llvm-svn: 123934
2011-01-20 18:38:10 +00:00
Bob Wilson 266d2ba124 Tidy comment.
llvm-svn: 123933
2011-01-20 18:38:07 +00:00
Bob Wilson 81aafcc374 Fix broken check for InstAlias argument used with different types.
llvm-svn: 123932
2011-01-20 18:38:05 +00:00
Bob Wilson f3f2835b01 Precompute InstAlias operand mapping to result instruction operand indices.
There should be no functional change from this, but I think it's simpler this
way.

llvm-svn: 123931
2011-01-20 18:38:02 +00:00
Douglas Gregor eb6561e81d Fix comment for gen-clang-decl-nodes tblgen backend, from Michael Han
llvm-svn: 123833
2011-01-19 15:57:47 +00:00
Owen Anderson dac7a0174e When matching asm operands, always try to match the most restricted type first.
Unfortunately, while this is the "right" thing to do, it breaks some ARM
asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous.  This
is tricky to resolve since neither is a subset of the other.

XFAIL the test for now.  The old way was broken in other ways, just ways
we didn't happen to be testing, and our ARM asm parsing is going to require
significant revisiting at a later point anyways.

llvm-svn: 123786
2011-01-18 23:01:21 +00:00
Bruno Cardoso Lopes 7f639c11d7 Add support for parsing and encoding ARM's official syntax for the BFI instruction
llvm-svn: 123770
2011-01-18 20:45:56 +00:00
Daniel Dunbar e46bc4cec5 Formatting tweak.
llvm-svn: 123718
2011-01-18 01:59:30 +00:00
Bob Wilson 03912aba9a Fix some tablegen issues to allow using zero_reg for InstAlias definitions.
This is needed to allow an InstAlias for an instruction with an "OptionalDef"
result register (like ARM's cc_out) where you want to set the optional register
to reg0.

llvm-svn: 123490
2011-01-14 22:58:09 +00:00
Owen Anderson c3c7f5dd56 Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting
the symbolic immediate names used for these instructions, fixing their pretty-printers, and
adding proper encoding information for them.

With this, we can properly pretty-print and encode assembly like:
	mrc p15, , r3, c13, c0, 

Fixes <rdar://problem/8857858>.

llvm-svn: 123404
2011-01-13 21:46:02 +00:00
Evan Cheng 965b3c7323 Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.

llvm-svn: 123369
2011-01-13 07:58:56 +00:00
Daniel Dunbar 4035383937 MC/AsmMatcher: Fix indirect 80-col viola.
llvm-svn: 123174
2011-01-10 15:26:11 +00:00
Bob Wilson 006089b761 Use __builtin_shufflevector to implement vget_low and vget_high intrinsics.
This was suggested by Edmund Grimley Evans in pr8411.

llvm-svn: 123043
2011-01-07 23:40:49 +00:00
David Greene 2f7cf7fcb4 Rename lisp-like functions as suggested by Gabor Greif as loooong time
ago.  This is both easier to learn and easier to read.

llvm-svn: 123001
2011-01-07 17:05:37 +00:00
Jim Grosbach 50986b5d39 Trailing whitespace.
llvm-svn: 122542
2010-12-24 05:06:32 +00:00
Chris Lattner 2a0a3b43d7 Flag -> Glue, the ongoing saga
llvm-svn: 122513
2010-12-23 18:28:41 +00:00
Chris Lattner 11a33811b6 flags -> glue for selectiondag
llvm-svn: 122509
2010-12-23 17:24:32 +00:00
Chris Lattner f647e95b9a sdisel flag -> glue.
llvm-svn: 122507
2010-12-23 17:13:18 +00:00
Chris Lattner f7f9e8c978 continue renaming flag -> glue.
llvm-svn: 122506
2010-12-23 17:03:20 +00:00
Jeffrey Yasskin 9b43f33620 Change all self assignments X=X to (void)X, so that we can turn on a
new gcc warning that complains on self-assignments and
self-initializations.

llvm-svn: 122458
2010-12-23 00:58:24 +00:00
Jim Grosbach 65586fea71 Tidy up a bit. Trailing whitespace, hard tabs and 80-columns.
llvm-svn: 122337
2010-12-21 16:16:00 +00:00
Chris Lattner 3e5fbd74ed rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310
2010-12-21 02:38:05 +00:00
Bob Wilson def12f3be1 Neon intrinsic tests need to be compiled for Cortex-A9 for f16 support.
llvm-svn: 122015
2010-12-17 01:21:03 +00:00
Michael J. Spencer 39a0ffc394 MemoryBuffer now return an error_code and returns a OwningPtr<MemoryBuffer> via an out parm.
llvm-svn: 121958
2010-12-16 03:29:14 +00:00
Bob Wilson d7f8bd1c14 Teach the Neon intrinsic generator to widen half-precision float types.
This isn't currently used for anything but I ran into it when experimenting
with some changes, and it might be useful in the future.

llvm-svn: 121911
2010-12-15 23:16:25 +00:00
Bob Wilson 9168a4f1c2 Add a Neon intrinsic test generator.
This is still a WIP.  It's already good enough to expose a few bugs, though.

llvm-svn: 121868
2010-12-15 16:58:45 +00:00
Bob Wilson 276f1ca897 Fix Neon intrinsic immediate range checking for some double-register operands.
Some quad-register intrinsics with lane operands only take a double-register
operand for the vector containing the lane.  The valid range of lane numbers
is then half as big as you would expect from the quad-register type.
Note: This currently has no effect because those intrinsics are now handled
entirely in the header file using __builtin_shufflevector, which does its own
range checking, but I want to use this for generating tests.

llvm-svn: 121867
2010-12-15 16:58:42 +00:00
Chris Lattner 89dcb687bc various cleanups to tblgen, patch by Garrison Venn!
llvm-svn: 121837
2010-12-15 04:48:22 +00:00
Mikhail Glushenkov 9f9b7051c7 llvmc: make switch options ZeroOrMore by default.
llvm-svn: 121822
2010-12-15 01:21:59 +00:00
Jakob Stoklund Olesen 757f0e37ea Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of all
registers that alias Reg, including itself. This is almost the same as the
existing getAliasSet() method, except for the inclusion of Reg.

The name matches the reflexive TRI::regsOverlap(x, y) relation.

It is very common to do stuff to a register and all its aliases:

  stuff(Reg)
  for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
    stuff(*Alias);

That can now be written as the simpler:

  for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias)
    stuff(*Alias);

This change requires a bit more constant space for the alias lists because Reg
is included and because the empty alias list cannot be shared any longer.

If the getAliasSet method is eventually removed, this space can be reclaimed by
sharing overlap lists. For instance, %rax and %eax have identical overlap sets.

llvm-svn: 121800
2010-12-14 23:03:42 +00:00
Jim Grosbach 509dc2a700 Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
llvm-svn: 121798
2010-12-14 22:28:03 +00:00
Bill Wendling 092a7bdf9f The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747
2010-12-14 03:36:38 +00:00
Owen Anderson 6d375e5637 Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
process cleaner.

llvm-svn: 121735
2010-12-14 00:36:49 +00:00
Bob Wilson 651eaa02b8 Remove the rest of the *_sfp Neon instruction patterns.
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

llvm-svn: 121730
2010-12-13 23:02:37 +00:00
Owen Anderson 9a4d42855d Revert r121721, which broke buildbots.
llvm-svn: 121726
2010-12-13 22:51:08 +00:00