b14f4fd0de
[Hexagon] Add handling fixups and instruction relaxation
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llvm-svn: 263981
2016-03-21 20:27:17 +00:00
c6f1e1a709
[Hexagon] Properly encode registers in duplex instructions
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llvm-svn: 263980
2016-03-21 20:13:33 +00:00
ab9eca4d9f
[Hexagon] As a size optimization, not lazy extending TPREL or DTPREL variants since they're usually in range.
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llvm-svn: 262258
2016-02-29 21:21:56 +00:00
ecef1d9cbc
[Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding.
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The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes.
Another way is to put a .word32 and mix code and data within a function. The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware.
This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits. Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register.
llvm-svn: 261006
2016-02-16 20:38:17 +00:00
d8a985ec7c
[llvm-readobj] Option to emit readelf like output
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New option --elf-output-style=LLVM or GNU
Enables -file-headers in readelf style when elf-output-style=GNU
Differential revision: http://reviews.llvm.org/D14128
llvm-svn: 260430
2016-02-10 20:40:55 +00:00
f46c92fe52
Revert "[llvm-readobj] Option to emit readelf like output"
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This reverts commit a58765909660a7195b32e0cc8c7476168b913750.
llvm-svn: 260397
2016-02-10 18:21:01 +00:00
4f2ca0d268
[llvm-readobj] Option to emit readelf like output
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New option --elf-output-style=LLVM or GNU
Enables -file-headers in readelf style when elf-output-style=GNU
Differential revision: http://reviews.llvm.org/D14128
llvm-svn: 260391
2016-02-10 17:51:28 +00:00
1c79d9be6e
[Hexagon] Fixing relocation generation and adding tests.
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llvm-svn: 260259
2016-02-09 19:18:02 +00:00
227b928abc
Fix several accidental DOS line endings in source files
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Summary:
There are a number of files in the tree which have been accidentally checked in with DOS line endings. Convert these to native line endings.
There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those.
Reviewers: joerg, aaron.ballman
Subscribers: aaron.ballman, sanjoy, dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D15848
llvm-svn: 256707
2016-01-03 17:22:03 +00:00
21dc8bdd9e
[Hexagon] Add PIC support
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llvm-svn: 256025
2015-12-18 20:19:30 +00:00
15ca65c253
[Hexagon] Adding shuffling resources for HVX instructions and tests for instruction encodings.
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llvm-svn: 254652
2015-12-03 21:44:28 +00:00
fa5558307b
[Hexagon] NFC. Adding a number of packet correctness tests.
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llvm-svn: 253000
2015-11-13 01:46:06 +00:00
8bb168b160
[Hexagon] Adding relaxation functionality to backend and test.
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llvm-svn: 252989
2015-11-13 01:12:25 +00:00
7a92c6ecbb
[Hexagon] Adding checks for values out of operand range and correct new-value producer usage.
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llvm-svn: 252969
2015-11-12 23:28:01 +00:00
a1fa71ead9
[Hexagon] Adding test to make sure labels and register pairs are correctly parsed.
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llvm-svn: 252968
2015-11-12 22:54:14 +00:00
3c7ecf9af1
[Hexagon] Adding instruction aliases and tests.
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llvm-svn: 252579
2015-11-10 01:58:26 +00:00
13cc3ab785
[Hexagon] Fixing compound register printing and reenabling more tests.
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llvm-svn: 252574
2015-11-10 00:51:56 +00:00
b7a5f9fc29
[Hexagon] Fixing store instructions and reenabling a few more tests.
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llvm-svn: 252561
2015-11-10 00:22:00 +00:00
8ab7e8e1b5
[Hexagon] Fixing load instruction parsing and reenabling tests.
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llvm-svn: 252555
2015-11-10 00:02:27 +00:00
7cd0892729
[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission.
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llvm-svn: 252443
2015-11-09 04:07:48 +00:00
a7c5f0409c
[Hexagon] Split double registers
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llvm-svn: 250549
2015-10-16 20:38:54 +00:00
be8c453d58
[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.
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llvm-svn: 239161
2015-06-05 16:00:11 +00:00
68d967d92e
[Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch.
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llvm-svn: 238556
2015-05-29 14:44:13 +00:00
c05dff1792
Expand MUX instructions early on Hexagon
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This time with all files included.
llvm-svn: 233696
2015-03-31 13:35:12 +00:00
8c4fd2bdeb
Revert 233694. Weak SVN-fu.
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llvm-svn: 233695
2015-03-31 13:32:32 +00:00
261d62c862
Expand MUX instructions early on Hexagon
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llvm-svn: 233694
2015-03-31 13:29:17 +00:00
30dcb232b0
[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.
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llvm-svn: 223800
2014-12-09 18:16:49 +00:00
6e0f9f8d61
[Hexagon] Adding cmp* immediate form instructions.
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llvm-svn: 222849
2014-11-26 19:43:12 +00:00
31abe33726
[Hexagon] Adding and64, or64, and xor64 instructions.
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llvm-svn: 222846
2014-11-26 18:55:59 +00:00
b3d08bb44b
[Hexagon] Adding add64 and sub64 instructions.
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llvm-svn: 222795
2014-11-25 22:15:44 +00:00
6f6c4ff1fc
Reverting 222792
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llvm-svn: 222793
2014-11-25 21:39:57 +00:00
aaf33928ee
[Hexagon] Adding compare with immediate instructions.
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llvm-svn: 222792
2014-11-25 21:30:28 +00:00
f7f156ffc3
[Hexagon] [NFC] Adding trailing whitespace to test files.
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llvm-svn: 222785
2014-11-25 20:22:24 +00:00
e83bc7476f
[Hexagon] Adding C2_mux instruction.
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llvm-svn: 222784
2014-11-25 20:20:09 +00:00
902157c249
[Hexagon] Replacing cmp* instructions with ones that contain encoding bits.
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llvm-svn: 222771
2014-11-25 18:20:52 +00:00
397a25e7cd
[Hexagon] Adding asrh instruction, removing unused multiclasses.
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llvm-svn: 222670
2014-11-24 18:04:42 +00:00
3b3197ef95
[Hexagon] Adding aslh instruction.
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llvm-svn: 222668
2014-11-24 17:44:19 +00:00
098256c5e6
[Hexagon] Adding zxth instruction.
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llvm-svn: 222662
2014-11-24 17:11:34 +00:00
bb7d6f5514
[Hexagon] Adding zxtb instruction.
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llvm-svn: 222660
2014-11-24 16:48:43 +00:00
310991c66f
[Hexagon] Adding sxth instruction.
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llvm-svn: 222577
2014-11-21 21:54:59 +00:00
91ffec908f
[Hexagon] Adding sxtb instruction. Renaming some identically named classes that will be removed after converting referencing defs.
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llvm-svn: 222575
2014-11-21 21:35:52 +00:00
ac00643603
[Hexagon] Adding A2_xor instruction with IR selection pattern and test.
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llvm-svn: 222399
2014-11-19 23:22:23 +00:00
21866546ae
[Hexagon] Adding A2_or instruction with IR selection pattern and test.
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llvm-svn: 222396
2014-11-19 22:58:04 +00:00
44fd1c8bdf
[Hexagon] Adding A2_and instruction.
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llvm-svn: 222274
2014-11-18 22:45:47 +00:00
38765e6d89
[Hexagon] Adding A2_sub instruction
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Renaming test files.
llvm-svn: 222263
2014-11-18 21:51:51 +00:00
efa74e0280
[Hexagon] Converting from ADD_rr to A2_add which has encoding bits.
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Adding test to show correct instruction selection and encoding.
llvm-svn: 222249
2014-11-18 20:28:11 +00:00
2c769209a1
[Hexagon] Adding basic Hexagon ELF object emitter.
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llvm-svn: 221465
2014-11-06 17:05:51 +00:00
9a103563f4
reverting r209132
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llvm-svn: 209139
2014-05-19 16:22:11 +00:00
daeb25d4e0
Hexagon: Add encoding bits to the mpy instructions.
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llvm-svn: 209132
2014-05-19 15:32:07 +00:00
Krzysztof Parzyszek