Commit Graph

84 Commits

Author SHA1 Message Date
Hsiangkai Wang 5158cfef8b [RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR.
Previous patch only reverts C builtins for tail policy. In order to keep
LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 19:41:49 +08:00
Hsiangkai Wang 7ccd31c900 Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics."
This reverts commit 7afa61e718.
2021-10-13 19:41:48 +08:00
Hsiangkai Wang ff3ed78304 Revert "[RISCV] Define _m intrinsics as builtins, instead of macros."
This reverts commit 97f0c63783.

As discussed in https://reviews.llvm.org/D110684, it increased the
compile time and the binary size of clang more than 1%. I reverted
this patch first to think about a better way to do it.
2021-10-13 12:21:51 +08:00
jacquesguan 0608bbd4e8 [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change
Rename vfredsum and vfwredsum to vfredusum and vfwredusum. Add aliases for vfredsum and vfwredsum.

Reviewed By: luismarques, HsiangKai, khchen, frasercrmck, kito-cheng, craig.topper

Differential Revision: https://reviews.llvm.org/D105690
2021-10-12 06:46:46 +00:00
Hsiangkai Wang 97f0c63783 [RISCV] Define _m intrinsics as builtins, instead of macros.
In the original design, we levarage _mt intrinsics to define macros for
_m intrinsics. Such as,

```
__builtin_rvv_vadd_vv_i8m1_mt((vbool8_t)(op0), (vint8m1_t)(op1), (vint8m1_t)(op2), (vint8m1_t)(op3), (size_t)(op4), (size_t)VE_TAIL_AGNOSTIC)
```

However, we could not define generic interface for mask intrinsics any
more due to clang_builtin_alias only accepts clang builtins as its
argument.

In the example,

```
 __rvv_overloaded
 __attribute__((clang_builtin_alias(__builtin_rvv_vadd_vv_i8m1_mt)))
  vint8m1_t vadd(vbool8_t op0, vint8m1_t op1, vint8m1_t op2, vint8m1_t
  op3, size_t op4, size_t op5);
```

op5 is the tail policy argument. When users want to use vadd generic
interface for masked vector add, they need to specify tail policy in the
previous design. In this patch, we define _m intrinsics as clang
builtins to solve the problem.

Differential Revision: https://reviews.llvm.org/D110684
2021-10-12 10:47:55 +08:00
Hsiangkai Wang 80a6456306 [RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.
vle1.v  -> vlm.v
vse1.v  -> vsm.v

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106044
2021-10-05 21:49:54 +08:00
Hsiangkai Wang c274384cff [NFC][RISCV] Update test cases through update_cc_test_checks.py. 2021-10-03 15:44:06 +08:00
Hsiangkai Wang 7afa61e718 [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.
Add the tail policy argument to Clang builtins. There
are two policies for tail elements. Tail agnostic means users do not
care about the values in the tail elements and tail undisturbed means
the values in the tail elements need to be kept after the operation. In
order to let users control the tail policy, we add an additional
argument at the end of the argument list.

For unmasked operations, we have no maskedoff and the tail policy is
always tail agnostic. If users want to keep tail elements under unmasked
operations, they could use all one mask in the masked operations to do
it. So, we only add the additional argument for masked operations for
most cases. There are exceptions listed below.

In this patch, we do not handle the following cases to reduce the
complexity of the patch. There could be two separate patches for them.

Use dest argument to control tail policy
vmerge.vvm/vmerge.vxm/vmerge.vim (add _t builtins with additional dest
argument)
vfmerge.vfm (add _t builtins with additional dest argument)
vmv.v.v (add _t builtins with additional dest argument)
vmv.v.x (add _t builtins with additional dest argument)
vmv.v.i (add _t builtins with additional dest argument)
vfmv.v.f (add _t builtins with additional dest argument)
vadc.vvm/vadc.vxm/vadc.vim (add _t builtins with additional dest
argument)
vsbc.vvm/vsbc.vxm (add _t builtins with additional dest argument)

Always has tail argument for masked/unmasked intrinsics
Vector Single-Width Integer Multiply-Add Instructions (add _t and _mt
builtins)
Vector Widening Integer Multiply-Add Instructions (add _t and _mt
builtins)
Vector Single-Width Floating-Point Fused Multiply-Add Instructions (add
_t and _mt builtins)
Vector Widening Floating-Point Fused Multiply-Add Instructions (add _t
and _mt builtins)
Vector Reduction Operations (add _t and _mt builtins)
Vector Slideup Instructions (add _t and _mt builtins)
Vector Slidedown Instructions (add _t and _mt builtins)

Discussion: https://github.com/riscv/rvv-intrinsic-doc/pull/101

Differential Revision: https://reviews.llvm.org/D109322
2021-09-24 17:09:50 +08:00
Shao-Ce SUN 1d8bbafed2 [RISCV][NFC] Fix clang test for vloxei/vluxei 2021-09-22 11:27:41 +08:00
Shao-Ce SUN e247fed23b [RISCV] add Half-precision test for clang
and deleted useless lines.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D109799
2021-09-22 11:06:57 +08:00
Shao-Ce SUN a83eda591c [RISCV][NFC] Deleted useless lines in clang tests. 2021-09-22 10:25:57 +08:00
Shao-Ce Sun d4f25d0046 [RISCV] add Half-precision test for vle/vse
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D109681
2021-09-14 08:55:22 +08:00
Hsiangkai Wang 5f996705e0 [RISCV] Half-precision for vget/vset.
Differential Revision: https://reviews.llvm.org/D107433
2021-08-09 17:38:15 +08:00
Hsiangkai Wang 8b33839f01 [RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR.
Differential Revision: https://reviews.llvm.org/D107139
2021-08-01 05:58:17 +08:00
Hsiangkai Wang 698f288fa1 [Clang][RISCV] Implement vsoxseg and vsuxseg.
Differential Revision: https://reviews.llvm.org/D103873
2021-07-22 09:24:41 +08:00
Hsiangkai Wang 915e6dc09c [Clang][RISCV] Implement vssseg.
Differential Revision: https://reviews.llvm.org/D103872
2021-07-22 09:24:40 +08:00
Hsiangkai Wang d1a401b35b [Clang][RISCV] Implement vsseg.
Differential Revision: https://reviews.llvm.org/D103871
2021-07-22 09:24:39 +08:00
Hsiangkai Wang e08825b0fc [Clang][RISCV] Add vloxseg and vluxseg test cases. 2021-07-22 09:24:27 +08:00
Hsiangkai Wang 1c55033ea1 [Clang][RISCV] Implement vloxseg and vluxseg.
Differential Revision: https://reviews.llvm.org/D103809
2021-07-22 09:23:47 +08:00
Hsiangkai Wang a9de8f7a53 [Clang][RISCV] Implement vlsseg.
Differential Revision: https://reviews.llvm.org/D103796
2021-07-22 09:23:47 +08:00
Hsiangkai Wang 89ce644902 [Clang][RISCV] Add half-precision FP for vle16/vse16.
I missed to add half-precision FP types for vle16/vse16 in the previous
patches. Added them in this patch.

Differential Revision: https://reviews.llvm.org/D106340
2021-07-21 09:55:21 +08:00
Hsiangkai Wang 0d22dee2ca [Clang][RISCV] Correct the alignment of stores generated by vlseg/vlsegff.
Differential Revision: https://reviews.llvm.org/D106255
2021-07-20 09:29:06 +08:00
Hsiangkai Wang 77bb82d068 [Clang][RISCV] Support half-precision floating point for RVV intrinsics.
Use _Float16 as the half-precision floating point type. Define a new
type specifier 'x' for the _Float16 type.

Differential Revision: https://reviews.llvm.org/D105001
2021-07-19 23:17:01 +08:00
Zakk Chen 08cf69c31f [RISCV] Support overloading for RVV miscellaneous functions.
Based on this update to the intrinsic doc
https://github.com/riscv/rvv-intrinsic-doc/pull/103

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D105611
2021-07-13 21:35:37 -07:00
Fangrui Song 3d89fb4d13 [RISCV] Support machine constraint "S"
Similar to D46745, "S" represents an absolute symbolic operand, which
can be used to specify the access models, e.g.

  extern int var;
  void *addr_via_asm() {
    void *ret;
    asm("lui %0, %%hi(%1)\naddi %0,%0,%%lo(%1)" : "=r"(ret) : "S"(&var));
    return ret;
  }

'S' is documented in trunk GCC: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101275

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D105254
2021-07-13 09:30:09 -07:00
jacquesguan 88326bbce3 [RISCV][clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins
Add extension macro __riscv_zvlsseg to enable Zvlsseg builtins only
with target feature Zvlsseg.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D105626
2021-07-09 13:18:42 +08:00
Hsiangkai Wang 593bf9b4de [Clang][RISCV] Implement vlseg and vlsegff.
Differential Revision: https://reviews.llvm.org/D103527
2021-07-07 13:44:40 +08:00
Craig Topper f225367305 [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.
These allow getting a whole register from a larger lmul. Or
inserting a whole register into a larger lmul register. Fractional
lmuls are not supported as they would require a vslide.

Based on this update to the intrinsic doc
https://github.com/riscv/rvv-intrinsic-doc/pull/99

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D104822
2021-06-24 18:06:36 -07:00
Hsiangkai Wang 2b13ff6979 [Clang][CodeGen] Set the size of llvm.lifetime to unknown for scalable types.
If the memory object is scalable type, we do not know the exact size of
it at compile time. Set the size of lifetime marker to unknown if the
object is scalable one.

Differential Revision: https://reviews.llvm.org/D102822
2021-06-07 23:30:13 +08:00
Craig Topper 18f3a14e13 [RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max)
These are required to be constants, this patch makes sure they
are in the accepted range of values.

These are usually created by wrappers in the riscv_vector.h header
which should always be correct. This patch protects against a user
using the builtin directly.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D102086
2021-05-10 12:11:13 -07:00
Craig Topper cfe3b0005f [RISCV] Reorder masked builtin operands. Use clang_builtin_alias for all overloaded vector builtins.
This patch makes the builtin operand order match the C operand order
for all intrinsics. With this we can use clang_builtin_alias for
all overloaded intrinsics.

This should further reduce the test time for vector intrinsics.

Differential Revision: https://reviews.llvm.org/D101700
2021-05-02 10:57:25 -07:00
Craig Topper f36e6e16a8 [RISCV] Add missing frontend tests for vcompress intrinsics. 2021-05-01 13:07:28 -07:00
Hsiangkai Wang b358a2be52 [RISCV] Remove riscv32 test cases for vector intrinsics. 2021-04-28 15:54:25 +08:00
Hsiangkai Wang 16dc9afa09 [RISCV] Add REQUIRES: riscv-registered-target for RISC-V test cases. 2021-04-26 17:02:27 +08:00
Hsiangkai Wang bd32c2d648 [RISCV] Implement the vwcvt{u}.x.x.v/vncvt.x.x.w builtin.
Differential Revision: https://reviews.llvm.org/D100824
2021-04-26 15:38:31 +08:00
Hsiangkai Wang 645c5f27a8 [RISCV] Implement the pseudo compare builtin.
Differential Revision: https://reviews.llvm.org/D100823
2021-04-26 15:38:31 +08:00
Hsiangkai Wang bfb3fca7e1 [RISCV] Implement the vfabs.v/vfneg.v builtin.
Differential Revision: https://reviews.llvm.org/D100822
2021-04-26 15:38:31 +08:00
Hsiangkai Wang 4b2434172c [RISCV] Implement the vmmv.m/vmnot.m builtin.
Differential Revision: https://reviews.llvm.org/D100821
2021-04-26 15:38:31 +08:00
Levy Hsu 8cf54c7ff5 [RISCV] [1/2] Add IR intrinsic for Zbe extension
RV32/64:
bcompress
bdecompress

RV64 ONLY:
bcompressw
bdecompressw

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D101143
2021-04-25 19:14:34 -07:00
Hsiangkai Wang d8fa5ef6a2 [RISCV] Apply clang_builtin_alias to overloaded builtins.
We only apply `clang_builtin_alias` to non-masked builtins.
Masked builtins could not use `clang_builtin_alias` because the
operand order is different between overloaded intrinsics and builtins.

A bunch of test cases need to be updated.

Differential Revision: https://reviews.llvm.org/D100658
2021-04-25 18:12:19 +08:00
Hsiangkai Wang 108864397d [Clang] Add clang attribute `clang_builtin_alias`.
In some cases, we want to provide the alias name for the clang builtins.
For example, the arguments must be constant integers for some RISC-V builtins.
If we use wrapper functions, we could not constrain the arguments be constant
integer. This attribute is used to achieve the purpose.

Besides this, use `clang_builtin_alias` is more efficient than using
wrapper functions. We use this attribute to deal with test time issue
reported in https://bugs.llvm.org/show_bug.cgi?id=49962.

In our downstream testing, it could decrease the testing time from 6.3
seconds to 3.7 seconds for vloxei.c test.

Differential Revision: https://reviews.llvm.org/D100611
2021-04-25 08:49:19 +08:00
Hsiangkai Wang 43cd588c2d [RISCV] Implement the vnot.v builtin.
Differential Revision: https://reviews.llvm.org/D100820
2021-04-23 13:16:23 +08:00
Hsiangkai Wang 14cc1cb222 [RISCV] Implement the vneg.v builtin.
Differential Revision: https://reviews.llvm.org/D100819
2021-04-23 11:40:18 +08:00
Levy Hsu b49337bbb9 [RISCV] [1/2] Add IR intrinsic for Zbp extension
RV32/64:
    grev
    grevi
    gorc
    gorci
    shfl
    shfli
    unshfl
    unshfli

RV64 ONLY:
    grevw
    greviw
    gorcw
    gorciw
    shflw
    shfli     (For non-existing shfliw)
    unshfli   (For non-existing unshfliw)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D100830
2021-04-22 16:34:51 -07:00
ShihPo Hung 11072a0bdb [RISCV][Clang] Add RVV AMO builtins
Add vamo[swap/add/xor/and/or/min/max/minu/maxu] builtins.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D100448
2021-04-21 01:48:02 -07:00
Zakk Chen 8f683366af [RISCV][Clang] Add RVV miscellaneous intrinsic functions.
1. vreinterpret
2. vundefined
3. LMUL truncation and extension.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D100391
2021-04-16 09:41:19 -07:00
Zakk Chen ca9e52f67c [RISCV][Clang] Drop the assembly tests for RVV intrinsics.
We had verified the correctness of all intrinsics in downstream, so
dropping the assembly tests to decrease the check-clang time.
It would remove 1/3 of the RUN lines.

https://reviews.llvm.org/D99151#2654154 mentions why we need to have
the ASM tests before.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D100617
2021-04-16 09:30:12 -07:00
Zakk Chen ea5d33dbc1 [RISCV][Clang] Add vmv and vfmv series intrinsic functions.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Reviewed By: craig.topper, Jim

Differential Revision: https://reviews.llvm.org/D100266
2021-04-14 22:22:39 -07:00
Zakk Chen 59d5b8c27b [RISCV][Clang] Add some RVV Permutation intrinsic functions.
Support the following instructions.
1. Vector Slide Instructions
2. Vector Register Gather Instructions
3. Vector Compress Instruction

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D100127
2021-04-11 19:19:02 -07:00
Zakk Chen a8fc0e445c [RISCV][Clang] Add all RVV Mask intrinsic functions.
1. Redefine vpopc and vfirst IR intrinsic so it could adapt on
clang tablegen generator which always appends a type for vl
in IntrinsicType of clang codegen.
2. Remove `c` type transformer and add `u` and `l` for unsigned long
and long type.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D100120
2021-04-11 19:19:02 -07:00