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3 Commits

Author SHA1 Message Date
Matt Arsenault 48eda37282 AMDGPU/GlobalISel: Start selecting image intrinsics 
Does not handled atomics yet.
 2020-03-30 17:33:04 -04:00
Matt Arsenault 2641ba52a9 AMDGPU/GlobalISel: Round up image operations with 5, 6 or 7 addresses 
The instruction definitions are missing for these register types, so
round up to 8 like the DAG.
 2020-03-30 17:02:47 -04:00
Matt Arsenault 039c917b43 AMDGPU/GlobalISel: Fix asserting on gather4 intrinsics 2020-03-17 11:07:30 -04:00