4 Commits

Author	SHA1	Message	Date
Tom Stellard	c5a154db48	AMDGPU: Separate R600 and GCN TableGen files ... Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942	2018-06-28 23:47:12 +00:00
Jan Vesely	39aeab4f30	AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction ... Only used by pre-GCN targets v2: fix predicate setting for FMA_Common Differential Revision: https://reviews.llvm.org/D40692 llvm-svn: 319712	2017-12-04 23:07:28 +00:00
Jan Vesely	d1c9b61e2b	AMDGPU: Disable fp64 support on pre GCN asics ... It's not implemented. Passing +fp64-fp16-denormal feature enables fp64 even on asics that don't support it v2: fix hasFP64 query Differential Revision: https://reviews.llvm.org/D39931 llvm-svn: 319709	2017-12-04 22:57:29 +00:00
Konstantin Zhuravlyov	27b0a033d8	AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td ... Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920	2017-11-10 20:01:58 +00:00