4a3711d077
Add class MipsCC which provides methods used to analyze formal and call
...
arguments and inquire about calling convention information.
llvm-svn: 166840
2012-10-26 23:56:38 +00:00
e485c65642
Delete MipsFunctionInfo::InArgFIRange.
...
llvm-svn: 166837
2012-10-26 23:49:51 +00:00
868b3a333b
[mips] Make sure sret argument is returned in register V0.
...
llvm-svn: 166539
2012-10-24 02:10:54 +00:00
0c7d131a7b
[mips] Use 64-bit registers to return an sret pointer if target ABI is N64.
...
llvm-svn: 166344
2012-10-19 22:11:40 +00:00
90131ac26c
[mips] Add code to do tail call optimization.
...
Currently, it is enabled only if option "enable-mips-tail-calls" is given and
all of the callee's arguments are passed in registers.
llvm-svn: 166342
2012-10-19 21:47:33 +00:00
c046243488
[mips] Delete MipsFunctionInfo::MaxCallFrameSize which is no longer used.
...
llvm-svn: 166339
2012-10-19 21:18:38 +00:00
91318df0cc
Add node and enum for mips tail call.
...
llvm-svn: 166318
2012-10-19 20:59:39 +00:00
9c8dcfc73a
Implement MipsTargetLowering::CanLowerReturn.
...
Patch by Sasa Stankovic.
llvm-svn: 165585
2012-10-10 01:27:09 +00:00
240322140e
Patch for integer multiply, signed/unsigned, long/long long.
...
llvm-svn: 165322
2012-10-05 18:27:54 +00:00
e4bd054f98
MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction.
...
llvm-svn: 164751
2012-09-27 02:15:57 +00:00
9061a46443
MIPS DSP: all the remaining instructions which read or write accumulators.
...
llvm-svn: 164750
2012-09-27 02:11:20 +00:00
1babeaa44c
MIPS DSP: add support for extract-word instructions.
...
llvm-svn: 164749
2012-09-27 02:05:42 +00:00
fabb8cf421
Add MIPS DSP register classes. Set actions of DSP vector operations and override
...
TargetLowering's callback functions.
llvm-svn: 164431
2012-09-21 23:58:31 +00:00
233ac53a3f
SelectionDAG node enums for MIPS DSP nodes.
...
llvm-svn: 164430
2012-09-21 23:52:47 +00:00
189d0adde9
Handled unaligned load/stores properly in Mips16
...
Patch by Reed Kotler.
llvm-svn: 163956
2012-09-15 01:02:03 +00:00
92a96e1da4
Misc.
...
1. Remove RA from list of allocatable registers
2. Enable d,y,r constraint inline assembly instructions
Patch by Reed Kotler.
llvm-svn: 163753
2012-09-12 23:27:55 +00:00
abb87d4857
Fix PR11985
...
- BlockAddress has no support of BA + offset form and there is no way to
propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
support BA + offset addressing.
llvm-svn: 163743
2012-09-12 21:43:09 +00:00
ad06cee239
Stop casting away const qualifier needlessly.
...
llvm-svn: 163258
2012-09-05 22:26:57 +00:00
ad4950258b
Add register Mips::GP to the list of reserved registers if target is bare-metal
...
to prevent it from being clobbered. mips uses $gp to access small data section.
This bug was originally reported by Carl Norum.
llvm-svn: 162340
2012-08-22 03:18:13 +00:00
33a25af5a8
Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.
...
The frame object which points to the dynamically allocated area will not be
needed after changes are made to cease reserving call frames.
llvm-svn: 161076
2012-07-31 20:54:48 +00:00
beda2241a4
When store nodes or memcpy nodes are created to copy the function call
...
arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and
integer offset operands rather than frame object operands.
llvm-svn: 161068
2012-07-31 18:46:41 +00:00
4ce7c4060d
Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
...
single-precision load and store.
Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.
llvm-svn: 161063
2012-07-31 18:16:49 +00:00
97ba7696f8
Pass the correct call frame size to callseq_start node. This is needed to
...
replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with
the one MachineFrameInfo has.
llvm-svn: 160841
2012-07-26 23:27:01 +00:00
64626fc20f
Fix call setup for PIC.
...
Patch by Reed Kotler.
llvm-svn: 160774
2012-07-26 02:24:43 +00:00
26e9ecb7a3
Add basic ability to setup call frame, and make procedure calls.
...
Hello world will compile and execute with this patch.
Patch by Reed Kotler.
llvm-svn: 160651
2012-07-23 23:45:54 +00:00
b49c68a65d
Revert accidental commit.
...
llvm-svn: 160598
2012-07-21 02:20:33 +00:00
f73e362758
Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.
...
Test case will be added later when long branch patch is checked in.
llvm-svn: 160597
2012-07-21 02:15:19 +00:00
24cf4e36e5
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.
...
llvm-svn: 160064
2012-07-11 19:32:27 +00:00
878ad8b28d
Lower RETURNADDR node in Mips backend.
...
Patch by Sasa Stankovic.
llvm-svn: 160031
2012-07-11 00:53:32 +00:00
efff7b763b
Make register Mips::RA allocatable if not in mips16 mode.
...
llvm-svn: 159971
2012-07-10 00:19:06 +00:00
b353094f27
mips32 long long register inline asm constraint support.
...
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
llvm-svn: 159625
2012-07-02 23:35:23 +00:00
dfc3e68c40
Revert " mips32 long long register inline asm constraint support." as
...
it appears to be breaking the bots.
This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876.
llvm-svn: 159619
2012-07-02 23:22:25 +00:00
5c1a01a625
mips32 long long register inline asm constraint support.
...
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
llvm-svn: 159610
2012-07-02 22:39:45 +00:00
5fd22485a3
Fix coding style violations. Remove white spaces and tabs.
...
llvm-svn: 158471
2012-06-14 21:10:56 +00:00
df5205ef3d
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following
...
pattern:
(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
"tjt" is a TargetJumpTable node.
llvm-svn: 158419
2012-06-13 20:33:18 +00:00
1daf8c2a16
Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.
...
llvm-svn: 158414
2012-06-13 19:33:32 +00:00
9586618c58
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.
...
llvm-svn: 158413
2012-06-13 19:06:08 +00:00
f0273603f5
Implement fastcc calling convention for MIPS.
...
llvm-svn: 158410
2012-06-13 18:06:00 +00:00
6734685f21
Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is
...
inserted after the shift-left-logical node.
llvm-svn: 157937
2012-06-04 17:46:29 +00:00
245917b536
MIPS TLS: use the model selected by TargetMachine::getTLSModel().
...
This was mostly done already in r156162, but I missed one place.
llvm-svn: 157929
2012-06-04 14:02:08 +00:00
58268c23ac
remove an unused variable.
...
llvm-svn: 157872
2012-06-02 01:03:42 +00:00
019e592f75
Set operation actions for load/store nodes in the Mips backend.
...
llvm-svn: 157866
2012-06-02 00:04:42 +00:00
8f1db778a4
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which
...
custom-lower unaligned load and store nodes.
llvm-svn: 157864
2012-06-02 00:03:49 +00:00
b9ebf8d644
Define Mips specific unaligned load/store nodes.
...
llvm-svn: 157863
2012-06-02 00:03:12 +00:00
4e76bf8282
Expand unaligned i16 loads/stores for the Mips backend.
...
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.
llvm-svn: 157862
2012-06-02 00:02:45 +00:00
bff8e31d3c
Cleanup and factoring of mips16 tablegen classes. Make register classes
...
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.
Patch by Reed Kotler.
llvm-svn: 157730
2012-05-31 02:59:44 +00:00
aa58397b3c
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
...
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
llvm-svn: 157479
2012-05-25 16:35:28 +00:00
f542ebd958
Make the following changes in MipsISelLowering.cpp:
...
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
before the call node. This will ensure $gp is valid at the entry of the
called function.
llvm-svn: 156692
2012-05-12 03:19:04 +00:00
0a8ab718cb
Expand 64-bit shifts if target ABI is O32.
...
llvm-svn: 156457
2012-05-09 00:55:21 +00:00
0d8c15d20f
Add support for the 'x' constraint.
...
Patch by Jack Carter.
llvm-svn: 156295
2012-05-07 06:25:19 +00:00
9c492e6ebf
Add support for the 'l' constraint.
...
Patch by Jack Carter.
llvm-svn: 156294
2012-05-07 06:25:15 +00:00
e3c494de82
Add support for the 'c' constraint.
...
Patch by Jack Carter.
llvm-svn: 156293
2012-05-07 06:25:10 +00:00
c18ae4a3b1
Add support for the 'P' constraint.
...
Patch by Jack Carter.
llvm-svn: 156292
2012-05-07 06:25:02 +00:00
470578a91b
Add support for the 'O' constraint.
...
Patch by Jack Carter.
llvm-svn: 156285
2012-05-07 05:46:48 +00:00
e07aa430b8
Add support for the 'N' inline asm constraint.
...
Patch by Jack Carter.
llvm-svn: 156284
2012-05-07 05:46:43 +00:00
1109b3406d
Add support for the 'L' inline asm constraint.
...
Patch by Jack Carter.
llvm-svn: 156283
2012-05-07 05:46:37 +00:00
3ff88a05b7
Add support for the inline asm constraint 'K'.
...
llvm-svn: 156282
2012-05-07 05:46:29 +00:00
7201e1b4b9
Support the 'J' constraint.
...
Patch by Jack Carter.
llvm-svn: 156280
2012-05-07 03:13:42 +00:00
1d6c89eea1
Add support for the 'I' inline asm constraint. Also add tests
...
from the previous 2 patches.
Patch by Jack Carter.
llvm-svn: 156279
2012-05-07 03:13:32 +00:00
58daf04681
Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.
...
Patch by Jack Carter.
llvm-svn: 156278
2012-05-07 03:13:22 +00:00
cfcd77b0bc
When using inline asm constraints representing
...
non-floating point general registers allow 8 and 16-bit
elements.
Patch by Jack Carter.
llvm-svn: 156277
2012-05-07 03:13:16 +00:00
aea412008e
Make ARM and Mips use TargetMachine::getTLSModel()
...
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).
llvm-svn: 156162
2012-05-04 09:40:39 +00:00
e30303fa86
llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC.
...
Thanks to Andy Gibbs, to report the issue.
llvm-svn: 155287
2012-04-21 15:31:45 +00:00
c7242e054d
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
...
llvm-svn: 155188
2012-04-20 07:30:17 +00:00
47ad674f67
Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,
...
otherwise expand FNEG during legalization.
llvm-svn: 154546
2012-04-11 22:59:08 +00:00
7f4c9d1429
Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.
...
Invalid operation is signaled if the operand of these instructions is NaN.
llvm-svn: 154545
2012-04-11 22:49:04 +00:00
4f5c8421b3
Fix bugs in lowering of FCOPYSIGN nodes.
...
- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.
Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).
llvm-svn: 154540
2012-04-11 22:13:04 +00:00
121342fcc2
Reapply 154038 without the failing test.
...
llvm-svn: 154062
2012-04-04 22:16:36 +00:00
4743c6e159
Revert r154038. It was causing make check failures.
...
llvm-svn: 154054
2012-04-04 21:18:58 +00:00
9705c865d9
Fix LowerGlobalAddress to produce instructions with the correct relocation
...
types for N32 ABI. Add new test case and update existing ones.
llvm-svn: 154038
2012-04-04 19:02:38 +00:00
591ecdd7c1
Fix LowerJumpTable to produce instructions with the correct relocation
...
types for N32 ABI. Test case will be updated after the patch that fixes
TargetLowering::getPICJumpTableRelocBase is checked in.
llvm-svn: 154036
2012-04-04 18:31:32 +00:00
b3a2b8c199
Fix LowerConstantPool to produce instructions with the correct relocation
...
types for N32 ABI and update test case.
llvm-svn: 154034
2012-04-04 18:26:12 +00:00
aeff24e424
Fix LowerBlockAddress to produce instructions with the correct relocation
...
types for N32 ABI and update test case.
llvm-svn: 154031
2012-04-04 18:22:53 +00:00
0603ad8c65
Expand FREM.
...
llvm-svn: 153671
2012-03-29 18:43:11 +00:00
8a7633c74e
Pass the llvm IR pointer value and offset to the constructor of
...
MachinePointerInfo when getStore is called to create a node that stores an
argument passed in register to the stack. Without this change, the post RA
scheduler will fail to discover the dependencies between the stores
instructions and the instructions that load from a structure passed by value.
The link to the related discussion is here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html
llvm-svn: 153499
2012-03-27 03:13:56 +00:00
769f69f9b6
Fix bug in LowerConstantPool.
...
llvm-svn: 153498
2012-03-27 02:55:31 +00:00
b25fda95f6
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
...
llvm-svn: 152997
2012-03-17 18:46:09 +00:00
bef78fc2ee
Convert more static tables of registers used by calling convention to uint16_t to reduce space.
...
llvm-svn: 152538
2012-03-11 07:57:25 +00:00
da00aa80b6
Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set
...
operation action of nodes.
llvm-svn: 152452
2012-03-10 00:03:50 +00:00
b7f78592e2
Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass.
...
llvm-svn: 152450
2012-03-09 23:46:03 +00:00
5e152182a4
Invoke setTargetDAGCombine for SELECT.
...
llvm-svn: 152290
2012-03-08 03:26:37 +00:00
7dd7c08419
Swap the operands of a select node if the false (the second) operand is 0.
...
For example, this pattern
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)
This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.
llvm-svn: 152285
2012-03-08 02:14:24 +00:00
956dd2261e
Set minimum function alignment to 3 if target is Mips64.
...
llvm-svn: 152282
2012-03-08 01:59:33 +00:00
5350c24509
Changes for migrating to using register mask operands.
...
llvm-svn: 151847
2012-03-01 22:27:29 +00:00
6bbe1f0d10
Fix bugs which were introduced when support for base+index floating point loads
...
and stores was added.
- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.
llvm-svn: 151843
2012-03-01 22:12:30 +00:00
65f9d19c4f
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
...
llvm-svn: 151645
2012-02-28 18:51:51 +00:00
ee7b899343
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
...
llvm-svn: 151630
2012-02-28 15:36:07 +00:00
f54f60f3ce
remove blanks, and some code format
...
llvm-svn: 151625
2012-02-28 07:46:26 +00:00
87c7b09d8d
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
...
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
llvm-svn: 151623
2012-02-28 06:42:03 +00:00
330d901ce3
Add support for floating point base register + offset register addressing mode
...
load and store instructions.
llvm-svn: 151611
2012-02-28 02:55:02 +00:00
b049aef2d1
Add an option to use a virtual register as the global base register instead of
...
reserving a physical register ($gp or $28) for that purpose.
This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register.
example:
.cpload $25 // set $gp.
...
.cprestore 16 // store $gp to stack slot 16($sp).
...
jalr $25 // function call. clobbers $gp.
lw $gp, 16($sp) // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25 // function call.
lw $gp, 16($sp) // not emitted if $gp is not live after this instruction.
...
llvm-svn: 151402
2012-02-24 22:34:47 +00:00
760b134ffa
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
...
llvm-svn: 151134
2012-02-22 05:59:10 +00:00
9f6101191b
remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.
...
llvm-svn: 150805
2012-02-17 08:55:11 +00:00
d608bac682
Do not promote i32 arguments to i64. This was causing unnecessary sign extension
...
instructions to be emitted.
llvm-svn: 150782
2012-02-17 02:20:26 +00:00
dd6c1cd4e8
add Emacs tag and fix some comment error in file headers
...
llvm-svn: 150775
2012-02-17 01:23:50 +00:00
e55c556a24
Convert assert(0) to llvm_unreachable
...
llvm-svn: 149961
2012-02-07 02:50:20 +00:00
f0b08445f6
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is
...
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.
llvm-svn: 149668
2012-02-03 04:33:00 +00:00
961883c1cf
Set the correct stack pointer register.
...
llvm-svn: 149585
2012-02-02 03:17:04 +00:00
f029537e68
Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer and
...
selector registers.
llvm-svn: 149584
2012-02-02 03:13:40 +00:00
d7970f9e4b
Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,
...
which is what N32/64 does.
llvm-svn: 148875
2012-01-24 23:18:43 +00:00
7e6c195c11
Pass CCState by reference.
...
llvm-svn: 148871
2012-01-24 22:07:36 +00:00
46a9f016c5
More dead code removal (using -Wunreachable-code)
...
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
aac3e06bf7
Enable -soft-float for MIPS.
...
llvm-svn: 147541
2012-01-04 19:29:11 +00:00
c669d7a6db
Have getRegForInlineAsmConstraint return the correct register class when target
...
is Mips64.
llvm-svn: 147516
2012-01-04 02:45:01 +00:00
1d8efaba7e
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
...
case for DCLO and DCLZ.
llvm-svn: 147022
2011-12-21 00:20:27 +00:00
410ce9cb44
Expand 64-bit CTPOP and CTTZ.
...
llvm-svn: 147021
2011-12-21 00:14:05 +00:00
91c052c4d8
Expand 64-bit atomic load and store.
...
llvm-svn: 147019
2011-12-21 00:02:58 +00:00
4706ac9715
Add definition of DSBH (Double Swap Bytes within Halfwords) and
...
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.
llvm-svn: 147017
2011-12-20 23:56:43 +00:00
79aed157e7
64-bit uint-fp conversion nodes are expanded.
...
llvm-svn: 147014
2011-12-20 23:40:56 +00:00
2bb8d068f5
Enable custom lowering DYNAMIC_STACKALLOC nodes.
...
llvm-svn: 147013
2011-12-20 23:35:46 +00:00
8e2c02e2d6
Set the correct stack pointer register that should be saved or restored.
...
llvm-svn: 147012
2011-12-20 23:28:36 +00:00
9e1d369e3c
Tidy up. Simplify logic. No functional change intended.
...
llvm-svn: 146896
2011-12-19 19:52:25 +00:00
bff84e1914
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
...
emission is not supported yet, but a patch that adds the support should follow
soon.
llvm-svn: 146572
2011-12-14 18:26:41 +00:00
637cc6a8aa
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
...
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
llvm-svn: 146466
2011-12-13 01:56:10 +00:00
faa88c0add
Fix indentation.
...
llvm-svn: 146431
2011-12-12 22:38:19 +00:00
64ba50a972
Mips: Don't create a dangling IR function just to get the address of a symbol.
...
llvm-svn: 146340
2011-12-11 12:21:34 +00:00
5ee8464e48
Rename WrapperPIC. It is now used for both pic and static.
...
llvm-svn: 146232
2011-12-09 01:53:17 +00:00
8e16aac534
jalr should use t9 ($25) for indirect calls regardless of the relocation model
...
specified.
llvm-svn: 146229
2011-12-09 01:45:12 +00:00
f10ee84956
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in
...
MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.
llvm-svn: 146183
2011-12-08 21:05:38 +00:00
dee6c8275c
Implement 64-bit support for thread local storage handling.
...
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
llvm-svn: 146175
2011-12-08 20:34:32 +00:00
c5b5a8d8b1
Modify LowerFCOPYSIGN to handle Mips64.
...
llvm-svn: 146080
2011-12-07 21:48:50 +00:00
61e6d987bf
Add a few moreLocal/Global R_MIPS_GOT related fixups and
...
make the addend fixup code a bit more generic
Patch by Jack Carter.
llvm-svn: 145998
2011-12-07 00:28:57 +00:00
20cee2eba1
Add definitions of 64-bit extract and insert instrucions and make
...
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
llvm-svn: 145853
2011-12-05 21:26:34 +00:00
34e3df76f9
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
...
O32 with relocation-model=pic too.
llvm-svn: 145850
2011-12-05 21:03:03 +00:00
b31abde0f3
Lower 64-bit constant pool node.
...
llvm-svn: 144849
2011-11-16 22:44:38 +00:00
eb42071721
Lower 64-bit block address.
...
llvm-svn: 144847
2011-11-16 22:42:10 +00:00
66a14c0650
Simplify function PassByValArg64.
...
llvm-svn: 144664
2011-11-15 18:42:25 +00:00
319904cc7e
Unbreak Release builds.
...
llvm-svn: 144560
2011-11-14 19:51:48 +00:00
0b8bc00424
AnalyzeCallOperands function for N32/64.
...
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.
llvm-svn: 144553
2011-11-14 19:02:54 +00:00
52359363f2
Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64.
...
llvm-svn: 144552
2011-11-14 19:01:09 +00:00
d673cfe027
Remove variable that keeps the size of area used to save byval or variable
...
argument registers on the callee's stack frame, along with functions that set
and get it.
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.
llvm-svn: 144549
2011-11-14 18:56:20 +00:00
77733535eb
Fix typo.
...
llvm-svn: 144453
2011-11-12 02:38:12 +00:00
19891f843c
Implement Mips64's handling of byval arguments in LowerCall.
...
llvm-svn: 144452
2011-11-12 02:34:50 +00:00
fb9bae34da
Implement Mips64's handling of byval arguments in LowerFormalArguments.
...
llvm-svn: 144449
2011-11-12 02:29:58 +00:00
202f6400ef
Function for handling byval arguments.
...
llvm-svn: 144447
2011-11-12 02:20:46 +00:00
c85e3ff334
Mips MC object code emission improvements:
...
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter
llvm-svn: 144414
2011-11-11 22:58:42 +00:00
4a63d1c0f0
Do not try to detect DAG combine patterns for integer multiply-add/sub if value
...
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.
llvm-svn: 144373
2011-11-11 04:18:21 +00:00
21cbc25bbb
64-bit atomic instructions.
...
llvm-svn: 144372
2011-11-11 04:14:30 +00:00
9189d7127f
Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.
...
llvm-svn: 144371
2011-11-11 04:11:56 +00:00
4bdfec57ba
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
...
llvm-svn: 144370
2011-11-11 04:06:38 +00:00
82cd9e81fc
Added invariant field to the DAG.getLoad method and changed all calls.
...
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
llvm-svn: 144100
2011-11-08 18:42:53 +00:00
104b7e3f2c
Make changes necessary in LowerFormalArguments to support Mips64.
...
llvm-svn: 143218
2011-10-28 19:55:48 +00:00
b20a325baf
Make changes necessary in LowerCall to support Mips64.
...
llvm-svn: 143217
2011-10-28 19:49:00 +00:00
7989f15d37
Add variable IsO32 to MipsTargetLowering.
...
llvm-svn: 143213
2011-10-28 18:47:24 +00:00
4c42be5b32
Fix misc warnings. Patch by Joe Abbey.
...
llvm-svn: 142332
2011-10-18 03:17:34 +00:00
a7e0b90897
Add definitions of conditional moves with 64-bit operands. Comment out code for
...
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
llvm-svn: 142226
2011-10-17 18:53:29 +00:00
09b23eb7bc
Modify lowering of GlobalAddress so that correct code is emitted when target is
...
Mips64.
llvm-svn: 141618
2011-10-11 00:55:05 +00:00
be68f3c348
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
...
zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
...
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
7ba8a8d656
Add definitions of Mips64 rotate instructions.
...
llvm-svn: 140870
2011-09-30 18:51:46 +00:00
a6a9c20c23
Set register class of a register according to value of HasMips64.
...
llvm-svn: 140570
2011-09-26 21:55:17 +00:00
7b502920ef
Define variable HasMips64 in MipsTargetLowering.
...
llvm-svn: 140569
2011-09-26 21:47:02 +00:00
e5ce709022
In single float mode, double precision FP arguments are passed in integer
...
registers, so there is no need to check here.
llvm-svn: 140568
2011-09-26 21:37:50 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
...
llvm-svn: 140443
2011-09-24 01:34:44 +00:00
ceb55e72de
Make FGR64RegisterClass available if target is Mips64.
...
llvm-svn: 140397
2011-09-23 18:28:39 +00:00
61bbcce84a
Do not rely on the enum values of argument registers A0-A3 being consecutive.
...
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.
llvm-svn: 140363
2011-09-23 00:58:33 +00:00
6a5f8b2fd4
Remove unnecessary condition check.
...
llvm-svn: 140291
2011-09-22 02:41:29 +00:00
bb49e721b8
Change the names of functions isMips* to hasMips*.
...
llvm-svn: 140214
2011-09-20 23:53:09 +00:00
79738336a8
Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't
...
yet legal according to comments in LegalizeDAG.cpp:227.
Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.
The two failing tests reported in PR10876 pass after applying this patch.
llvm-svn: 140046
2011-09-19 20:26:02 +00:00
f2641e1bc1
Add codegen support for vector select (in the IR this means a select
...
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
llvm-svn: 139159
2011-09-06 19:07:46 +00:00
7dfa791f4f
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
...
llvm-svn: 138751
2011-08-29 18:23:02 +00:00
419fd4f315
Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
...
needed for Mips32.
llvm-svn: 138132
2011-08-19 22:59:00 +00:00
fb4161ae88
Use subword loads instead of a 4-byte load when the size of a structure (or a
...
piece of it) that is being passed by value is smaller than a word.
llvm-svn: 138007
2011-08-18 23:39:37 +00:00
73d78b7ab1
Make IsShiftedMask a static function rather than defining it in an
...
anonymous namespace.
llvm-svn: 137975
2011-08-18 20:07:42 +00:00
eea541ce4e
Changed definition of EXT and INS per Bruno's comments.
...
llvm-svn: 137892
2011-08-17 22:59:46 +00:00
b2e7558c40
Add support for half-word unaligned loads and stores.
...
llvm-svn: 137848
2011-08-17 18:49:18 +00:00
184b63d09c
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment.
...
llvm-svn: 137831
2011-08-17 17:45:08 +00:00
5360f88355
Add support for ext and ins.
...
llvm-svn: 137804
2011-08-17 02:05:42 +00:00
2fcc1cfdce
Define unaligned load and store.
...
llvm-svn: 137515
2011-08-12 21:30:06 +00:00
30a49e93e3
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
...
I think this completes the basic CodeGen for atomicrmw and cmpxchg.
llvm-svn: 136813
2011-08-03 21:06:02 +00:00
26a484852e
Code generation for 'fence' instruction.
...
llvm-svn: 136283
2011-07-27 22:21:52 +00:00
a4c09bce9b
Lower memory barriers to sync instructions.
...
llvm-svn: 135537
2011-07-19 23:30:50 +00:00
9663dd3f00
Change variable name.
...
llvm-svn: 135522
2011-07-19 20:56:53 +00:00
f3b29992d5
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
...
ANDi, when the instruction does not have any immediate operands.
llvm-svn: 135520
2011-07-19 20:34:00 +00:00
0e01959327
Use descriptive variable names.
...
llvm-svn: 135514
2011-07-19 20:11:17 +00:00
db2ccdcfd2
Fix comments.
...
llvm-svn: 135496
2011-07-19 18:19:40 +00:00
e450358a21
Remove redundant instructions.
...
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
instruction being expanded, instead of masking it in thisMBB.
- Remove redundant Or in EmitAtomicCmpSwap.
llvm-svn: 135495
2011-07-19 18:14:26 +00:00
08636b4633
Separate code that modifies control flow from code that adds instruction to
...
basic blocks.
llvm-svn: 135490
2011-07-19 17:09:53 +00:00
e4e9a590d2
Make EmitAtomic functions return the correct MachineBasicBlocks so that
...
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.
llvm-svn: 135465
2011-07-19 03:42:13 +00:00
e97bd81f07
Do not insert instructions in reverse order.
...
llvm-svn: 135464
2011-07-19 03:14:58 +00:00
338879a7f4
Do not treat atomic.load.sub differently than other atomic binary intrinsics.
...
llvm-svn: 135418
2011-07-18 19:58:59 +00:00
27292638bd
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
...
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
llvm-svn: 135415
2011-07-18 18:52:12 +00:00
8b98515c29
Change destination register operands of SC instructions so that unique
...
virtual registers are used.
llvm-svn: 135403
2011-07-18 17:44:27 +00:00
229907cd11
land David Blaikie's patch to de-constify Type, with a few tweaks.
...
llvm-svn: 135375
2011-07-18 04:54:35 +00:00
f03fa189ca
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
...
is to use this for architectures that have a native FMA instruction.
llvm-svn: 134742
2011-07-08 21:39:21 +00:00
9c6028f98e
Lower MachineInstr to MC Inst and print to .s files.
...
llvm-svn: 134661
2011-07-07 23:56:50 +00:00
2e766ed2f8
Reverse order of operands of address operand mem so that the base operand comes
...
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.
llvm-svn: 134625
2011-07-07 18:57:00 +00:00
eaf77dc2bd
Update comment for getRegForInlineAsmConstraint for Mips.
...
llvm-svn: 134087
2011-06-29 19:33:04 +00:00
9519c08a43
Remove getRegClassForInlineAsmConstraint for Mips.
...
Part of rdar://9643582
llvm-svn: 134084
2011-06-29 19:04:31 +00:00
35792089e7
Change the chain input of nodes that load the address of a function. This change
...
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.
llvm-svn: 133811
2011-06-24 19:01:25 +00:00
5b350be79d
Coding style fixes.
...
llvm-svn: 133496
2011-06-21 01:02:03 +00:00
4c406e7457
Re-apply 132758 and 132768 which were speculatively reverted in 132777.
...
llvm-svn: 133494
2011-06-21 00:40:49 +00:00
5444a7b4cd
Silence warnings in non assert builds. Patch by David Blaikie
...
llvm-svn: 133118
2011-06-16 00:40:02 +00:00
f15601f19a
Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
...
llvm-svn: 132777
2011-06-09 16:03:19 +00:00
0713a9d8fc
Add a parameter to CCState so that it can access the MachineFunction.
...
No functional change.
Part of PR6965
llvm-svn: 132763
2011-06-08 23:55:35 +00:00
4e9af454f7
Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
...
dynamically allocated stack area was not set.
llvm-svn: 132758
2011-06-08 21:28:09 +00:00
195a1e2184
Reorganize code in MipsTargetLowering::LowerCall to improve readability.
...
llvm-svn: 132756
2011-06-08 17:39:33 +00:00
41956cf6e3
Refactor MipsTargetLowering::EmitInstrWithCustomInserter.
...
llvm-svn: 132726
2011-06-07 19:28:39 +00:00
1550678765
Coding style fixes.
...
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.
llvm-svn: 132724
2011-06-07 18:58:42 +00:00
6627752050
Custom-lower FRAMEADDR. Patch by Sasa Stankovic.
...
llvm-svn: 132444
2011-06-02 00:24:44 +00:00
Akira Hatanaka