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411 Commits

Author SHA1 Message Date
Evan Cheng a7ca624028 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
llvm-svn: 37643
 2007-06-19 01:26:51 +00:00
Evan Cheng e8c3cbf971 Mark these instructions clobbersPred. They modify the condition code register. 
llvm-svn: 37468
 2007-06-06 10:17:05 +00:00
Evan Cheng 9aa5fc8577 Opcode modifier s comes after condition code. e.g. addlts, not addslt. 
llvm-svn: 37388
 2007-06-01 20:51:29 +00:00
Evan Cheng a2ab4e5feb Make jumptable non-predicable for now. 
llvm-svn: 37381
 2007-06-01 00:56:15 +00:00
Evan Cheng a6e9a4ce07 For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq. 
llvm-svn: 37349
 2007-05-29 23:32:06 +00:00
Dale Johannesen d1de276c16 Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. 
llvm-svn: 37271
 2007-05-21 22:42:04 +00:00
Dale Johannesen 7d55f3733e Add some patterns for PIC PC-relative loads and stores. 
llvm-svn: 37269
 2007-05-21 22:14:33 +00:00
Evan Cheng 4ae1840d21 Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code. 
llvm-svn: 37199
 2007-05-18 01:53:54 +00:00
Evan Cheng dcd6cdf896 Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable. 
llvm-svn: 37118
 2007-05-16 20:50:01 +00:00
Evan Cheng 01a4227ed1 Conditional branch is not a barrier. 
llvm-svn: 37103
 2007-05-16 07:45:54 +00:00
Evan Cheng 0f7cbe8370 Add PredicateOperand to all ARM instructions that have the condition field. 
llvm-svn: 37066
 2007-05-15 01:29:07 +00:00
Evan Cheng 9c031c0ddf Switch BCC, MOVCCr, etc. to PredicateOperand. 
llvm-svn: 36948
 2007-05-08 21:08:43 +00:00
Dale Johannesen 7e7280b538 change per review 
llvm-svn: 36519
 2007-04-28 00:36:37 +00:00
Dale Johannesen 29c05756b5 Prevent Thumb code from generating ARM instructions 
llvm-svn: 36518
 2007-04-27 22:17:18 +00:00
Lauro Ramos Venancio c39c12a3fa ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. 
llvm-svn: 36506
 2007-04-27 13:54:47 +00:00
Chris Lattner 598bc0d9a3 dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll 
llvm-svn: 36222
 2007-04-17 22:39:58 +00:00
Lauro Ramos Venancio 6be85337b0 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573
 2007-04-02 01:30:03 +00:00
Lauro Ramos Venancio 143b0dff31 bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
llvm-svn: 35381
 2007-03-27 16:19:21 +00:00
Lauro Ramos Venancio a88c4a74f3 bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Evan Cheng 9e7b838469 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
llvm-svn: 35207
 2007-03-20 08:11:30 +00:00
Evan Cheng 9bb01c9f4f Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng ee2763f76f Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
 2007-03-19 07:20:03 +00:00
Evan Cheng 5be3e09a30 Constant generation instructions are re-materializable. 
llvm-svn: 35161
 2007-03-19 07:09:02 +00:00
Evan Cheng 456db39ea9 ARM callseq_end should have a input flag operand so it would be scheduled right after the call. 
llvm-svn: 33832
 2007-02-03 09:11:58 +00:00
Evan Cheng 83f35170fa - Fix codegen for pc relative constant (e.g. JT) in thumb mode: 
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.

llvm-svn: 33664
 2007-01-30 20:37:08 +00:00
Jim Laskey f9e5445ed4 Make LABEL a builtin opcode. 
llvm-svn: 33537
 2007-01-26 14:34:52 +00:00
Evan Cheng 77c15ded10 Code clean up. Use def : pat instead of defining new instructions. 
llvm-svn: 33368
 2007-01-19 20:27:35 +00:00
Evan Cheng 10043e215b ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00
Rafael Espindola fd68718467 implement missing compares 
patch by Lauro
bug fixed by me

llvm-svn: 32795
 2006-12-31 18:52:39 +00:00
Lauro Ramos Venancio 7251e57ff8 Implement SELECT_CC (f32/f64) for ARM. 
llvm-svn: 32762
 2006-12-28 13:11:14 +00:00
Rafael Espindola 865b979833 remove duplicated line 
bug noticed by Lauro

llvm-svn: 32761
 2006-12-28 12:51:40 +00:00
Lauro Ramos Venancio d0ced3f1e8 This patch defines extloadi1 and fixes an internal compiler error on 
arm.

llvm-svn: 32760
 2006-12-26 19:30:42 +00:00
Rafael Espindola 67d1c8ae0e more general matching of the MVN instruction 
llvm-svn: 32484
 2006-12-12 17:10:13 +00:00
Rafael Espindola 9fa0a26808 use MVN to handle small negative constants 
llvm-svn: 32459
 2006-12-12 01:03:11 +00:00
Rafael Espindola 1bbe581d0f add mvn 
llvm-svn: 32454
 2006-12-12 00:37:38 +00:00
Rafael Espindola 87f4382163 fix truncstorei1 
llvm-svn: 32364
 2006-12-08 18:41:21 +00:00
Rafael Espindola 5f7ab1b964 implement load effective address similar to the alpha backend 
remove lea_addri and the now unused memri addressing mode

llvm-svn: 31592
 2006-11-09 13:58:55 +00:00
Rafael Espindola 708cb60588 initial implementation of addressing mode 2 
TODO: fix lea_addri

llvm-svn: 31552
 2006-11-08 17:07:32 +00:00
Chris Lattner 9ac6442db6 remove dead/redundant vars 
llvm-svn: 31435
 2006-11-03 23:48:56 +00:00
Rafael Espindola 0cd8d14c7c implement zextload bool and truncstore bool 
llvm-svn: 31348
 2006-11-01 14:13:27 +00:00
Chris Lattner aaeede0aa2 implement uncond branch insertion, mark branches with isBranch. 
llvm-svn: 31160
 2006-10-24 16:47:57 +00:00
Rafael Espindola b43efe86f5 implement STRB and STRH 
llvm-svn: 31138
 2006-10-23 20:34:27 +00:00
Rafael Espindola 336d62e99a use Pat to implement extloadi8 and extloadi16 
llvm-svn: 31052
 2006-10-19 17:05:03 +00:00
Rafael Espindola f8274c0318 implement undef 
llvm-svn: 31049
 2006-10-19 13:45:00 +00:00
Rafael Espindola ff62819e2f implement extloadi8 and extloadi16 
llvm-svn: 31047
 2006-10-19 12:45:04 +00:00
Rafael Espindola bad440742e add blx 
llvm-svn: 31037
 2006-10-18 16:21:43 +00:00
Rafael Espindola 01dd97a8aa add isTerminatortto b and bcond 
llvm-svn: 31036
 2006-10-18 16:20:57 +00:00
Rafael Espindola 3968263ca8 add the FPUnaryOp and DFPUnaryOp classes 
llvm-svn: 31013
 2006-10-17 20:45:22 +00:00
Rafael Espindola 99bf133d58 add FABSS and FABSD 
llvm-svn: 31012
 2006-10-17 20:33:13 +00:00
Rafael Espindola 2d7d14262a remove extra [] in stores 
llvm-svn: 31008
 2006-10-17 18:29:14 +00:00
Rafael Espindola 19398ec86e initial implementation of addressing mode 5 
llvm-svn: 31002
 2006-10-17 18:04:53 +00:00
Rafael Espindola 418c8e69bb add FSTD and FSTS 
llvm-svn: 30996
 2006-10-17 13:36:07 +00:00
Rafael Espindola c31ee94920 add FCPYS and FCPYD 
llvm-svn: 30995
 2006-10-17 13:13:23 +00:00
Rafael Espindola afdd47ace4 add fdivs e fdivd 
llvm-svn: 30988
 2006-10-16 21:50:04 +00:00
Rafael Espindola f719c5f43d expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS 
llvm-svn: 30987
 2006-10-16 21:10:32 +00:00
Rafael Espindola e341d60f53 define the DFPBinOp class 
llvm-svn: 30981
 2006-10-16 18:39:22 +00:00
Rafael Espindola f63752f94b add the FPBinOp class 
llvm-svn: 30980
 2006-10-16 18:32:36 +00:00
Rafael Espindola b23dc14135 define the Addr1BinOp class 
llvm-svn: 30979
 2006-10-16 18:18:14 +00:00
Rafael Espindola 203922d083 define the IntBinOp class and use it to implement the multiply instructions 
llvm-svn: 30978
 2006-10-16 17:57:20 +00:00
Rafael Espindola c4abf8dc5b fix assembly syntax 
llvm-svn: 30977
 2006-10-16 17:38:12 +00:00
Rafael Espindola 677ee8390d implement LDRB, LDRSB, LDRH and LDRSH 
llvm-svn: 30976
 2006-10-16 17:17:22 +00:00
Rafael Espindola 595dc4c884 implement smull and umull 
llvm-svn: 30975
 2006-10-16 16:33:29 +00:00
Rafael Espindola 4c1baf1528 fix some fp condition codes 
use non trapping comparison instructions

llvm-svn: 30962
 2006-10-14 13:42:53 +00:00
Rafael Espindola 5ab3166f74 add FNEGS and FNEGD 
llvm-svn: 30932
 2006-10-13 17:37:35 +00:00
Rafael Espindola d6050c3149 add SBCS and SUBS 
llvm-svn: 30930
 2006-10-13 17:19:20 +00:00
Rafael Espindola 3874a168d0 implement unordered floating point compares 
llvm-svn: 30928
 2006-10-13 13:14:59 +00:00
Chris Lattner 8c9422c4b8 mark call adjustments as modifying the SP 
llvm-svn: 30911
 2006-10-12 18:00:26 +00:00
Evan Cheng 577ef7694e Add properties to ComplexPattern. 
llvm-svn: 30891
 2006-10-11 21:03:53 +00:00
Rafael Espindola 8429e1f6c3 uint <-> double conversion 
llvm-svn: 30862
 2006-10-10 20:38:57 +00:00
Rafael Espindola b5f1ff336a add fp sub 
llvm-svn: 30859
 2006-10-10 19:35:01 +00:00
Rafael Espindola 57d109fb08 add double <-> int conversion 
llvm-svn: 30858
 2006-10-10 18:55:14 +00:00
Rafael Espindola d1a4ea41c9 compare doubles 
llvm-svn: 30856
 2006-10-10 16:33:47 +00:00
Rafael Espindola d15c892433 initial support for fp compares. Unordered compares not implemented yet 
llvm-svn: 30854
 2006-10-10 12:56:00 +00:00
Rafael Espindola 9e29ec371a add float -> double and double -> float conversion 
llvm-svn: 30835
 2006-10-09 17:50:29 +00:00
Rafael Espindola 396b4a6b7b add ADDS and ADCS 
llvm-svn: 30830
 2006-10-09 17:18:28 +00:00
Rafael Espindola b50938866b implement FUITOS and FUITOD 
llvm-svn: 30803
 2006-10-07 14:24:52 +00:00
Rafael Espindola 58c368bc4f implement FLDD 
llvm-svn: 30802
 2006-10-07 14:03:39 +00:00
Rafael Espindola 40f5dd27f0 implement fadds, faddd, fmuls and fmuld 
llvm-svn: 30801
 2006-10-07 13:46:42 +00:00
Rafael Espindola aa2a12f1a2 add optional input flag to FMRRD 
llvm-svn: 30774
 2006-10-06 20:33:26 +00:00
Rafael Espindola e04df41ca2 implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL 
implement FMDRR
add support for f64 function arguments

llvm-svn: 30754
 2006-10-05 16:48:49 +00:00
Rafael Espindola 68d238801c Implement floating point constants 
llvm-svn: 30704
 2006-10-03 17:27:58 +00:00
Rafael Espindola d55c0a41df fix the names of the 64bit fp register 
initial support for returning 64bit floating point numbers

llvm-svn: 30692
 2006-10-02 19:30:56 +00:00
Rafael Espindola 53f78be49e add floating point registers 
implement SINT_TO_FP

llvm-svn: 30673
 2006-09-29 21:20:16 +00:00
Rafael Espindola 3130a756ef add shifts to addressing mode 1 
llvm-svn: 30291
 2006-09-13 12:09:43 +00:00
Rafael Espindola c7829d62c0 implement SRL and MUL 
llvm-svn: 30262
 2006-09-11 19:24:19 +00:00
Rafael Espindola e45a79a9e2 partial implementation of the ARM Addressing Mode 1 
llvm-svn: 30252
 2006-09-11 17:25:40 +00:00
Rafael Espindola d11fb5d13b implement shl and sra 
llvm-svn: 30191
 2006-09-08 17:36:23 +00:00
Rafael Espindola 4443c7d60a add the eor (xor) instruction 
llvm-svn: 30189
 2006-09-08 16:59:47 +00:00
Rafael Espindola 778769aafb implement unconditional branches 
fix select.ll

llvm-svn: 30186
 2006-09-08 12:47:03 +00:00
Rafael Espindola abd8bcbe5e add the orr instruction 
llvm-svn: 30125
 2006-09-06 18:03:12 +00:00
Rafael Espindola 29e4875f57 add the "eq" condition code 
implement a movcond instruction

llvm-svn: 29857
 2006-08-24 17:19:08 +00:00
Rafael Espindola fe03fe9bf4 create a generic bcond instruction that has a conditional code argument 
llvm-svn: 29856
 2006-08-24 16:13:15 +00:00
Rafael Espindola e08b9853cc initial support for branches 
llvm-svn: 29854
 2006-08-24 13:45:55 +00:00
Rafael Espindola d0dee77718 initial support for select 
llvm-svn: 29802
 2006-08-21 22:00:32 +00:00
Rafael Espindola 9d77f9fd24 add the and instruction 
llvm-svn: 29793
 2006-08-21 13:58:59 +00:00
Rafael Espindola c3ed77e1b9 add a "load effective address" 
llvm-svn: 29748
 2006-08-17 17:09:40 +00:00
Rafael Espindola bf8e751488 Declare the callee saved regs 
Remove the hard coded store and load of the link register
Implement ARMFrameInfo

llvm-svn: 29727
 2006-08-16 14:43:33 +00:00
Evan Cheng 81b645a76b CALLSEQ_* produces chain even if that's not needed. 
llvm-svn: 29603
 2006-08-11 09:03:33 +00:00
Rafael Espindola 8c41f99e6f change the addressing mode of the str instruction to reg+imm 
llvm-svn: 29571
 2006-08-08 20:35:03 +00:00
Rafael Espindola a94b9e33af add and use ARMISD::RET_FLAG 
llvm-svn: 29499
 2006-08-03 17:02:20 +00:00
Rafael Espindola 8b7bd8264b start comments with # 
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save

llvm-svn: 29451
 2006-08-01 18:53:10 +00:00
Rafael Espindola 976c93a110 implemented sub 
correctly update the stack pointer in the prologue and epilogue

llvm-svn: 29244
 2006-07-21 12:26:16 +00:00
Rafael Espindola bf3a17cd32 initial prologue and epilogue implementation. Need to define add and sub before finishing it :-) 
llvm-svn: 29175
 2006-07-18 17:00:30 +00:00
Rafael Espindola 75269be065 skeleton of a lowerCall implementation for ARM 
llvm-svn: 29159
 2006-07-16 01:02:57 +00:00
Rafael Espindola 185c5c2bdf add the memri memory operand 
this makes it possible for ldr instructions with non-zero immediate

llvm-svn: 29103
 2006-07-11 11:36:48 +00:00
Rafael Espindola e40a7e2aa2 create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
 2006-07-10 01:41:35 +00:00
Rafael Espindola a88966fd5e initial implementation of ARMRegisterInfo::eliminateFrameIndex 
fixes test/Regression/CodeGen/ARM/ret_arg5.ll

llvm-svn: 28854
 2006-06-18 00:08:07 +00:00
Rafael Espindola 5bc60da112 Expand ret into "CopyToReg;BRIND" 
llvm-svn: 28559
 2006-05-30 17:33:19 +00:00
Rafael Espindola 87bc1a9b0b On ARM, alignment is in bits 
Add lr as a hard coded operand of bx

llvm-svn: 28494
 2006-05-26 10:56:17 +00:00
Rafael Espindola b15597b59a implement movri 
add a stub LowerFORMAL_ARGUMENTS

llvm-svn: 28388
 2006-05-18 21:45:49 +00:00
Rafael Espindola ffdc24b847 added a skeleton of the ARM backend 
llvm-svn: 28301
 2006-05-14 22:18:28 +00:00