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Author SHA1 Message Date
Chris Lattner c408558638 When rewriting frame instructions, emit the appropriate small-immediate 
instruction when possible.

llvm-svn: 25938
 2006-02-03 18:20:04 +00:00
Chris Lattner a23b04acdb remove some target-indep and implemented notes 
llvm-svn: 25930
 2006-02-03 06:22:11 +00:00
Chris Lattner a1eac9b978 the X86 backend no longer needs to delete its own noop copies 
llvm-svn: 25923
 2006-02-03 02:59:58 +00:00
Chris Lattner 5123346708 fix operand numbers 
llvm-svn: 25915
 2006-02-02 20:38:12 +00:00
Chris Lattner bb53acd03c Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) 
llvm-svn: 25913
 2006-02-02 20:12:32 +00:00
Chris Lattner 246ee44c8f implement isStoreToStackSlot 
llvm-svn: 25911
 2006-02-02 20:00:41 +00:00
Chris Lattner 0acc90c67e add a method 
llvm-svn: 25910
 2006-02-02 19:57:16 +00:00
Chris Lattner d8208c3665 more notes 
llvm-svn: 25908
 2006-02-02 19:43:28 +00:00
Chris Lattner d3f033e8e0 add a note, I have no idea how important this is. 
llvm-svn: 25907
 2006-02-02 19:16:34 +00:00
Chris Lattner 4b2ec8af23 implemented, testcase here: test/Regression/CodeGen/X86/compare-add.ll 
llvm-svn: 25899
 2006-02-02 06:36:48 +00:00
Evan Cheng d3908f79cb Update. 
llvm-svn: 25896
 2006-02-02 02:40:17 +00:00
Evan Cheng d8fba3a1ee Fix a erroneous comment. 
llvm-svn: 25894
 2006-02-02 00:28:23 +00:00
Chris Lattner 6132a87cf4 more notes 
llvm-svn: 25890
 2006-02-01 23:38:08 +00:00
Evan Cheng b3ea2677a4 Tell codegen MOVAPSrr and MOVAPDrr are copies. 
llvm-svn: 25889
 2006-02-01 23:03:16 +00:00
Evan Cheng f1ed826c2a Added SSE entries to foldMemoryOperand(). 
llvm-svn: 25888
 2006-02-01 23:02:25 +00:00
Evan Cheng 8b40cde148 Rearrange code to my liking. :) 
llvm-svn: 25887
 2006-02-01 23:01:57 +00:00
Chris Lattner 2f7650f9dc another note 
llvm-svn: 25883
 2006-02-01 21:44:48 +00:00
Nate Begeman 7e7f439f85 Fix some of the stuff in the PPC README file, and clean up legalization 
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.

llvm-svn: 25875
 2006-02-01 07:19:44 +00:00
Chris Lattner 3da1bb520e add a note, I'll take care of this after nate commits his big patch 
llvm-svn: 25873
 2006-02-01 06:40:32 +00:00
Evan Cheng 9e350cd6ad - Use xor to clear integer registers (set R, 0). 
- Added a new format for instructions where the source register is implied
  and it is same as the destination register. Used for pseudo instructions
  that clear the destination register.

llvm-svn: 25872
 2006-02-01 06:13:50 +00:00
Evan Cheng c404b5748c Remove another entry. 
llvm-svn: 25871
 2006-02-01 06:08:48 +00:00
Chris Lattner b0a76b0981 Another regression from the pattern isel 
llvm-svn: 25867
 2006-02-01 01:44:25 +00:00
Evan Cheng a24617f5d4 Return's chain should be matching either the chain produced by the 
value or the chain going into the load.

llvm-svn: 25863
 2006-02-01 01:19:32 +00:00
Evan Cheng e1ce4d7115 When folding a load into a return of SSE value, check the chain to 
ensure the memory location has not been clobbered.

llvm-svn: 25861
 2006-02-01 00:20:21 +00:00
Evan Cheng bc1fcd074e Remove an item. It's done. 
llvm-svn: 25860
 2006-02-01 00:15:53 +00:00
Evan Cheng 5659ca8f47 Be smarter about whether to store the SSE return value in memory. If 
it is already available in memory, do a fld directly from there.

llvm-svn: 25859
 2006-01-31 23:19:54 +00:00
Chris Lattner 64387c3e9c turning these into 'adds' would require extra copies 
llvm-svn: 25858
 2006-01-31 22:59:46 +00:00
Evan Cheng 72d5c256c9 - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*. 
- Use XORP* to implement fneg.

llvm-svn: 25857
 2006-01-31 22:28:30 +00:00
Evan Cheng a91eb48547 Remove entries on fabs and fneg. These are done. 
llvm-svn: 25856
 2006-01-31 22:26:21 +00:00
Chris Lattner c642aa5e1c * Fix 80-column violations 
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.

llvm-svn: 25854
 2006-01-31 19:43:35 +00:00
Evan Cheng 2dd217b88f Added custom lowering of fabs 
llvm-svn: 25831
 2006-01-31 03:14:29 +00:00
Chris Lattner d916e78b0a Another high-prio selection performance bug 
llvm-svn: 25828
 2006-01-31 02:10:06 +00:00
Chris Lattner 2b70a6f853 more mumbling 
llvm-svn: 25826
 2006-01-31 00:45:37 +00:00
Chris Lattner b521361fb9 add some notes 
llvm-svn: 25825
 2006-01-31 00:20:38 +00:00
Evan Cheng 45df7f84ff Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip 
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.

llvm-svn: 25824
 2006-01-30 23:41:35 +00:00
Evan Cheng 08390f6a21 i64 -> f32, f32 -> i64 and some clean up. 
llvm-svn: 25818
 2006-01-30 22:13:22 +00:00
Evan Cheng 5b97fcf0f5 Always use FP stack instructions to perform i64 to f64 as well as f64 to i64 
conversions. SSE does not have instructions to handle these tasks.

llvm-svn: 25817
 2006-01-30 08:02:57 +00:00
Chris Lattner f0b24d2dc0 Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. 
llvm-svn: 25803
 2006-01-30 04:09:27 +00:00
Chris Lattner c6fa0282d2 adjust prototype 
llvm-svn: 25798
 2006-01-30 03:49:07 +00:00
Chris Lattner 3c6a950653 add another note 
llvm-svn: 25789
 2006-01-29 09:46:06 +00:00
Chris Lattner dabee1f655 add some performance notes from looking at sgefa 
llvm-svn: 25788
 2006-01-29 09:42:20 +00:00
Chris Lattner 7c7cbde0e5 add a high-priority SSE issue from sgefa 
llvm-svn: 25787
 2006-01-29 09:14:47 +00:00
Chris Lattner 5a7a22c9dd add a missed optimization 
llvm-svn: 25786
 2006-01-29 09:08:15 +00:00
Reid Spencer 0c05a2c99c Add a note about lowering llvm.memset, llvm.memcpy, and llvm.memmove to a 
few stores under certain conditions.

llvm-svn: 25777
 2006-01-29 06:48:25 +00:00
Chris Lattner 35d20a4c00 remove now-dead code, the legalizer takes care of this for us 
llvm-svn: 25776
 2006-01-29 06:45:31 +00:00
Chris Lattner 132177e103 The FP stack doesn't support UNDEF, ask the legalizer to legalize it 
instead of lying and saying we have it.

llvm-svn: 25775
 2006-01-29 06:44:22 +00:00
Chris Lattner 61c9a8e942 Targets all now request ConstantFP to be legalized into TargetConstantFP. 
'fpimm' in .td files is now TargetConstantFP.

llvm-svn: 25771
 2006-01-29 06:26:08 +00:00
Jeff Cohen 4ab39e43e8 Fix typo. 
llvm-svn: 25760
 2006-01-29 03:45:35 +00:00
Jeff Cohen 8643ea67b1 Flesh out AMD family/models. 
llvm-svn: 25755
 2006-01-28 20:30:18 +00:00
Jeff Cohen 58ca0be9af Correctly determine CPU vendor. 
llvm-svn: 25754
 2006-01-28 19:48:34 +00:00
Jeff Cohen 71287085a1 Use union instead of reinterpret_cast. 
llvm-svn: 25751
 2006-01-28 18:47:32 +00:00
Jeff Cohen b5de47cd9a Fix recognition of Intel CPUs. 
llvm-svn: 25750
 2006-01-28 18:38:20 +00:00
Chris Lattner b3ab2d3a42 Is64Bit reflects the capability of the chip, not an aspect of the target os 
llvm-svn: 25749
 2006-01-28 18:23:48 +00:00
Chris Lattner be08957dc5 Fix a bunch of JIT failures with the new isel 
llvm-svn: 25748
 2006-01-28 18:19:37 +00:00
Jeff Cohen e128d5f724 Improve X86 subtarget support for Windows and AMD. 
llvm-svn: 25747
 2006-01-28 18:09:06 +00:00
Chris Lattner ccd2a20c4b silence a warning 
llvm-svn: 25745
 2006-01-28 10:34:47 +00:00
Chris Lattner dc8bbb6527 make this work on non-native hosts 
llvm-svn: 25734
 2006-01-28 06:05:41 +00:00
Evan Cheng 18243826fd A bit of wisdom from Chris on the last entry. 
llvm-svn: 25715
 2006-01-27 22:54:32 +00:00
Evan Cheng 63045d221b AT&T assembly convention: registers are in lower case. 
llvm-svn: 25714
 2006-01-27 22:53:29 +00:00
Chris Lattner dbfc299915 initialize all instance vars 
llvm-svn: 25711
 2006-01-27 22:37:09 +00:00
Evan Cheng 9857d075b5 Added notes about a x86 isel deficiency. 
llvm-svn: 25706
 2006-01-27 22:11:01 +00:00
Evan Cheng 1073ae07b0 Added a temporary option -enable-x86-sse to enable sse support. It is used by 
llc-beta.

llvm-svn: 25701
 2006-01-27 21:49:34 +00:00
Evan Cheng a814f0b31c Bye bye Pattern ISel, hello DAG ISel. 
llvm-svn: 25700
 2006-01-27 21:26:54 +00:00
Nate Begeman 8c47c3a3b1 Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for 
the same functionality.  This addresses another piece of bug 680.  Next,
on to fixing Alpha VAARG, which I broke last time.

llvm-svn: 25696
 2006-01-27 21:09:22 +00:00
Evan Cheng afab7aa8f2 A better workaround 
llvm-svn: 25692
 2006-01-27 19:30:30 +00:00
Chris Lattner 4be147f456 force sse/3dnow off until they work. This fixes all the x86 failures last night 
llvm-svn: 25690
 2006-01-27 18:30:50 +00:00
Chris Lattner ed2bb8562f Unbreak the JIT with SSE 
llvm-svn: 25688
 2006-01-27 18:27:18 +00:00
Evan Cheng cde9e30bc6 x86 CPU detection and proper subtarget support 
llvm-svn: 25679
 2006-01-27 08:10:46 +00:00
Chris Lattner 1240574609 PHI and INLINEASM are now built-in instructions provided by Target.td 
llvm-svn: 25674
 2006-01-27 01:46:15 +00:00
Jeff Cohen 15a8c15a1f Improve compatibility with VC2005, patch by Morten Ofstad! 
llvm-svn: 25661
 2006-01-26 20:41:32 +00:00
Chris Lattner ebbfb386a5 Improve compatibility with VC2005, patch by Morten Ofstad! 
llvm-svn: 25653
 2006-01-26 19:55:20 +00:00
Evan Cheng 54c13da29c Added preliminary x86 subtarget support. 
llvm-svn: 25645
 2006-01-26 09:53:06 +00:00
Evan Cheng fcdce6d26f Work around some x86 Darwin assembler bugs 
llvm-svn: 25638
 2006-01-26 02:27:43 +00:00
Evan Cheng 944d1e91ea When trying to fold X86::SETCC into a Select, make a copy if it has more than 
one use. This allows more CMOV instructions.

llvm-svn: 25634
 2006-01-26 02:13:10 +00:00
Evan Cheng 97c68f0f5c Remove the uses of STATUS flag register. Rely on node property SDNPInFlag, 
SDNPOutFlag, and SDNPOptInFlag instead.

llvm-svn: 25629
 2006-01-26 00:29:36 +00:00
Nate Begeman e74795cd70 First part of bug 680: 
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.

llvm-svn: 25606
 2006-01-25 18:21:52 +00:00
Evan Cheng 83eeefbbd1 X86 prefer scheduling for reduced register pressure. 
llvm-svn: 25602
 2006-01-25 09:15:17 +00:00
Evan Cheng aff0800fd1 Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it. 
llvm-svn: 25596
 2006-01-25 09:05:09 +00:00
Chris Lattner bc7226a7cc Loosen up these checks to allow direct uses of ESP 
llvm-svn: 25595
 2006-01-25 08:00:36 +00:00
Chris Lattner 27d30a5f42 use ESP directly, not a copy of ESP into some other register for fastcc calls 
llvm-svn: 25584
 2006-01-24 06:14:44 +00:00
Chris Lattner 6f33eaeb81 Emit the copies out of call return registers *after* the ISD::CALLSEQ_END 
node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.

llvm-svn: 25580
 2006-01-24 05:17:12 +00:00
Chris Lattner 68e62a5184 Allow jit-beta to work 
llvm-svn: 25578
 2006-01-24 04:50:48 +00:00
Chris Lattner de02d7727f Add explicit #includes of <iostream> 
llvm-svn: 25515
 2006-01-22 23:41:00 +00:00
Evan Cheng 468fecdc99 Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual). 
Some assemblers can't recognize the aliases.

llvm-svn: 25494
 2006-01-21 02:55:41 +00:00
Chris Lattner 335b46dd20 LowerReturn now doesn't have to handle f32 returns. 
llvm-svn: 25484
 2006-01-20 18:41:25 +00:00
Evan Cheng 0c5de2864f Stop doing that accidental commit. 
llvm-svn: 25474
 2006-01-20 01:14:05 +00:00
Evan Cheng cce748d316 A few more SH{L|R}D peepholes. 
llvm-svn: 25473
 2006-01-20 01:13:30 +00:00
Evan Cheng 9c30bd5e25 Didn't mean to commit the last one. 
llvm-svn: 25469
 2006-01-19 23:27:08 +00:00
Evan Cheng 8591b9f254 Added i16 SH{L|R}D patterns. 
llvm-svn: 25468
 2006-01-19 23:26:24 +00:00
Evan Cheng 3d2cc7e2e9 Avoid generating a redundant setcc. 
llvm-svn: 25457
 2006-01-19 08:52:46 +00:00
Evan Cheng 91007126c2 adc and sbb need an incoming flag to ensure it reads the carry flag 
from add / sub.

llvm-svn: 25444
 2006-01-19 06:53:20 +00:00
Evan Cheng a7bfbe996e Two peepholes: 
(or (x >> c) | (y << (32 - c))) ==> (shrd x, y, c)
(or (x << c) | (y >> (32 - c))) ==> (shld x, y, c)

llvm-svn: 25438
 2006-01-19 01:56:29 +00:00
Evan Cheng 6135a7a546 Didn't mean to check that in. 
llvm-svn: 25436
 2006-01-19 01:52:56 +00:00
Evan Cheng 267ba5965e A obvious typo 
llvm-svn: 25435
 2006-01-19 01:46:14 +00:00
Evan Cheng 621674a19d SRA shift amount must be in i8 
llvm-svn: 25416
 2006-01-18 09:26:46 +00:00
Evan Cheng 4b3774e0a2 If a call return type is i1, insert a truncate from X86::AL to i1. 
llvm-svn: 25415
 2006-01-18 08:08:38 +00:00
Evan Cheng feaed4d107 Fix lowering of calls which return f32 values. 
llvm-svn: 25413
 2006-01-17 21:58:21 +00:00
Evan Cheng 14417ed99c Zero extending load from i1 to i8. 
llvm-svn: 25391
 2006-01-17 07:02:46 +00:00
Evan Cheng 0d5b69f734 SSE does not support i64 SINT_TO_FP (FP stack doesn't either, but we custom 
expand it), so ask legalizer to expand i32 UINT_TO_FP.

llvm-svn: 25386
 2006-01-17 02:32:49 +00:00
Evan Cheng 561881f30a Added a FIXME comment about why FST is currently flagged to fpGETRESULT. 
llvm-svn: 25381
 2006-01-17 00:37:42 +00:00
Evan Cheng bec9d720b0 Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should 
read a flag.

llvm-svn: 25378
 2006-01-17 00:19:47 +00:00
Evan Cheng c14bb1026b More typo's 
llvm-svn: 25375
 2006-01-16 23:26:53 +00:00
Evan Cheng 64eeed27d9 Some typo's 
llvm-svn: 25374
 2006-01-16 22:48:46 +00:00
Evan Cheng 911c68d7a8 Fix FP_TO_INT**_IN_MEM lowering. 
llvm-svn: 25368
 2006-01-16 21:21:29 +00:00
Chris Lattner b2eacf48aa transfer some notes from my email to somewhere useful. 
llvm-svn: 25361
 2006-01-16 17:53:00 +00:00
Evan Cheng 2494ce49f0 Added patterns for 8-bit multiply 
llvm-svn: 25338
 2006-01-15 10:05:20 +00:00
Chris Lattner 78c358d1ad Use the default lowering of ISD::DYNAMIC_STACKALLOC, delete now dead code. 
llvm-svn: 25333
 2006-01-15 09:00:21 +00:00
Chris Lattner 8869c6f782 silence a warning 
llvm-svn: 25322
 2006-01-14 20:11:13 +00:00
Nate Begeman 2fba8a3aaa bswap implementation 
llvm-svn: 25312
 2006-01-14 03:14:10 +00:00
Evan Cheng 3bc25e8a54 A typo. 
llvm-svn: 25307
 2006-01-14 01:18:49 +00:00
Evan Cheng 392c7d2779 Add truncstore i1 patterns. 
llvm-svn: 25296
 2006-01-13 21:45:19 +00:00
Chris Lattner 5f9c134bac Fix a bug in my last X86 checkin, pointed out by cozmic 
llvm-svn: 25293
 2006-01-13 20:19:44 +00:00
Evan Cheng dba84bbc1e LHS = X86ISD::CMOVcc LHS, RHS means LHS = RHS if cc. So the operands must be 
flipped around.

llvm-svn: 25290
 2006-01-13 19:51:46 +00:00
Chris Lattner 1a8d918ef1 Enable X86 support for savestack/restorestack 
llvm-svn: 25278
 2006-01-13 18:00:54 +00:00
Chris Lattner 8e2f52e645 expand unsupported stacksave/stackrestore nodes 
llvm-svn: 25272
 2006-01-13 02:42:53 +00:00
Evan Cheng f00374e4a8 Minor update. 
llvm-svn: 25263
 2006-01-13 01:20:42 +00:00
Evan Cheng d7faa4bae1 More typo's. I need new eye glasses... 
llvm-svn: 25261
 2006-01-13 01:17:24 +00:00
Evan Cheng 731423f36a Oops. Typo. 
llvm-svn: 25260
 2006-01-13 01:06:49 +00:00
Evan Cheng fb22e86c4d Fix a SETCC / BRCOND folding bug. 
llvm-svn: 25259
 2006-01-13 01:03:02 +00:00
Evan Cheng 6305e50ee1 Fix sint_to_fp (fild*) support. 
llvm-svn: 25257
 2006-01-12 22:54:21 +00:00
Evan Cheng c993d4522d Specify transformation from GlobalAddress to TargetGlobalAddress and 
ExternalSymbol to TargetExternalSymbol.

llvm-svn: 25253
 2006-01-12 19:36:31 +00:00
Evan Cheng 84dc9b55f0 X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be 
linked together).

llvm-svn: 25247
 2006-01-12 08:27:59 +00:00
Evan Cheng b94db9e9a4 * Materialize GlobalAddress and ExternalSym with MOV32ri rather than 
LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.

llvm-svn: 25246
 2006-01-12 07:56:47 +00:00
Evan Cheng 6d2ab04463 Added ROTL and ROTR. 
llvm-svn: 25232
 2006-01-11 23:20:05 +00:00
Evan Cheng ae986f1f1e Support for MEMCPY and MEMSET. 
llvm-svn: 25226
 2006-01-11 22:15:48 +00:00
Evan Cheng 2ae799aff0 Select DYNAMIC_STACKALLOC 
llvm-svn: 25225
 2006-01-11 22:15:18 +00:00
Nate Begeman 1b8121b227 Add bswap, rotl, and rotr nodes 
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them

llvm-svn: 25222
 2006-01-11 21:21:00 +00:00
Evan Cheng bc7a0f44bd * Add special entry code main() (to set x87 to 64-bit precision). 
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
  call parmater passing.

llvm-svn: 25207
 2006-01-11 06:09:51 +00:00
Chris Lattner 7c551268d0 implement FP_REG_KILL insertion for the dag-dag instruction selector 
llvm-svn: 25192
 2006-01-11 01:15:34 +00:00
Chris Lattner 29852a58b0 Fit into 80 cols 
llvm-svn: 25191
 2006-01-11 00:46:55 +00:00
Evan Cheng 339edad775 SSE cmov support. 
llvm-svn: 25190
 2006-01-11 00:33:36 +00:00
Evan Cheng efaf5c56fd * fp to sint patterns. 
* fiadd, fisub, etc.

llvm-svn: 25189
 2006-01-10 22:22:02 +00:00
Evan Cheng 73a1ad975e FP_TO_INT*_IN_MEM and x87 FP Select support. 
llvm-svn: 25188
 2006-01-10 20:26:56 +00:00
Evan Cheng 7c4486215f * Added undef patterns. 
* Some reorg.

llvm-svn: 25163
 2006-01-09 23:10:28 +00:00
Evan Cheng 12181af0c7 More typos 
llvm-svn: 25162
 2006-01-09 22:29:54 +00:00
Evan Cheng 77fa9195cd typo 
llvm-svn: 25160
 2006-01-09 20:49:21 +00:00
Evan Cheng 9c249c37f8 Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. 
llvm-svn: 25158
 2006-01-09 18:33:28 +00:00
Evan Cheng 92e2797ce2 * Added integer div / rem. 
* Fixed a load folding bug.

llvm-svn: 25136
 2006-01-06 23:19:29 +00:00
Evan Cheng 10d2790d50 ISEL code for MULHU, MULHS, and UNDEF. 
llvm-svn: 25132
 2006-01-06 20:36:21 +00:00
Chris Lattner efbb8da3f5 silence a bogus gcc warning 
llvm-svn: 25129
 2006-01-06 17:56:38 +00:00
Evan Cheng 53dd0ac226 Addd (shl x, 1) ==> (shl x, x) peepholes. 
llvm-svn: 25123
 2006-01-06 02:31:59 +00:00
Evan Cheng b03f9b32d2 fold (shl x, 1) -> (add x, x) 
llvm-svn: 25120
 2006-01-06 01:06:31 +00:00
Evan Cheng 172fce7050 * Fast call support. 
* FP cmp, setcc, etc.

llvm-svn: 25117
 2006-01-06 00:43:03 +00:00
Evan Cheng a5ae6e8320 Added ConstantFP patterns. 
llvm-svn: 25108
 2006-01-05 02:08:37 +00:00
Jim Laskey deeafa0f00 Had expand logic backward. 
llvm-svn: 25105
 2006-01-05 01:47:43 +00:00
Jim Laskey 762e9ec06c Added initial support for DEBUG_LABEL allowing debug specific labels to be 
inserted in the code.

llvm-svn: 25104
 2006-01-05 01:25:28 +00:00
Evan Cheng 45e19098a6 DAG based isel call support. 
llvm-svn: 25103
 2006-01-05 00:27:02 +00:00
Chris Lattner 8258489ca4 Fix a problem duraid pointed out to me compiling kc++ with -enable-x86-fastcc 
llvm-svn: 25024
 2005-12-27 03:02:18 +00:00
Evan Cheng 14c53b45f5 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Evan Cheng 782b654e6f Let the helper functions know about X86::FR32RegClass and X86::FR64RegClass. 
llvm-svn: 25004
 2005-12-24 09:48:35 +00:00
Evan Cheng 9ae486047e * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. 
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997
 2005-12-23 22:14:32 +00:00
Evan Cheng 5c59d49630 More X86 floating point patterns. 
llvm-svn: 24990
 2005-12-23 07:31:11 +00:00
Chris Lattner 30107e65c8 make sure bit_convert's are expanded 
llvm-svn: 24979
 2005-12-23 05:15:23 +00:00
Evan Cheng dfad8ed54e Bye bye HACKTROCITY. 
llvm-svn: 24935
 2005-12-22 02:26:21 +00:00
Evan Cheng 9cdc16c6d3 * Fix a GlobalAddress lowering bug. 
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921
 2005-12-21 23:05:39 +00:00
Evan Cheng 02767195bb Oops. Accidentally deleted RET pattern. It's still needed for return void; 
llvm-svn: 24920
 2005-12-21 22:22:16 +00:00
Jim Laskey 9e296bee9a Disengage DEBUG_LOC from non-PPC targets. 
llvm-svn: 24919
 2005-12-21 20:51:37 +00:00
Evan Cheng c1583dbd63 * Added support for X86 RET with an additional operand to specify number of 
bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917
 2005-12-21 20:21:51 +00:00
Chris Lattner 0dcdd83c0e This was meant to go in 
llvm-svn: 24900
 2005-12-21 07:50:26 +00:00
Chris Lattner f431ad4477 Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns 
that were overloaded to work before and after the stackifier runs.  With the
new clean world, it is possible to write patterns for these instructions: woo!

This also adds a few simple patterns here and there, though there are a lot
still missing.  These should be easy to add though. :)

See the comments under "Floating Point Stack Support" for more details on
the new world order.

This patch as absolutely no effect on the generated code, woo!

llvm-svn: 24899
 2005-12-21 07:47:04 +00:00
Chris Lattner 988827a482 Wrap some long lines: no functionality change 
llvm-svn: 24898
 2005-12-21 05:34:58 +00:00
Evan Cheng a2f308fc3e Remove ISD::RET select code. Now tblgen'd. 
llvm-svn: 24889
 2005-12-21 02:41:57 +00:00
Evan Cheng a74ce62746 * Added lowering hook for external weak global address. It inserts a load 
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888
 2005-12-21 02:39:21 +00:00
Evan Cheng 5c0b4df483 SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns. 
llvm-svn: 24886
 2005-12-20 22:59:51 +00:00
Evan Cheng 5815a6e455 Added X86 readport patterns. 
llvm-svn: 24879
 2005-12-20 07:38:38 +00:00
Evan Cheng 6af02635a7 Added a hook to print out names of target specific DAG nodes. 
llvm-svn: 24877
 2005-12-20 06:22:03 +00:00
Evan Cheng 6fc31046aa X86 conditional branch support. 
llvm-svn: 24870
 2005-12-19 23:12:38 +00:00
Evan Cheng 1d9b671de0 It's essential we clear CodeGenMap after isel every basic block! 
llvm-svn: 24867
 2005-12-19 22:36:02 +00:00
Chris Lattner db8e888fb5 eliminate some redundancy 
llvm-svn: 24781
 2005-12-17 19:47:05 +00:00
Evan Cheng 1d71248392 Darwin API issue: indirect load of external and weak symbols. 
llvm-svn: 24775
 2005-12-17 09:13:43 +00:00
Evan Cheng f3b16bc5a0 Remove a few lines of dead code. 
llvm-svn: 24768
 2005-12-17 07:18:44 +00:00
Evan Cheng 7087cd275b Added an idea about any_extend for performance tuning. 
llvm-svn: 24763
 2005-12-17 06:54:43 +00:00
Evan Cheng bc7708c0e8 Added truncate. 
llvm-svn: 24760
 2005-12-17 02:02:50 +00:00
Evan Cheng b06925d1dd Added anyext, modelled as zext on X86. 
llvm-svn: 24759
 2005-12-17 01:47:57 +00:00
Evan Cheng 6b76009393 Added some isel ideas. 
llvm-svn: 24757
 2005-12-17 01:25:19 +00:00
Evan Cheng cb19390ead Added support for cmp, test, and conditional move instructions. 
llvm-svn: 24756
 2005-12-17 01:24:02 +00:00
Evan Cheng 0f68322992 Only lower SELECT when using DAG based isel. 
llvm-svn: 24755
 2005-12-17 01:22:13 +00:00
Evan Cheng 225a4d0d6d X86 lowers SELECT to a cmp / test followed by a conditional move. 
llvm-svn: 24754
 2005-12-17 01:21:05 +00:00
Chris Lattner 9f62a2a51d Don't globalize internal functions 
llvm-svn: 24727
 2005-12-16 00:07:30 +00:00
Evan Cheng 74151ba279 * Promote all 1 bit entities to 8 bit. 
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726
 2005-12-15 19:49:23 +00:00
Evan Cheng 305c6a73b5 Added frameindex, constpool, globaladdr, and externalsym as root nodes of 
leaaddr.

llvm-svn: 24724
 2005-12-15 08:31:04 +00:00
Evan Cheng 00fcb0017e Handling zero extension of 1 bit value. 
llvm-svn: 24722
 2005-12-15 01:02:48 +00:00
Evan Cheng bc9344477e Use MOV8rm to load 1 bit value. 
llvm-svn: 24721
 2005-12-15 00:59:17 +00:00
Evan Cheng 023aef2f31 Fixed a typo: line 2323: MOVSX16rm8 -> MOVZX16rm8. This was the cause fo 12/14/2005 hbd failure. 
llvm-svn: 24717
 2005-12-14 22:28:18 +00:00
Evan Cheng c273900dd8 Added sext and zext patterns. 
llvm-svn: 24705
 2005-12-14 02:22:27 +00:00
Evan Cheng 229f0ee6d7 Add load + store folding srl and sra patterns. 
llvm-svn: 24696
 2005-12-13 07:24:22 +00:00
Chris Lattner 87079884d1 Use the shared asmprinter code for printing special llvm globals 
llvm-svn: 24695
 2005-12-13 06:32:50 +00:00
Chris Lattner 4d80f6e52e Add ELF and darwin support for static ctors and dtors 
llvm-svn: 24693
 2005-12-13 04:53:51 +00:00
Evan Cheng acec857b1a Beautify a few patterns. 
llvm-svn: 24690
 2005-12-13 02:40:18 +00:00
Evan Cheng 89c6db4baf Some shl patterns which do load + store folding. 
llvm-svn: 24689
 2005-12-13 02:34:51 +00:00
Evan Cheng 108beceb0f A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility. 
llvm-svn: 24688
 2005-12-13 01:57:51 +00:00
Evan Cheng ddd5ae5a22 Add and, or, and xor patterns which fold load + stores. 
llvm-svn: 24687
 2005-12-13 01:41:36 +00:00
Evan Cheng e5a94a03e2 Add inc + dec patterns which fold load + stores. 
llvm-svn: 24686
 2005-12-13 01:02:47 +00:00
Evan Cheng bde9e6fca6 Add neg and not patterns which fold load + stores. 
llvm-svn: 24685
 2005-12-13 00:54:44 +00:00
Evan Cheng c414d563f0 Missed a couple redundant explicit type casts. 
llvm-svn: 24684
 2005-12-13 00:25:07 +00:00
Evan Cheng 62e6808aa5 Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc. 
llvm-svn: 24683
 2005-12-13 00:14:11 +00:00
Evan Cheng 86b2cf22d2 * Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands. 
This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.

llvm-svn: 24682
 2005-12-13 00:01:09 +00:00
Evan Cheng 3e52756928 Add some integer mul patterns. 
llvm-svn: 24681
 2005-12-12 23:47:46 +00:00
Evan Cheng af3fe8217a Add some sub patterns. 
llvm-svn: 24675
 2005-12-12 21:54:05 +00:00
Evan Cheng 67ed58e22b When SelectLEAAddr() fails, it shouldn't cause the side effect of having the 
base or index operands being selected.

llvm-svn: 24674
 2005-12-12 21:49:40 +00:00
Evan Cheng bfd259a2b7 For ISD::RET, if # of operands >= 2, try selection the real data dep. operand 
first before the chain.
e.g.
int X;

int foo(int x)
{
  x += X + 37;
  return x;
}

If chain operand is selected first, we would generate:
	movl X, %eax
	movl 4(%esp), %ecx
	leal 37(%ecx,%eax), %eax

rather than
	movl $37, %eax
	addl 4(%esp), %eax
	addl X, %eax

which does not require %ecx. (Due to ADD32rm not matching.)

llvm-svn: 24673
 2005-12-12 20:32:18 +00:00
Chris Lattner d6b17765e4 remove some never-completed and now-obsolete code. 
llvm-svn: 24671
 2005-12-12 20:12:20 +00:00
Evan Cheng e80248b378 Add a few more add / store patterns. e.g. ADD32mi8. 
llvm-svn: 24670
 2005-12-12 19:45:23 +00:00
Evan Cheng 0d6cfee704 * Added X86 store patterns. 
* Added X86 dec patterns.

llvm-svn: 24654
 2005-12-10 00:48:20 +00:00
Evan Cheng 275a3ed80c Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al 
llvm-svn: 24648
 2005-12-09 22:48:48 +00:00
Evan Cheng f039648614 Added explicit type field to ComplexPattern. 
llvm-svn: 24637
 2005-12-08 02:15:07 +00:00
Evan Cheng c9fab31098 * Added intelligence to X86 LEA addressing mode matching routine so it returns 
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.

llvm-svn: 24635
 2005-12-08 02:01:35 +00:00
Chris Lattner 3225733e65 X86 doesn't support sextinreg for 8-bit things either. 
llvm-svn: 24631
 2005-12-07 17:59:14 +00:00
Evan Cheng c0c190239d Remove unnecessary let hasCtrlDep=1 now it can be inferred. 
llvm-svn: 24611
 2005-12-05 23:09:43 +00:00
Chris Lattner 3c0b8f577d Several things: 
1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly.  The port number really
   *is* a 16-bit value, but the patterns should only match if the number
   is 0-255.  Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
   i8, not an i16 as they were believed to be before.  This previous fib
   stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.

llvm-svn: 24599
 2005-12-05 02:40:25 +00:00
Evan Cheng 95cb763818 Added isel patterns for RET, JMP, and WRITEPORT. 
llvm-svn: 24588
 2005-12-04 08:19:43 +00:00
Chris Lattner 7e79292fef Fix PR672 another way which should be more robust 
llvm-svn: 24585
 2005-12-04 06:03:50 +00:00
Chris Lattner ecfc7e56c5 Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672. 
This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on.  Given a clean nightly tester run, we should be able to turn it
on by default!

llvm-svn: 24578
 2005-12-03 07:15:55 +00:00
Chris Lattner 986cb40953 add a note 
llvm-svn: 24572
 2005-12-02 00:11:20 +00:00
Nate Begeman 006bb04f3a Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.

llvm-svn: 24563
 2005-12-01 04:51:06 +00:00
Evan Cheng 4b02426130 Proper support for shifts with register shift value. 
llvm-svn: 24559
 2005-12-01 00:43:55 +00:00
Chris Lattner af2e0373dd SelectNodeTo now returns its result, we must pay attention to it. 
llvm-svn: 24550
 2005-11-30 22:59:19 +00:00
Nate Begeman 11695c0537 Fix a typo in my latest change 
llvm-svn: 24542
 2005-11-30 18:57:39 +00:00
Nate Begeman 6f8c1ace6e No longer track value types for asm printer operands, and remove them as 
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.

llvm-svn: 24541
 2005-11-30 18:54:35 +00:00
Chris Lattner 9c7af08bc9 Fix a bug in a recent patch that broke shifts 
llvm-svn: 24526
 2005-11-30 05:11:18 +00:00
Evan Cheng 4eb7af9bc9 Added support to STORE and shifts to DAG to DAG isel. 
llvm-svn: 24525
 2005-11-30 02:51:20 +00:00
Evan Cheng d2cb70513d Fixed a minor bug: - -offset != offset iff offset == MININT 
llvm-svn: 24522
 2005-11-30 01:59:00 +00:00
Evan Cheng 72ab335858 Add more X86 ISel patterns. 
llvm-svn: 24520
 2005-11-29 19:38:52 +00:00
Chris Lattner 9c415364cf No targets support line number info yet. 
llvm-svn: 24513
 2005-11-29 06:16:21 +00:00
Chris Lattner 820c94e467 Add a missed optimization 
llvm-svn: 24495
 2005-11-28 04:52:39 +00:00
Chris Lattner ac6cb46429 Use HasDotTypeDotSizeDirective instead of forELF 
llvm-svn: 24481
 2005-11-21 23:06:54 +00:00
Chris Lattner 78161dbc84 Remove a level of indentation by using a continue. 
llvm-svn: 24479
 2005-11-21 22:48:18 +00:00
Chris Lattner 40f8c8450d Simplify the subtarget info, allow the asmwriter to do some target sensing 
based on TargetType.

llvm-svn: 24478
 2005-11-21 22:43:58 +00:00
Chris Lattner 99be8f766f Use subtarget information computed by X86Subtarget instead of rolling our own. 
llvm-svn: 24477
 2005-11-21 22:39:40 +00:00
Chris Lattner 3eb876117a Make the X86 subtarget compute the basic target type: ELF, Cygwin, Darwin, 
or native Win32

llvm-svn: 24476
 2005-11-21 22:31:58 +00:00
Chris Lattner ebc39f5a9c Add a forELF flag, allowing the removal of forCygwin and simplification of 
conditionals.

llvm-svn: 24475
 2005-11-21 22:19:48 +00:00
Chris Lattner 7df25ab429 simplify and genericize this code 
llvm-svn: 24473
 2005-11-21 19:50:31 +00:00
Chris Lattner 4a7eb5132b prune #include 
llvm-svn: 24468
 2005-11-21 08:33:17 +00:00
Chris Lattner 8a5f3c1b68 Switch to using the shared constant pool printer, along with using shorter 
CPI ids

llvm-svn: 24467
 2005-11-21 08:32:23 +00:00
Chris Lattner 99946fb63f Adjust to capitalized AsmPrinter method names 
llvm-svn: 24456
 2005-11-21 07:51:23 +00:00
Chris Lattner d365627d3e Use PrivateGlobalPrefix for basic block labels. This allows the x86 darwin 
port to properly use L for the bb prefix instead of .

llvm-svn: 24454
 2005-11-21 07:43:59 +00:00
Chris Lattner 050bf2faf8 convert the rest of this over to use SwitchSection 
llvm-svn: 24448
 2005-11-21 07:16:34 +00:00
Chris Lattner 024e32e118 Start using the AsmPrinter shared SwitchSection code. This allows the X86 
backend to implement global variables in sections.

llvm-svn: 24447
 2005-11-21 07:11:11 +00:00
Chris Lattner 2c0b435ba6 Rename SwitchSection -> switchSection to avoid conflicting with a future 
change.

llvm-svn: 24443
 2005-11-21 06:55:27 +00:00
Chris Lattner 618981fd03 Naturally align doubles in the constant pool, set PrivateGlobalPrefix on 
darwin, use it when printing the constant pool indices so the labels are
appropriately private, emit cp entries to .const instead of .data on darwin
and only emit a single .section for the constant pool, not one for each
entry.

llvm-svn: 24440
 2005-11-21 06:46:22 +00:00
Chris Lattner 6c1ca888d4 Lower READCYCLECOUNTER correctly, preserving the chain result 
llvm-svn: 24438
 2005-11-20 22:57:19 +00:00
Chris Lattner d1061ac8d1 encode rdtsc correctly 
llvm-svn: 24435
 2005-11-20 22:13:18 +00:00
Chris Lattner 6df9e11989 use chain operands to ensure the copies don't wander from the rdtsc instruction. 
llvm-svn: 24434
 2005-11-20 22:01:40 +00:00
Andrew Lenharth 0bf68ae434 The second patch of X86 support for read cycle counter. 
llvm-svn: 24430
 2005-11-20 21:41:10 +00:00
Chris Lattner d7102c4980 Teach the x86 backend about the register constraints of its addressing mode. 
Patch by Evan Cheng

llvm-svn: 24423
 2005-11-19 07:01:30 +00:00
Chris Lattner 3f0f71b92b Add load and other support to the dag-dag isel. Patch contributed by Evan 
Cheng!

llvm-svn: 24419
 2005-11-19 02:11:08 +00:00
Chris Lattner 57ce97862d add more patterns, patch by Evan Cheng. 
llvm-svn: 24406
 2005-11-18 01:04:42 +00:00
Chris Lattner 2bf458af92 Add patterns for some 16-bit immediate instructions, patch contributed by 
Evan Cheng.

llvm-svn: 24384
 2005-11-17 02:01:55 +00:00
Chris Lattner 5930d3df3d Add patterns for several simple instructions that take i32 immediates. 
Patch contributed by Evan Cheng!

llvm-svn: 24382
 2005-11-16 22:59:19 +00:00
Chris Lattner 655e7dfd0d initial step at adding a dag-to-dag isel for X86 backend. Patch contributed 
by Evan Cheng!

llvm-svn: 24371
 2005-11-16 01:54:32 +00:00
Chris Lattner 76ac068568 Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch 
contributed by Evan Cheng.

llvm-svn: 24358
 2005-11-15 00:40:23 +00:00
Chris Lattner b28f214033 Add a new option to indicate we want the code generator to emit code quickly,not spending tons of time microoptimizing it. This is useful for an -O0style of build. 
llvm-svn: 24233
 2005-11-08 02:11:51 +00:00
Chris Lattner b54070745e add a note that Nate mentioned last week 
llvm-svn: 23898
 2005-10-23 21:44:59 +00:00
Chris Lattner 2e81fba9cd Put some of my random notes somewhere public 
llvm-svn: 23897
 2005-10-23 19:52:42 +00:00
Nate Begeman 4dd383120f Invert the TargetLowering flag that controls divide by consant expansion. 
Add a new flag to TargetLowering indicating if the target has really cheap
  signed division by powers of two, make ppc use it.  This will probably go
  away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.

llvm-svn: 23853
 2005-10-21 00:02:42 +00:00
Nate Begeman c0896117d3 Remove some dead code now that the dag combiner exists. 
llvm-svn: 23754
 2005-10-15 22:08:02 +00:00
Nate Begeman 9d7008b08d Properly split f32 and f64 into separate register classes for scalar sse fp 
fixing a bunch of nasty hackery

llvm-svn: 23735
 2005-10-14 22:06:00 +00:00
Chris Lattner 9982da2703 silence some warnings 
llvm-svn: 23594
 2005-10-02 16:29:36 +00:00
Chris Lattner bb1c9ecb17 simplify this code using the new regclass info passed in 
llvm-svn: 23557
 2005-09-30 17:12:38 +00:00
Chris Lattner a654525c1c Pass extra regclasses into spilling code 
llvm-svn: 23537
 2005-09-30 01:29:42 +00:00
Chris Lattner 0815dcae3f Add FP versions of the binary operators, keeping the int and fp worlds seperate. 
Though I have done extensive testing, it is possible that this will break
things in configs I can't test.  Please let me know if this causes a problem
and I'll fix it ASAP.

llvm-svn: 23505
 2005-09-28 22:29:17 +00:00
Chris Lattner de3c87a2ab Implement the isLoadFromStackSlot interface 
llvm-svn: 23387
 2005-09-19 05:23:44 +00:00
Chris Lattner 2e84be22a8 give all operands names 
llvm-svn: 23356
 2005-09-14 21:10:24 +00:00
Chris Lattner b42e962d23 fix a major regression from my patch this afternoon 
llvm-svn: 23347
 2005-09-14 06:06:45 +00:00
Chris Lattner fb96e50b8c This code is no longer needed, it is moved to the target-indep code 
llvm-svn: 23332
 2005-09-13 19:31:44 +00:00
Chris Lattner 210975cfbb Handle any_extend like zext 
llvm-svn: 23202
 2005-09-02 00:16:09 +00:00
Jim Laskey 19058c3989 1. Use SubtargetFeatures in llc/lli. 
2. Propagate feature "string" to all targets.

3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.

llvm-svn: 23192
 2005-09-01 21:38:21 +00:00
Reid Spencer aa7fbca285 Adjust to member variable name change. 
llvm-svn: 23119
 2005-08-27 19:09:48 +00:00
Chris Lattner d0dc6f4299 Fix a bug in my previous checkin 
llvm-svn: 23082
 2005-08-26 17:18:44 +00:00
Chris Lattner c30405e0ee Change ConstantPoolSDNode to actually hold the Constant itself instead of 
putting it into the constant pool.  This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.

llvm-svn: 23081
 2005-08-26 17:15:30 +00:00
Chris Lattner c146940f0d Fix a warning 
llvm-svn: 23031
 2005-08-25 00:05:15 +00:00
Chris Lattner cdc0cbbcd0 Adjust to new livevars interface 
llvm-svn: 22991
 2005-08-23 23:41:14 +00:00
Chris Lattner 7c1c6e06f3 Simplify this code by using LiveVariables::KillsRegister 
llvm-svn: 22988
 2005-08-23 22:49:55 +00:00
Chris Lattner bd26a82051 Split RegisterClass 'Methods' into MethodProtos and MethodBodies 
llvm-svn: 22929
 2005-08-19 19:13:20 +00:00
Chris Lattner 757a770a57 Put register classes into namespaces 
llvm-svn: 22925
 2005-08-19 18:51:57 +00:00
Chris Lattner 8ad3700a3e The simple isel being gone makes this dead! 
llvm-svn: 22914
 2005-08-19 18:32:03 +00:00
Chris Lattner 423d7cbbf8 add a few missing cases 
llvm-svn: 22891
 2005-08-19 00:41:29 +00:00
Chris Lattner e2967ac53d Give ADJCALLSTACKDOWN/UP the correct operands. 
Give a whole bunch of other stuff variable operands, particularly FP.  The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable.  This will have to be fixed before we can dag->dag
the X86 backend.  The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.

llvm-svn: 22890
 2005-08-19 00:38:22 +00:00
Chris Lattner a9d68f140e The variable SAR's only take one operand too 
llvm-svn: 22888
 2005-08-19 00:31:37 +00:00
Chris Lattner 145695927a Stop adding bogus operands to variable shifts on X86. These instructions 
only take one operand.  The other comes implicitly in through CL.

llvm-svn: 22887
 2005-08-19 00:16:17 +00:00
Nate Begeman be1f314a47 Remove the X86 and PowerPC Simple instruction selectors; their time has 
passed.

llvm-svn: 22886
 2005-08-18 23:53:15 +00:00
Chris Lattner 7c76278242 update the backends to work with the new CopyFromReg/CopyToReg/ImplicitDef nodes 
llvm-svn: 22807
 2005-08-16 21:56:37 +00:00
Nate Begeman 371e49515d Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nasty 
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.

llvm-svn: 22805
 2005-08-16 19:49:35 +00:00
Nate Begeman e5394d453d Fix last night's X86 regressions by putting code for SSE in the if(SSE) 
block.  nur.

llvm-svn: 22788
 2005-08-14 18:37:02 +00:00
Nate Begeman 4d959f6627 Fix FP_TO_UINT with Scalar SSE2 now that the legalizer can handle it. We 
now generate the relatively good code sequences:
unsigned short foo(float a) { return a; }
_foo:
        movss 4(%esp), %xmm0
        cvttss2si %xmm0, %eax
        movzwl %ax, %eax
        ret

and
unsigned bar(float a) { return a; }
_bar:
        movss .CPI_bar_0, %xmm0
        movss 4(%esp), %xmm1
        movapd %xmm1, %xmm2
        subss %xmm0, %xmm2
        cvttss2si %xmm2, %eax
        xorl $-2147483648, %eax
        cvttss2si %xmm1, %ecx
        ucomiss %xmm0, %xmm1
        cmovb %ecx, %eax
        ret

llvm-svn: 22786
 2005-08-14 04:36:51 +00:00
Chris Lattner 6ec7745e80 Update the targets to the new SETCC/CondCodeSDNode interfaces. 
llvm-svn: 22729
 2005-08-09 20:21:10 +00:00
Chris Lattner 158acab986 adjust to change in getSubtarget() api 
llvm-svn: 22687
 2005-08-05 21:54:27 +00:00
Nate Begeman 3bcfcd9474 Add Subtarget support to PowerPC. Next up, using it. 
llvm-svn: 22644
 2005-08-04 07:12:09 +00:00
Nate Begeman 8d394eb703 Scalar SSE: load +0.0 -> xorps/xorpd 
Scalar SSE: a < b ? c : 0.0 -> cmpss, andps
Scalar SSE: float -> i16 needs to be promoted

llvm-svn: 22637
 2005-08-03 23:26:28 +00:00
Chris Lattner 6667bdbaca Update to use the new MathExtras.h support for log2 computation. 
Patch contributed by Jim Laskey!

llvm-svn: 22594
 2005-08-02 19:26:06 +00:00
Jeff Cohen 546fd5944e Keep tabs and trailing spaces out. 
llvm-svn: 22565
 2005-07-30 18:33:25 +00:00
Chris Lattner 4913457573 fix a typeo 
llvm-svn: 22561
 2005-07-30 00:43:00 +00:00
Chris Lattner aeef51b6b7 Change the fp to integer code to not perform 2-byte stores followed by 
1 byte loads and other operations.  This is bad for store-forwarding on
common CPUs.  We now do this:

fnstcw WORD PTR [%ESP]
mov %AX, WORD PTR [%ESP]

instead of:

fnstcw WORD PTR [%ESP]
mov %AL, BYTE PTR [%ESP + 1]

llvm-svn: 22559
 2005-07-30 00:17:52 +00:00
Chris Lattner 4738d1b5cd Use a custom expander for all FP to int conversions, as the X86 only has 
FP-to-int-in-memory: this exposes the load from the stored slot to the
selection dag, allowing it to be folded into other operaions.

llvm-svn: 22556
 2005-07-30 00:05:54 +00:00
Andrew Lenharth 2f9c52e194 turn off GOT on archs that didn't use it (not that it appeard to harm them much with it on) 
llvm-svn: 22553
 2005-07-29 23:32:02 +00:00
Chris Lattner bc85c32c73 Implement a FIXME: move a bunch of cruft for handling FP_TO_*INT operations 
that the X86 does not support to the legalizer.  This allows it to be better
optimized, etc, and will help with SSE support.

llvm-svn: 22551
 2005-07-29 01:00:29 +00:00
Chris Lattner 6dc60e859b Don't forget to diddle with the control word when performing an FISTP64. 
llvm-svn: 22550
 2005-07-29 00:54:34 +00:00
Chris Lattner 67756e2e22 Use a custom expander to compile this: 
long %test4(double %X) {
        %tmp.1 = cast double %X to long         ; <long> [#uses=1]
        ret long %tmp.1
}

to this:

_test4:
        sub %ESP, 12
        fld QWORD PTR [%ESP + 16]
        fistp QWORD PTR [%ESP]
        mov %EDX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP]
        add %ESP, 12
        ret

instead of this:

_test4:
        sub %ESP, 28
        fld QWORD PTR [%ESP + 32]
        fstp QWORD PTR [%ESP]
        call ___fixdfdi
        add %ESP, 28
        ret

llvm-svn: 22549
 2005-07-29 00:40:01 +00:00
Jeff Cohen 5f4ef3c5a8 Eliminate all remaining tabs and trailing spaces. 
llvm-svn: 22523
 2005-07-27 06:12:32 +00:00
Jeff Cohen 33a030e36c Eliminate tabs and trailing spaces. 
llvm-svn: 22520
 2005-07-27 05:53:44 +00:00
Andrew Lenharth 111e5e6490 update interface 
llvm-svn: 22498
 2005-07-22 20:49:37 +00:00
Reid Spencer d37d854cb2 For: memory operations -> stores 
This is the first incremental patch to implement this feature. It adds no
functionality to LLVM but setup up the information needed from targets in
order to implement the optimization correctly. Each target needs to specify
the maximum number of store operations for conversion of the llvm.memset,
llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations.
The limit needs to be chosen at the threshold of performance for such an
optimization (generally smallish). The target also needs to specify whether
the target can support unaligned stores for multi-byte store operations.
This helps ensure the optimization doesn't generate code that will trap on
an alignment errors.
More patches to follow.

llvm-svn: 22468
 2005-07-19 04:52:44 +00:00
Nate Begeman 7e74c834c1 Teach the legalizer how to promote SINT_TO_FP to a wider SINT_TO_FP that 
the target natively supports.  This eliminates some special-case code from
the x86 backend and generates better code as well.

For an i8 to f64 conversion, before & after:

_x87 before:
        subl $2, %esp
        movb 6(%esp), %al
        movsbw %al, %ax
        movw %ax, (%esp)
        filds (%esp)
        addl $2, %esp
        ret

_x87 after:
        subl $2, %esp
        movsbw 6(%esp), %ax
        movw %ax, (%esp)
        filds (%esp)
        addl $2, %esp
        ret

_sse before:
        subl $12, %esp
        movb 16(%esp), %al
        movsbl %al, %eax
        cvtsi2sd %eax, %xmm0
        addl $12, %esp
        ret

_sse after:
        subl $12, %esp
        movsbl 16(%esp), %eax
        cvtsi2sd %eax, %xmm0
        addl $12, %esp
        ret

llvm-svn: 22452
 2005-07-16 02:02:34 +00:00
Nate Begeman 8293d0e232 Teach the register allocator that movaps is also a move instruction 
llvm-svn: 22451
 2005-07-16 02:00:20 +00:00
Nate Begeman 57b9ed522d A couple more darwinisms 
llvm-svn: 22450
 2005-07-16 01:59:47 +00:00
Chris Lattner 507a27592f Remove all knowledge of UINT_TO_FP from the X86 backend, relying on the 
legalizer to eliminate them.  With this comes the expected code quality
improvements, such as, for this:

double foo(unsigned short X) { return X; }

we now generate this:

_foo:
        subl $4, %esp
        movzwl 8(%esp), %eax
        movl %eax, (%esp)
        fildl (%esp)
        addl $4, %esp
        ret

instead of this:

_foo:
        subl $4, %esp
        movw 8(%esp), %ax
        movzwl %ax, %eax   ;; Load not folded into this.
        movl %eax, (%esp)
        fildl (%esp)
        addl $4, %esp
        ret

-Chris

llvm-svn: 22449
 2005-07-16 00:28:20 +00:00
Nate Begeman a0b5e035ea Get closer to fully working scalar FP in SSE regs. This gets singlesource 
working, and Olden/power.

llvm-svn: 22441
 2005-07-15 00:38:55 +00:00
Nate Begeman 0f38dc4970 Add support for printing the sse scalar comparison instruction mnemonics. 
llvm-svn: 22440
 2005-07-14 22:52:25 +00:00
Nate Begeman 8dd96ec769 Check in the last of the darwin-specific code necessary to get shootout 
working before modifying the asm printer to use the subtarget info.

llvm-svn: 22408
 2005-07-12 18:34:58 +00:00
Nate Begeman df8946dede Clean up the TargetSubtarget class a bit, removing an unnecessary argument 
to the constructor.

llvm-svn: 22392
 2005-07-12 02:41:19 +00:00
Chris Lattner 351817b1f9 Minor changes to improve comments and fix the build on _WIN32 systems. 
llvm-svn: 22391
 2005-07-12 02:36:10 +00:00
Chris Lattner f873f4d504 Add a note 
llvm-svn: 22390
 2005-07-12 02:35:36 +00:00
Nate Begeman f26625e1de Implement Subtarget support 
Implement the X86 Subtarget.

This consolidates the checks for target triple, and setting options based
on target triple into one place.  This allows us to convert the asm printer
and isel over from being littered with "forDarwin", "forCygwin", etc. into
just having the appropriate flags for each subtarget feature controlling
the code for that feature.

This patch also implements indirect external and weak references in the
X86 pattern isel, for darwin.  Next up is to convert over the asm printers
to use this new interface.

llvm-svn: 22389
 2005-07-12 01:41:54 +00:00
Nate Begeman 83b492b83c Commit some pending darwin changes before subtarget support. 
llvm-svn: 22388
 2005-07-12 01:37:28 +00:00
Chris Lattner 9bdb1c3818 Output .size directives to tell the assembler the size of each function. 
llvm-svn: 22381
 2005-07-11 06:29:14 +00:00
Chris Lattner 0d2f043c41 Fix crazy indentation 
llvm-svn: 22380
 2005-07-11 06:25:47 +00:00
Chris Lattner d831209c34 Refactor things a bit to allow the ELF code emitter to run the X86 machine code emitter 
after itself.

llvm-svn: 22376
 2005-07-11 05:17:48 +00:00
Chris Lattner c3e38f7943 Remove prototype for non-existant function 
llvm-svn: 22372
 2005-07-11 04:20:55 +00:00
Chris Lattner 53676dfd33 Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode. 
This is the last MVTSDNode.

This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.

Also, remove some uses of dyn_cast that should really be cast (which is
cheaper in a release build).

llvm-svn: 22368
 2005-07-10 01:56:13 +00:00
Chris Lattner 36db1ed06f Change TRUNCSTORE to use a VTSDNode operand instead of being an MVTSTDNode 
llvm-svn: 22366
 2005-07-10 00:29:18 +00:00
Nate Begeman b62a4c8da6 Add support for assembling .s files on mac os x for intel 
Add support for running bugpoint on mac os x for intel

llvm-svn: 22351
 2005-07-08 00:23:26 +00:00
Chris Lattner 2e81f65eb8 Restore some code that was accidentally removed by Nate's patch yesterday. 
This fixes the regressions from last night.

llvm-svn: 22344
 2005-07-07 17:12:53 +00:00
Nate Begeman fcd2f76cb6 Fix a typo in my checkin today that caused regressions. Oops! 
llvm-svn: 22341
 2005-07-07 06:32:01 +00:00
Nate Begeman 8a0933608a First round of support for doing scalar FP using the SSE2 ISA extension and 
XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

llvm-svn: 22340
 2005-07-06 18:59:04 +00:00
Chris Lattner a7220851c0 Make several cleanups to Andrews varargs change: 
1. Pass Value*'s into lowering methods so that the proper pointers can be
   added to load/stores from the valist
2. Intrinsics that return void should only return a token chain, not a token
   chain/retval pair.
3. Rename LowerVAArgNext -> LowerVAArg, because VANext is long gone.
4. Now that we have Value*'s available in the lowering methods, pass them
   into any load/stores from the valist that are emitted

llvm-svn: 22339
 2005-07-05 19:58:54 +00:00
Chris Lattner 91ae129b90 Fit to 80 columns 
llvm-svn: 22336
 2005-07-05 17:50:16 +00:00
Chris Lattner 9f6ce0ebb3 Percolate the call up to the right superclass 
llvm-svn: 22330
 2005-07-03 17:34:39 +00:00
Nate Begeman 9a1dc72729 The statistic needs to be in the correct namespace. 
llvm-svn: 22327
 2005-07-01 23:56:38 +00:00
Chris Lattner b97404687a Refactor X86AsmPrinter.cpp into multiple files. Patch contributed 
by Aaron Gray, cleaned up by me.

llvm-svn: 22324
 2005-07-01 22:44:09 +00:00
Nate Begeman 718387e491 Make the x86 asm printer darwin-aware. This mostly entails doing the same 
thing as cygwin most of the time, and printing our alignments in log2
rather than number of bytes.

llvm-svn: 22316
 2005-06-30 00:53:20 +00:00
Nate Begeman db32921535 Initial set of .td file changes necessary to get scalar fp in xmm registers 
working.  The instruction selector changes will hopefully be coming later
this week once they are debugged.  This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87.  As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier.  This leads to significantly
better codegen in several cases.

llvm-svn: 22300
 2005-06-27 21:20:31 +00:00
Chris Lattner 10594206f4 Add support to the X86 backend for emitting ELF files. To use this, we 
currently use: llc t.bc --filetype=obj

This will produce a t.o file which is dumpable with readelf.  Currently
the file produced is empty, but the scaffolding to do more is now in place.

llvm-svn: 22292
 2005-06-27 06:30:12 +00:00
Chris Lattner f11f48ba61 Refactor the addPassesToEmitAssembly interface into a addPassesToEmitFile 
interface.

llvm-svn: 22282
 2005-06-25 02:48:37 +00:00
Andrew Lenharth 253145299b If we support structs as va_list, we must pass pointers to them to va_copy 
See last commit for LangRef, this implements it on all targets.

llvm-svn: 22273
 2005-06-22 21:04:42 +00:00
John Criswell 9cb5a82cdc Fixed indentation. 
llvm-svn: 22270
 2005-06-20 19:59:22 +00:00
Andrew Lenharth 9144ec4764 core changes for varargs 
llvm-svn: 22254
 2005-06-18 18:34:52 +00:00
Chris Lattner 459a9cbe1e silence a bogus warning 
llvm-svn: 22245
 2005-06-17 13:23:32 +00:00
Nate Begeman 85c7d546fe Fix lli linking on Mac OS X 10.4.1 for Intel. 
llvm-svn: 22200
 2005-06-08 01:02:38 +00:00
Reid Spencer 4c07caf9d4 Make sure that Cygwin assembly includes _ as part of function names. 
llvm-svn: 22190
 2005-06-02 21:33:19 +00:00
Nate Begeman 38724d33c1 C'mon everybody, let's modify X86JITInfo.cpp. This time, we add <iostream> 
so that the shiny new use of std::cerr is defined.

llvm-svn: 22156
 2005-05-20 21:29:24 +00:00
Misha Brukman eba2471fa3 Since everyone else has "fixed" this file, might as well join in the fun. 
* Change assert() to std::cerr printout, as it will not appear in opt builds
* Add comments to clarify what #ifdef/#else/#endif match what condition(s)

llvm-svn: 22154
 2005-05-20 19:46:50 +00:00
Chris Lattner 8deafa3378 Fix this a 3rd time :) 
llvm-svn: 22151
 2005-05-20 17:00:21 +00:00
Andrew Lenharth 5d37a3abae fix compilation error due to no abort being defined. There is probably a better way to do this 
llvm-svn: 22150
 2005-05-20 16:34:44 +00:00
Duraid Madina 6e7355e6c1 this seems dead (and broke the ia64 build, so..) 
llvm-svn: 22147
 2005-05-20 06:21:59 +00:00
Jeff Cohen e3948c433c Fix tail call support in VC++ builds 
llvm-svn: 22143
 2005-05-20 01:35:39 +00:00
Chris Lattner 83a6f107fb Fastcc passes arguments in EAX and EDX, make sure the JIT doesn't clobber them 
llvm-svn: 22137
 2005-05-19 06:49:17 +00:00
Chris Lattner 57279597ab Tailcalls require stubs to be emitted. Otherwise, the compilation callback 
doesn't know who 'called' it.

llvm-svn: 22136
 2005-05-19 05:54:33 +00:00
Chris Lattner 1a61fa460f don't reserve space for tailcall arg areas. It explicitly managed. 
llvm-svn: 22050
 2005-05-15 06:07:10 +00:00
Chris Lattner 97e3b65652 Teach reginfo how to deal with ADJSTACKPTRri, allowing us to generate: 
add %ESP, 20
        jmp %EDX  # TAIL CALL

instead of:
        add %ESP, -8
        add %ESP, 28
        jmp %EDX  # TAIL CALL

llvm-svn: 22047
 2005-05-15 05:49:58 +00:00
Chris Lattner dd66a41e0e Implement proper tail calls in the X86 backend for all fastcc->fastcc 
tail calls.

llvm-svn: 22046
 2005-05-15 05:46:45 +00:00
Chris Lattner 3f5a98d1f4 Add markers in the asm file for tail calls, add a new ADJSTACKPTRri 
sorta-pseudo-instruction

llvm-svn: 22042
 2005-05-15 03:10:37 +00:00
Chris Lattner 6b5fa91a63 Yes, calltarget is the operand of the day. 
llvm-svn: 22040
 2005-05-15 01:10:30 +00:00
Chris Lattner 5366c859a7 When emitting the function epilog, check to see if there already a stack 
adjustment.  If so, we merge the adjustment into the existing one.  This
allows us to generate:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        add %ESP, 8
        ret 4

intead of:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        sub %ESP, 4
        add %ESP, 12
        ret 4

for X86/fast-cc-merge-stack-adj.ll

llvm-svn: 22038
 2005-05-14 23:53:43 +00:00
Chris Lattner f0649db870 Add some new instructions 
llvm-svn: 22036
 2005-05-14 23:35:21 +00:00
Chris Lattner 18b2c2f13c Pass i64 values correctly split in reg/mem to fastcc calls. 
This fixes fourinarow with -enable-x86-fastcc.

llvm-svn: 22022
 2005-05-14 12:03:10 +00:00
Chris Lattner 1b3520c90b Use target-specific nodes for calls. This allows the fastcc code to not have 
to do ugly hackery to avoid emitting code like this:

   call foo
   mov vreg, EAX
   adjcallstackup ...

If foo is a fastcc call and if vreg gets spilled, we might end up with this:

   call foo
   mov [ESP+offset], EAX     ;; Offset doesn't consider the 12!
   sub ESP, 12

Which is bad.  The previous hacky code to deal with this was A) gross B) not
good enough.  In particular, it could miss cases and emit the bad code above.
Now we always emit this:

   call foo
   adjcallstackup ...
   mov vreg, EAX

directly.

This makes fastcc with callees poping the stack work much better.  Next
stop (finally!) really is tail calls.

llvm-svn: 22021
 2005-05-14 08:48:15 +00:00
Chris Lattner a36117b360 use a target-specific node and custom expander to lower long->FP to FILD64m. 
This should fix some missing symbols problems on BSD and improve performance
of programs that use that operation.

llvm-svn: 22012
 2005-05-14 06:52:07 +00:00
Chris Lattner 9b29fe2008 Make sure the start of the arg area and the end (after the RA is pushed) 
is always 8-byte aligned for fastcc

llvm-svn: 21995
 2005-05-13 23:49:10 +00:00
Chris Lattner 5011ff0179 fix typo 
llvm-svn: 21991
 2005-05-13 22:46:57 +00:00
Chris Lattner 2267d67941 Fix the problems with callee popped argument lists 
llvm-svn: 21988
 2005-05-13 22:13:49 +00:00
Chris Lattner 79e9fa5de1 Don't emit SAR X, 0 in the case of sdiv Y, 2 
llvm-svn: 21986
 2005-05-13 21:50:27 +00:00
Chris Lattner 7d387d207d Fix UnitTests/2005-05-13-SDivTwo.c 
llvm-svn: 21985
 2005-05-13 21:48:20 +00:00
Chris Lattner c0e369ed66 switch to having the callee pop stack operands for fastcc. This is currently buggy 
do not use

llvm-svn: 21984
 2005-05-13 21:44:04 +00:00
Chris Lattner 1a12476531 allow RETI 
llvm-svn: 21980
 2005-05-13 20:46:35 +00:00
Chris Lattner f27e31d690 Build TAILCALL nodes in LowerCallTo, treat them like normal calls everywhere. 
llvm-svn: 21976
 2005-05-13 20:29:13 +00:00
Chris Lattner 2e77db6af6 Add an isTailCall flag to LowerCallTo 
llvm-svn: 21958
 2005-05-13 18:50:42 +00:00
Chris Lattner 6e4c2302e6 add 'ret imm' instruction 
llvm-svn: 21945
 2005-05-13 17:56:48 +00:00
Chris Lattner 0b17b45a96 Do not CopyFromReg physregs for live-in values. Instead, create a vreg for 
each live in, and copy the regs from the vregs.  As the very first thing we
do in the function, insert copies from the pregs to the vregs.  This fixes
problems where the token chain of CopyFromReg was not enough to allow reordering
of the copyfromreg nodes and other unchained nodes (e.g. div, which clobbers
eax on intel).

llvm-svn: 21932
 2005-05-13 07:38:09 +00:00
Chris Lattner 2dce703710 rename the ADJCALLSTACKDOWN/ADJCALLSTACKUP nodes to be CALLSEQ_START/BEGIN. 
llvm-svn: 21915
 2005-05-12 23:24:06 +00:00
Chris Lattner 7ce7a8fc81 Add a new -enable-x86-fastcc option that enables passing the first 
two integer values in registers for the fastcc calling conv.

llvm-svn: 21912
 2005-05-12 23:06:28 +00:00
Chris Lattner 36674a123e Pass in Calling Convention to use into LowerCallTo 
llvm-svn: 21899
 2005-05-12 19:56:45 +00:00
Chris Lattner b5ff4e5e10 Enable pattern isel by default 
llvm-svn: 21898
 2005-05-12 19:56:09 +00:00
Chris Lattner 05ad4b8369 X86 has more than just 32-bit registers 
llvm-svn: 21857
 2005-05-11 05:00:34 +00:00
Chris Lattner d8145bcd5b Convert feature of the simple isel over for the pattern isel to use. 
llvm-svn: 21840
 2005-05-10 03:53:18 +00:00
Jeff Cohen 915594d884 Silence some VC++ warnings 
llvm-svn: 21838
 2005-05-10 02:22:38 +00:00
Chris Lattner 70ea07cfd2 Implement READPORT/WRITEPORT, implementing the last X86 regression tests 
that were failing with the pattern selector.  Note that the support that
existed in the simple selector was clearly broken in several ways though
(which has also been fixed).

llvm-svn: 21831
 2005-05-09 21:17:38 +00:00
Chris Lattner e53158e21d do not emit illegal instructions 
llvm-svn: 21830
 2005-05-09 21:06:04 +00:00
Chris Lattner 46b5ca4310 Fix the syntax of the i/o instructions, these are obviously unused. 
llvm-svn: 21829
 2005-05-09 20:49:20 +00:00
Chris Lattner 6c6a39a7b8 legalize readio/writeio into load/stores, fixing CodeGen/X86/io.llx with 
the pattern isel.

llvm-svn: 21828
 2005-05-09 20:37:29 +00:00
Chris Lattner 4ccd1f603c restore some non-dead code I removed last night breaking double casts to 
uint

llvm-svn: 21821
 2005-05-09 18:37:02 +00:00
Chris Lattner daa064d8fd Wrap long lines, remove dead code that is now handled by legalize 
llvm-svn: 21811
 2005-05-09 05:40:26 +00:00
Chris Lattner e62661185c Fix FP -> bool casts 
llvm-svn: 21810
 2005-05-09 05:33:18 +00:00
Chris Lattner 6972c31ab5 Fix X86/2005-05-08-FPStackifierPHI.ll: ugly gross hack. 
llvm-svn: 21801
 2005-05-09 03:36:39 +00:00
Andrew Lenharth b8e94c3499 fix typo 
llvm-svn: 21693
 2005-05-04 19:25:37 +00:00
Andrew Lenharth 5e177826fd Implement count leading zeros (ctlz), count trailing zeros (cttz), and count 
population (ctpop).  Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.

More coming soon.

llvm-svn: 21676
 2005-05-03 17:19:30 +00:00
Chris Lattner db68d39a01 Add support for FSIN/FCOS when unsafe math ops are enabled. Patch contributed by 
Morten Ofstad!

llvm-svn: 21632
 2005-04-30 04:25:35 +00:00
Chris Lattner 3b20386551 Add support for llvm.sqrt and sin/cos if unsafe math optimizations are enabled. 
llvm-svn: 21631
 2005-04-30 04:12:40 +00:00
Chris Lattner 014d2c42e7 Add support for FSQRT node, patch contributed by Morten Ofstad 
llvm-svn: 21610
 2005-04-28 22:07:18 +00:00
Chris Lattner 61827484c7 Add some new X86 instrs, patch contributed by Morten Ofstad 
llvm-svn: 21608
 2005-04-28 21:50:05 +00:00
Chris Lattner effaec5436 Codegen fabs/fabsf as FABS. Patch contributed by Morten Ofstad 
llvm-svn: 21607
 2005-04-28 21:48:42 +00:00
Andrew Lenharth 4a73c2cfdc Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends. 
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*.  Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.

llvm-svn: 21599
 2005-04-27 20:10:01 +00:00
Misha Brukman c88330ad13 * Remove trailing whitespace 
* Convert tabs to spaces

llvm-svn: 21426
 2005-04-21 23:38:14 +00:00
Chris Lattner 486a1ec909 Handle stores of global address as stores of immediates. Instead of: 
test1:
        movl $N, %eax
        movl %eax, G
        ret

emit:

test1:
        movl $N, G
        ret

llvm-svn: 21407
 2005-04-21 19:11:03 +00:00
Chris Lattner adcfc1748b Handle (store &GV -> mem) as a store immediate. This often occurs for 
printf format strings and other stuff.  Instead of generating this:

        movl $l1__2E_str_1, %eax
        movl %eax, (%esp)

we now emit:

        movl $l1__2E_str_1, (%esp)

llvm-svn: 21406
 2005-04-21 19:03:24 +00:00
Nate Begeman 779c5cbb44 Make pattern isel default for ppc 
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default

llvm-svn: 21309
 2005-04-15 22:12:16 +00:00
Chris Lattner 60c23bd169 Fix some mysteriously missing {}'s which cause the miscompilation of 
Olden/mst, Ptrdist/bc, Obsequi, etc.

llvm-svn: 21274
 2005-04-13 03:29:53 +00:00
Chris Lattner 248fe6bda2 Z_E_I is gone 
llvm-svn: 21267
 2005-04-13 02:39:05 +00:00
Chris Lattner b59006c4a1 Use live out sets for return values instead of imp_defs, which is cleaner and faster. 
llvm-svn: 21181
 2005-04-09 15:23:56 +00:00
Chris Lattner a3a135a9f7 This target does not support/want ISD::BRCONDTWOWAY 
llvm-svn: 21164
 2005-04-09 03:22:37 +00:00
Chris Lattner 38fd97084b X86 zero extends setcc results 
llvm-svn: 21146
 2005-04-07 19:41:46 +00:00
Chris Lattner bd32728a98 Fix SingleSource/Regression/C/2005-05-06-LongLongSignedShift.c, we were not 
properly sign extending the top of the result of a 64-bit shift right by
a constant > 32.

llvm-svn: 21120
 2005-04-06 20:59:35 +00:00
Chris Lattner 4fbb4af5d1 Add (untested) support for MULHS and MULHU. 
llvm-svn: 21107
 2005-04-06 04:21:07 +00:00
Chris Lattner c21db6b15c add signed versions of the extra precision multiplies 
llvm-svn: 21106
 2005-04-06 04:19:22 +00:00
Chris Lattner 0e0b599d29 add support for FABS and FNEG 
llvm-svn: 21015
 2005-04-02 05:30:17 +00:00
Chris Lattner 0b7e4cd107 This target doesn't support fabs/fneg yet. 
llvm-svn: 21010
 2005-04-02 05:03:24 +00:00
Chris Lattner 2d451658a6 add an fabs instr 
llvm-svn: 21006
 2005-04-02 04:31:56 +00:00
Chris Lattner a31d4c7548 Add support for 64-bit shifts. 
llvm-svn: 21005
 2005-04-02 04:01:14 +00:00
Chris Lattner f4b985d1f6 Add support for ISD::UNDEF to the X86 be 
llvm-svn: 20990
 2005-04-01 22:46:45 +00:00
Chris Lattner 472a265ef6 don't depend on the cfg being set up yet 
llvm-svn: 20936
 2005-03-30 01:10:00 +00:00
Nate Begeman f656525cb6 Change interface to LowerCallTo to take a boolean isVarArg argument. 
llvm-svn: 20842
 2005-03-26 01:29:23 +00:00
Chris Lattner b15317b74a eliminate dead variables, patch contributed by Gabor Greif! 
llvm-svn: 20812
 2005-03-24 17:32:20 +00:00
Nate Begeman 952105220e Remove comments that are now meaningless from the pattern ISels, at Chris's 
request.

llvm-svn: 20804
 2005-03-24 04:39:54 +00:00
Chris Lattner 43832b049e Don't emit two comparisons when comparing a FP value against zero! 
llvm-svn: 20651
 2005-03-17 16:29:26 +00:00
Chris Lattner 7b9020a059 Fix the missing symbols problem Bill was hitting. Patch contributed by 
Bill Wendling!!

llvm-svn: 20649
 2005-03-17 15:38:16 +00:00
Chris Lattner 531f9e92d4 This mega patch converts us from using Function::a{iterator|begin|end} to 
using Function::arg_{iterator|begin|end}.  Likewise Module::g* -> Module::global_*.

This patch is contributed by Gabor Greif, thanks!

llvm-svn: 20597
 2005-03-15 04:54:21 +00:00
Reid Spencer 00658b80fb Patch to make assembly output compatible with mingw compilation (identical 
to cygwin)

llvm-svn: 20520
 2005-03-08 17:02:05 +00:00
Chris Lattner 0ce80cd542 Fix spelling, patch contributed by Gabor Greif! 
llvm-svn: 20343
 2005-02-27 06:18:25 +00:00
Chris Lattner 80c5b97046 Silence some uninit variable warnings. 
llvm-svn: 20284
 2005-02-23 05:57:21 +00:00
Chris Lattner 1b20615173 We can fold promoted and non-promoted loads into divs also! 
llvm-svn: 19835
 2005-01-25 20:35:10 +00:00
Chris Lattner 30607ec66e Fold promoted loads into binary ops for FP, allowing us to generate m32 forms 
of FP ops.

llvm-svn: 19834
 2005-01-25 20:03:11 +00:00
Chris Lattner 0e1de101a1 Silence a warning. 
llvm-svn: 19798
 2005-01-23 23:20:06 +00:00
Chris Lattner debae1e3c3 Allow the FP stackifier to completely ignore functions that do not use FP at 
all.  This should speed up the X86 backend fairly significantly on integer
codes.  Now if only we didn't have to compute livevar still... ;-)

llvm-svn: 19796
 2005-01-23 23:13:59 +00:00
Reid Spencer 30226da5b3 Support Cygwin assembly generation. The cygwin version of Gnu ASsembler 
doesn't support certain directives and symbols on cygwin are prefixed with
an underscore. This patch makes the necessary adjustments to the output.

llvm-svn: 19775
 2005-01-23 03:52:14 +00:00
Chris Lattner e70eb9da7d Speed up folding operations into loads. 
llvm-svn: 19733
 2005-01-21 21:43:02 +00:00
Chris Lattner e1e844c416 The ever-important vanity pass name :) 
llvm-svn: 19731
 2005-01-21 21:35:14 +00:00
Chris Lattner c78776d209 Fix a FIXME: realize that argument stores are all independent (don't alias) 
llvm-svn: 19728
 2005-01-21 19:46:38 +00:00
Chris Lattner 2a631fa406 Implement ADD_PARTS/SUB_PARTS so that 64-bit integer add/sub work. This 
fixes most of the remaining llc-beta failures.

llvm-svn: 19716
 2005-01-20 18:53:00 +00:00
Chris Lattner 5b04f33405 Fix a crash compiling 134.perl. 
llvm-svn: 19711
 2005-01-20 16:50:16 +00:00
Chris Lattner 474aac4da9 Fix a problem where were were literally selecting for INCREASED register 
pressure, not decreases register pressure.  Fix problem where we accidentally
swapped the operands of SHLD, which caused fourinarow to fail.  This fixes
fourinarow.

llvm-svn: 19697
 2005-01-19 17:24:34 +00:00
Chris Lattner 25be208e02 When commuting these instructions, make sure to actually swap the operands too. 
llvm-svn: 19694
 2005-01-19 16:55:52 +00:00
Chris Lattner de87d146ab Implement Regression/CodeGen/X86/rotate.ll: emit rotate instructions (which 
typically cost 1 cycle) instead of shld/shrd instruction (which are typically
6 or more cycles).  This also saves code space.

For example, instead of emitting:

rotr:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %CL, BYTE PTR [%ESP + 8]
        shrd %EAX, %EAX, %CL
        ret
rotli:
        mov %EAX, DWORD PTR [%ESP + 4]
        shrd %EAX, %EAX, 27
        ret

Emit:

rotr32:
        mov %CL, BYTE PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%ESP + 4]
        ror %EAX, %CL
        ret
rotli32:
        mov %EAX, DWORD PTR [%ESP + 4]
        ror %EAX, 27
        ret

We also emit byte rotate instructions which do not have a sh[lr]d counterpart
at all.

llvm-svn: 19692
 2005-01-19 08:07:05 +00:00
Chris Lattner 0edf9535b9 Add rotate instructions. 
llvm-svn: 19690
 2005-01-19 07:50:03 +00:00
Chris Lattner 29f5819158 Match 16-bit shld/shrd instructions as well, implementing shift-double.llx:test5 
llvm-svn: 19689
 2005-01-19 07:37:26 +00:00
Chris Lattner d54845f530 Improve coverage of the X86 instruction set by adding 16-bit shift doubles. 
llvm-svn: 19687
 2005-01-19 07:31:24 +00:00
Chris Lattner 2947801735 Teach the code generator that shrd/shld is commutable if it has an immediate. 
This allows us to generate this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shld %EDX, %EDX, 2
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

Note the magically transmogrifying immediate.

llvm-svn: 19686
 2005-01-19 07:11:01 +00:00
Chris Lattner 41fe201b61 Codegen long >> 2 to this: 
foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shrd %EAX, %EDX, 2
        sar %EDX, 2
        ret

instead of this:

test1:
        mov %ECX, DWORD PTR [%ESP + 4]
        shr %ECX, 2
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %EAX, %EDX
        shl %EAX, 30
        or %EAX, %ECX
        sar %EDX, 2
        ret

and long << 2 to this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
***     mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        shr %ECX, 30
        mov %EDX, DWORD PTR [%ESP + 8]
        shl %EDX, 2
        or %EDX, %ECX
        shl %EAX, 2
        ret

The extra copy (marked ***) can be eliminated when I teach the code generator
that shrd32rri8 is really commutative.

llvm-svn: 19681
 2005-01-19 06:18:43 +00:00
Chris Lattner d8d306601a X86 shifts mask the amount. 
llvm-svn: 19678
 2005-01-19 03:36:30 +00:00
Chris Lattner 14947c34cc Code to handle FP_EXTEND is dead now. X86 doesn't support any data types to 
FP_EXTEND from!

llvm-svn: 19674
 2005-01-18 20:05:56 +00:00
Chris Lattner c6e928cba5 Remove more dead code. 
llvm-svn: 19673
 2005-01-18 19:50:08 +00:00
Chris Lattner 0616fa6b9b The selection dag code handles the promotions from F32 to F64 for us, so we 
don't need to even think about F32 in the X86 code anymore.

llvm-svn: 19672
 2005-01-18 19:46:54 +00:00
Chris Lattner 479c7118e4 Fix 124.m88ksim. 
llvm-svn: 19667
 2005-01-18 17:35:28 +00:00
Chris Lattner ed246ec0d2 Do not emit loads multiple times, potentially in the wrong places. 
llvm-svn: 19661
 2005-01-18 04:18:32 +00:00
Chris Lattner 28a205e01b Eliminate bad assertions. 
llvm-svn: 19659
 2005-01-18 04:00:54 +00:00
Chris Lattner 78d3028350 * Eliminate the TokenSet and just use the ExprMap for both tokens and values. 
* Insert some really pedantic assertions that will notice when we emit the
  same loads more than one time, exposing bugs.  This turns a miscompilation in
  bzip2 into a compile-fail.  yaay.

llvm-svn: 19658
 2005-01-18 03:51:59 +00:00
Chris Lattner d7f93950aa Rely on the code in MatchAddress to do this work. Otherwise we fail to 
match (X+Y)+(Z << 1), because we match the X+Y first, consuming the index
register, then there is no place to put the Z.

llvm-svn: 19652
 2005-01-18 02:25:52 +00:00
Chris Lattner a7acdda064 Fix a problem where probing for addressing modes caused expressions to be 
emitted too early.  In particular, this fixes
Regression/CodeGen/X86/regpressure.ll:regpressure3.

This also improves the 2nd basic block in 164.gzip:flush_block, which went from

.LBBflush_block_1:      # loopentry.1.i
        movzx %EAX, WORD PTR [dyn_ltree + 20]
        movzx %ECX, WORD PTR [dyn_ltree + 16]
        mov DWORD PTR [%ESP + 32], %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 12]
        movzx %EDX, WORD PTR [dyn_ltree + 8]
        movzx %EBX, WORD PTR [dyn_ltree + 4]
        mov DWORD PTR [%ESP + 36], %EBX
        movzx %EBX, WORD PTR [dyn_ltree]
        add DWORD PTR [%ESP + 36], %EBX
        add %EDX, DWORD PTR [%ESP + 36]
        add %ECX, %EDX
        add DWORD PTR [%ESP + 32], %ECX
        add %EAX, DWORD PTR [%ESP + 32]
        movzx %ECX, WORD PTR [dyn_ltree + 24]
        add %EAX, %ECX
        mov %ECX, 0
        mov %EDX, %ECX

to

.LBBflush_block_1:      # loopentry.1.i
        movzx %EAX, WORD PTR [dyn_ltree]
        movzx %ECX, WORD PTR [dyn_ltree + 4]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 8]
        add %EAX, %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 12]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 16]
        add %EAX, %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 20]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 24]
        add %ECX, %EAX
        mov %EAX, 0
        mov %EDX, %EAX

... which results in less spilling in the function.

This change alone speeds up 164.gzip from 37.23s to 36.24s on apoc.  The
default isel takes 37.31s.

llvm-svn: 19650
 2005-01-18 01:06:26 +00:00
Chris Lattner b93409f3e2 Fix indentation. 
llvm-svn: 19649
 2005-01-17 23:25:45 +00:00
Chris Lattner a5d137f471 Don't bother using max here. 
llvm-svn: 19647
 2005-01-17 23:02:13 +00:00
Chris Lattner ca318edb94 Do not give token factor nodes outrageous weights 
llvm-svn: 19645
 2005-01-17 22:56:09 +00:00
Chris Lattner e86c933df7 Two changes: 
1. Fold  [mem] += (1|-1) into inc [mem]/dec [mem] to save some icache space.
 2. Do not let token factor nodes prevent forming '[mem] op= val' folds.

llvm-svn: 19643
 2005-01-17 22:10:42 +00:00