Commit Graph

1788 Commits

Author SHA1 Message Date
Evan Cheng a4a4ceb478 - Emit subsections_via_symbols for Darwin.
- Conditionalize Dwarf debugging output (Darwin only for now).

llvm-svn: 26582
2006-03-07 02:23:26 +00:00
Evan Cheng 30d7b70b73 Enable Dwarf debugging info.
llvm-svn: 26581
2006-03-07 02:02:57 +00:00
Chris Lattner 9c7f50376a Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
implement copysign as a native op if they have it.

llvm-svn: 26541
2006-03-05 05:08:37 +00:00
Chris Lattner c2dd7aae71 add a note for something evan noticed
llvm-svn: 26539
2006-03-05 01:15:18 +00:00
Evan Cheng c66fd44541 Add an entry
llvm-svn: 26520
2006-03-04 07:49:50 +00:00
Evan Cheng 6dc73297c3 MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of
rep/stos and rep/mov if the count is not a constant. We could do
  rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.

Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.

llvm-svn: 26517
2006-03-04 02:48:56 +00:00
Evan Cheng 084a102b17 Typo
llvm-svn: 26512
2006-03-04 01:12:00 +00:00
Chris Lattner ad3c974a77 remove the read/write port/io intrinsics.
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
Evan Cheng 1926427351 Vector op lowering.
llvm-svn: 26438
2006-03-01 01:11:20 +00:00
Evan Cheng 0e69f45b07 Another entry.
llvm-svn: 26430
2006-02-28 23:38:49 +00:00
Evan Cheng 990c3602bd Don't match x << 1 to LEAL. It's better to emit x + x.
llvm-svn: 26429
2006-02-28 21:13:57 +00:00
Evan Cheng 877ab55e06 ConstantPoolIndex is now the displacement portion of the address (rather
than base).

llvm-svn: 26382
2006-02-26 09:12:34 +00:00
Evan Cheng 75b8783aaf Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP
and 2005-05-12-Int64ToFP.

llvm-svn: 26380
2006-02-26 08:28:12 +00:00
Evan Cheng 77d86ff8fc * Cleaned up addressing mode matching code.
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
  they need to be matched before LEA.

llvm-svn: 26376
2006-02-25 10:09:08 +00:00
Evan Cheng 1c557bfeb5 Updates.
llvm-svn: 26375
2006-02-25 10:04:07 +00:00
Evan Cheng 1fac3b3360 * Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
* Add patterns to handle GlobalAddress, ConstantPool, etc.
  MOV32ri to materialize these nodes in registers.
  ADD32ri to handle %reg + GA, etc.
  MOV32mi to handle store GA, etc. to memory.

llvm-svn: 26374
2006-02-25 10:02:21 +00:00
Evan Cheng e4a8b74e4f ConstantPoolIndex is now the displacement field of addressing mode.
llvm-svn: 26373
2006-02-25 09:56:50 +00:00
Evan Cheng 994700101e Added a common about the need for X86ISD::Wrapper.
llvm-svn: 26372
2006-02-25 09:55:19 +00:00
Evan Cheng ed169db8a5 Added an offset field to ConstantPoolSDNode.
llvm-svn: 26371
2006-02-25 09:54:52 +00:00
Evan Cheng 42d5ac557c Fix an obvious bug exposed when we are doing
ADD X, 4
==>
MOV32ri $X+4, ...

llvm-svn: 26366
2006-02-25 01:37:02 +00:00
Evan Cheng e0ed6ec13f - Clean up the lowering and selection code of ConstantPool, GlobalAddress,
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
  mentioned leaf nodes. Do not mutate and nodes and do not record the
  selection in CodeGenMap. These nodes should be safe to duplicate. This is
  a performance win.

llvm-svn: 26335
2006-02-23 20:41:18 +00:00
Chris Lattner 16f08f53b1 "." isn't enough to get a private label on linux, use ".L".
llvm-svn: 26327
2006-02-23 05:25:02 +00:00
Chris Lattner 2bacf981bf add a small and simple case.
llvm-svn: 26326
2006-02-23 05:17:43 +00:00
Evan Cheng f4448cee66 A couple of new entries.
llvm-svn: 26325
2006-02-23 02:50:21 +00:00
Evan Cheng 1f342c2884 PIC related bug fixes.
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.

llvm-svn: 26324
2006-02-23 02:43:52 +00:00
Evan Cheng 7eabbfd618 X86 codegen tweak to use lea in another case:
Suppose base == %eax and it has multiple uses, then instead of
  movl %eax, %ecx
  addl $8, %ecx
use
  leal 8(%eax), %ecx.

llvm-svn: 26323
2006-02-23 00:13:58 +00:00
Evan Cheng 7714a59d91 Missing .globl for weak / link-once .text symbols.
llvm-svn: 26321
2006-02-22 23:59:57 +00:00
Evan Cheng 73136dfecc - Added option -relocation-model to set relocation model. Valid values include static, pic,
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.

llvm-svn: 26315
2006-02-22 20:19:42 +00:00
Evan Cheng 9e252e3bcf Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
Fixed some existing bugs (wrong predicates, prefixes) at the same time.

llvm-svn: 26310
2006-02-22 02:26:30 +00:00
Chris Lattner 7ad77dfc2a split register class handling from explicit physreg handling.
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
Chris Lattner 7bb4696dc3 Updates to match change of getRegForInlineAsmConstraint prototype
llvm-svn: 26305
2006-02-21 23:11:00 +00:00
Evan Cheng d58478161f One more round of reorg so sabre doesn't freak out. :-)
llvm-svn: 26303
2006-02-21 20:00:20 +00:00
Evan Cheng 6fc1162855 A big more cleaning up.
llvm-svn: 26302
2006-02-21 19:30:30 +00:00
Evan Cheng 8711b6bff3 Moving things to their proper places.
llvm-svn: 26301
2006-02-21 19:26:52 +00:00
Evan Cheng 6e595b9fd8 Split instruction info into multiple files, one for each of x87, MMX, and SSE.
llvm-svn: 26300
2006-02-21 19:13:53 +00:00
Evan Cheng d57203c0a1 Added separate alias instructions for SSE logical ops that operate on non-packed types.
llvm-svn: 26297
2006-02-21 02:24:38 +00:00
Evan Cheng afffe63fc1 Added MMX and XMM packed integer move instructions, movd and movq.
llvm-svn: 26296
2006-02-21 01:39:57 +00:00
Evan Cheng fa57a0add9 Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
Added generic vector types: VR64 and VR128.

llvm-svn: 26295
2006-02-21 01:38:21 +00:00
Evan Cheng 43070b7541 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294
2006-02-20 22:34:53 +00:00
Evan Cheng 4547400ae2 Some updates
llvm-svn: 26292
2006-02-20 19:58:27 +00:00
Evan Cheng d13778eb30 If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take
advantage of fisttpll.

llvm-svn: 26288
2006-02-18 07:26:17 +00:00
Evan Cheng 70af620709 Added fisttp for fp to int conversion.
llvm-svn: 26283
2006-02-18 02:36:28 +00:00
Evan Cheng 06c2e6d1b3 Disable PIC for JIT.
llvm-svn: 26281
2006-02-18 01:49:25 +00:00
Evan Cheng 5caed8a231 Jit does not support PIC yet.
llvm-svn: 26278
2006-02-18 00:57:10 +00:00
Evan Cheng 5588de9415 x86 / Darwin PIC support.
llvm-svn: 26273
2006-02-18 00:15:05 +00:00
Chris Lattner 07a2677e43 unbreak the build
llvm-svn: 26260
2006-02-17 07:09:27 +00:00
Evan Cheng 593bea73ba Unbreak x86 be
llvm-svn: 26259
2006-02-17 07:01:52 +00:00
Nate Begeman 5965bd19f8 kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255
2006-02-17 05:43:56 +00:00
Chris Lattner 67c21b6c46 add note about div by power of 2
llvm-svn: 26253
2006-02-17 04:20:13 +00:00
Evan Cheng b590d3a72b Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers"
issue. Need to do more experiments.

llvm-svn: 26247
2006-02-17 00:04:28 +00:00
Nate Begeman 7e5496d5fe Kill the x86 pattern isel. boom.
llvm-svn: 26246
2006-02-17 00:03:04 +00:00
Evan Cheng db1dbbe8d6 Remove the entry about using movapd for SSE reg-reg moves.
llvm-svn: 26245
2006-02-17 00:00:58 +00:00
Evan Cheng eb7b3380fd pxor (for FLD0SS) encoding was missing the OpSize prefix.
llvm-svn: 26244
2006-02-16 23:59:30 +00:00
Evan Cheng 24c461b51e 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.

llvm-svn: 26241
2006-02-16 22:45:17 +00:00
Evan Cheng 3f99628939 Use movaps / movapd to spill / restore V4F4 / V2F8 registers.
llvm-svn: 26240
2006-02-16 21:20:26 +00:00
Nate Begeman 8a77efe4f7 Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238
2006-02-16 21:11:51 +00:00
Evan Cheng 01afec2adb MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.
llvm-svn: 26234
2006-02-16 19:34:41 +00:00
Evan Cheng ae82498e81 Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg
transfer.

According to the Intel P4 Optimization Manual:

Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.

Not to mention movaps is shorter than movss.

llvm-svn: 26226
2006-02-16 01:50:02 +00:00
Evan Cheng 03c1e6f48e A bit more memset / memcpy optimization.
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).

llvm-svn: 26224
2006-02-16 00:21:07 +00:00
Evan Cheng 7a6c21ac26 Remove an entry.
llvm-svn: 26197
2006-02-15 01:56:48 +00:00
Evan Cheng 2d23c9f1ab Use .zerofill on x86/darwin.
llvm-svn: 26196
2006-02-15 01:56:23 +00:00
Evan Cheng aacc4c3b4c cvtsd2ss / cvtss2sd encoding bug.
llvm-svn: 26193
2006-02-15 00:31:03 +00:00
Evan Cheng 665c26ab40 movaps, movapd encoding bug.
llvm-svn: 26192
2006-02-15 00:11:37 +00:00
Chris Lattner e3c793a71a new note
llvm-svn: 26186
2006-02-14 22:19:54 +00:00
Evan Cheng f84774ed46 Don't special case XS, XD prefixes.
llvm-svn: 26183
2006-02-14 21:52:51 +00:00
Evan Cheng fb7b5ef74b Bug fix: XS, XD prefixes were being emitted twice.
XMM registers were not being handled.

llvm-svn: 26182
2006-02-14 21:45:24 +00:00
Evan Cheng 43b72f4421 Duh
llvm-svn: 26180
2006-02-14 20:37:37 +00:00
Evan Cheng ad8c20cd2b Remove -disable-x86-sse
llvm-svn: 26179
2006-02-14 20:30:14 +00:00
Evan Cheng 4b40a42653 Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
llvm-svn: 26174
2006-02-14 08:38:30 +00:00
Evan Cheng f976d79f78 Add a entry.
llvm-svn: 26173
2006-02-14 08:25:32 +00:00
Evan Cheng 6a37456d73 Set maxStoresPerMemSet to 16. Ditto for maxStoresPerMemCpy and
maxStoresPerMemMove. Although the last one is not used.

llvm-svn: 26172
2006-02-14 08:25:08 +00:00
Evan Cheng 40b6eb9973 Enable SSE (for the right subtargets)
llvm-svn: 26169
2006-02-14 08:07:58 +00:00
Chris Lattner 62c3484e43 Switch targets over to using SelectionDAG::getCALLSEQ_START to create
CALLSEQ_START nodes.

llvm-svn: 26143
2006-02-13 09:00:43 +00:00
Evan Cheng a86ba85dc5 Prevent certain nodes that have already been selected from being folded into
X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.

llvm-svn: 26117
2006-02-11 02:05:36 +00:00
Evan Cheng 2b6f78b664 Nicer code. :-)
llvm-svn: 26111
2006-02-10 22:46:26 +00:00
Evan Cheng d49cc3634e Added X86 isel debugging stuff.
llvm-svn: 26110
2006-02-10 22:24:32 +00:00
Evan Cheng 907be3e24c Remove a completed entry; add a new entry about fisttp op
llvm-svn: 26105
2006-02-10 05:48:15 +00:00
Evan Cheng 101e4b916a Match tblgen change.
llvm-svn: 26096
2006-02-09 22:12:53 +00:00
Evan Cheng d1b82d8db0 Match getTargetNode() changes (now return SDNode* instead of SDOperand).
llvm-svn: 26085
2006-02-09 07:17:49 +00:00
Chris Lattner d94a3d2c8a provide an explicit alignment for cp entries
llvm-svn: 26069
2006-02-09 02:15:30 +00:00
Evan Cheng 6dc90ca172 Change Select() from
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);

llvm-svn: 26067
2006-02-09 00:37:58 +00:00
Chris Lattner 2e07d6370a Darwin doesn't support #APP/#NO_APP
llvm-svn: 26066
2006-02-08 23:42:22 +00:00
Chris Lattner b4fc050f0f add a simple optimization
llvm-svn: 26062
2006-02-08 17:47:22 +00:00
Chris Lattner b7e074ab9b more email -> README moving
llvm-svn: 26054
2006-02-08 07:12:07 +00:00
Chris Lattner 45bb34b715 Add some random notes, not high-prio
llvm-svn: 26052
2006-02-08 06:52:06 +00:00
Evan Cheng adeb8fb5a2 Fixed a local common symbol bug.
llvm-svn: 26044
2006-02-07 23:32:58 +00:00
Evan Cheng ec212fb66d For ELF, .comm takes alignment value as the optional 3rd argument. It must be
specified in bytes.

llvm-svn: 26043
2006-02-07 21:54:08 +00:00
Evan Cheng 5a76680de1 Darwin ABI issues: weak, linkonce, etc. dynamic-no-pic support is complete.
Also fixed a function stub bug. Added weak and linkonce support for
x86 Linux.

llvm-svn: 26038
2006-02-07 08:38:37 +00:00
Evan Cheng 227e469c25 Remind myself to add PIC and static asm printer support.
llvm-svn: 26037
2006-02-07 08:35:44 +00:00
Chris Lattner d62a3bfa66 Eliminate the printCallOperand method, using a 'call' modifier on
printOperand instead.

llvm-svn: 26025
2006-02-06 23:41:19 +00:00
Evan Cheng d5f2ba0d6f - Update load folding checks to match those auto-generated by tblgen.
- Manually select SDOperand's returned by TryFoldLoad which make up the
  load address.

llvm-svn: 26012
2006-02-06 06:02:33 +00:00
Evan Cheng 54cb1833a4 Use SelectRoot() as entry of any tblgen based isel.
llvm-svn: 25997
2006-02-05 06:46:41 +00:00
Evan Cheng d19d51f414 Re-commit the last bit of change that was backed out.
llvm-svn: 25983
2006-02-05 05:25:07 +00:00
Chris Lattner c070cb685d Use getPreferredAlignmentLog.
llvm-svn: 25980
2006-02-05 01:45:04 +00:00
Chris Lattner 22b4edfb42 Temporarily revert this patch, which probably breaks with the
tblgen patch reverted.

llvm-svn: 25971
2006-02-04 09:24:16 +00:00
Evan Cheng ce87cac555 Complex pattern's custom matcher should not call Select() on any operands.
Select them afterwards if it returns true.

llvm-svn: 25968
2006-02-04 08:50:49 +00:00
Evan Cheng 0a977c95aa Remove an unnecessary predicate.
llvm-svn: 25954
2006-02-04 02:23:01 +00:00
Evan Cheng 11613a5219 Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
flag so it can be flagged to a FST.

llvm-svn: 25953
2006-02-04 02:20:30 +00:00
Chris Lattner a1d312c6ea remove an old comment
llvm-svn: 25940
2006-02-03 18:59:39 +00:00
Chris Lattner 23d55f2547 Remove the X86PeepholeOptimizerPass, a truly horrible old hack that is now
obsolete.  yaay :)

llvm-svn: 25939
2006-02-03 18:54:24 +00:00
Chris Lattner c408558638 When rewriting frame instructions, emit the appropriate small-immediate
instruction when possible.

llvm-svn: 25938
2006-02-03 18:20:04 +00:00
Chris Lattner a23b04acdb remove some target-indep and implemented notes
llvm-svn: 25930
2006-02-03 06:22:11 +00:00
Chris Lattner a1eac9b978 the X86 backend no longer needs to delete its own noop copies
llvm-svn: 25923
2006-02-03 02:59:58 +00:00
Chris Lattner 5123346708 fix operand numbers
llvm-svn: 25915
2006-02-02 20:38:12 +00:00
Chris Lattner bb53acd03c Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
Chris Lattner 246ee44c8f implement isStoreToStackSlot
llvm-svn: 25911
2006-02-02 20:00:41 +00:00
Chris Lattner 0acc90c67e add a method
llvm-svn: 25910
2006-02-02 19:57:16 +00:00
Chris Lattner d8208c3665 more notes
llvm-svn: 25908
2006-02-02 19:43:28 +00:00
Chris Lattner d3f033e8e0 add a note, I have no idea how important this is.
llvm-svn: 25907
2006-02-02 19:16:34 +00:00
Chris Lattner 4b2ec8af23 implemented, testcase here: test/Regression/CodeGen/X86/compare-add.ll
llvm-svn: 25899
2006-02-02 06:36:48 +00:00
Evan Cheng d3908f79cb Update.
llvm-svn: 25896
2006-02-02 02:40:17 +00:00
Evan Cheng d8fba3a1ee Fix a erroneous comment.
llvm-svn: 25894
2006-02-02 00:28:23 +00:00
Chris Lattner 6132a87cf4 more notes
llvm-svn: 25890
2006-02-01 23:38:08 +00:00
Evan Cheng b3ea2677a4 Tell codegen MOVAPSrr and MOVAPDrr are copies.
llvm-svn: 25889
2006-02-01 23:03:16 +00:00
Evan Cheng f1ed826c2a Added SSE entries to foldMemoryOperand().
llvm-svn: 25888
2006-02-01 23:02:25 +00:00
Evan Cheng 8b40cde148 Rearrange code to my liking. :)
llvm-svn: 25887
2006-02-01 23:01:57 +00:00
Chris Lattner 2f7650f9dc another note
llvm-svn: 25883
2006-02-01 21:44:48 +00:00
Nate Begeman 7e7f439f85 Fix some of the stuff in the PPC README file, and clean up legalization
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.

llvm-svn: 25875
2006-02-01 07:19:44 +00:00
Chris Lattner 3da1bb520e add a note, I'll take care of this after nate commits his big patch
llvm-svn: 25873
2006-02-01 06:40:32 +00:00
Evan Cheng 9e350cd6ad - Use xor to clear integer registers (set R, 0).
- Added a new format for instructions where the source register is implied
  and it is same as the destination register. Used for pseudo instructions
  that clear the destination register.

llvm-svn: 25872
2006-02-01 06:13:50 +00:00
Evan Cheng c404b5748c Remove another entry.
llvm-svn: 25871
2006-02-01 06:08:48 +00:00
Chris Lattner b0a76b0981 Another regression from the pattern isel
llvm-svn: 25867
2006-02-01 01:44:25 +00:00
Evan Cheng a24617f5d4 Return's chain should be matching either the chain produced by the
value or the chain going into the load.

llvm-svn: 25863
2006-02-01 01:19:32 +00:00
Evan Cheng e1ce4d7115 When folding a load into a return of SSE value, check the chain to
ensure the memory location has not been clobbered.

llvm-svn: 25861
2006-02-01 00:20:21 +00:00
Evan Cheng bc1fcd074e Remove an item. It's done.
llvm-svn: 25860
2006-02-01 00:15:53 +00:00
Evan Cheng 5659ca8f47 Be smarter about whether to store the SSE return value in memory. If
it is already available in memory, do a fld directly from there.

llvm-svn: 25859
2006-01-31 23:19:54 +00:00
Chris Lattner 64387c3e9c turning these into 'adds' would require extra copies
llvm-svn: 25858
2006-01-31 22:59:46 +00:00
Evan Cheng 72d5c256c9 - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
- Use XORP* to implement fneg.

llvm-svn: 25857
2006-01-31 22:28:30 +00:00
Evan Cheng a91eb48547 Remove entries on fabs and fneg. These are done.
llvm-svn: 25856
2006-01-31 22:26:21 +00:00
Chris Lattner c642aa5e1c * Fix 80-column violations
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.

llvm-svn: 25854
2006-01-31 19:43:35 +00:00
Evan Cheng 2dd217b88f Added custom lowering of fabs
llvm-svn: 25831
2006-01-31 03:14:29 +00:00
Chris Lattner d916e78b0a Another high-prio selection performance bug
llvm-svn: 25828
2006-01-31 02:10:06 +00:00
Chris Lattner 2b70a6f853 more mumbling
llvm-svn: 25826
2006-01-31 00:45:37 +00:00
Chris Lattner b521361fb9 add some notes
llvm-svn: 25825
2006-01-31 00:20:38 +00:00
Evan Cheng 45df7f84ff Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.

llvm-svn: 25824
2006-01-30 23:41:35 +00:00
Evan Cheng 08390f6a21 i64 -> f32, f32 -> i64 and some clean up.
llvm-svn: 25818
2006-01-30 22:13:22 +00:00
Evan Cheng 5b97fcf0f5 Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
conversions. SSE does not have instructions to handle these tasks.

llvm-svn: 25817
2006-01-30 08:02:57 +00:00
Chris Lattner f0b24d2dc0 Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
llvm-svn: 25803
2006-01-30 04:09:27 +00:00
Chris Lattner c6fa0282d2 adjust prototype
llvm-svn: 25798
2006-01-30 03:49:07 +00:00
Chris Lattner 3c6a950653 add another note
llvm-svn: 25789
2006-01-29 09:46:06 +00:00
Chris Lattner dabee1f655 add some performance notes from looking at sgefa
llvm-svn: 25788
2006-01-29 09:42:20 +00:00
Chris Lattner 7c7cbde0e5 add a high-priority SSE issue from sgefa
llvm-svn: 25787
2006-01-29 09:14:47 +00:00
Chris Lattner 5a7a22c9dd add a missed optimization
llvm-svn: 25786
2006-01-29 09:08:15 +00:00
Reid Spencer 0c05a2c99c Add a note about lowering llvm.memset, llvm.memcpy, and llvm.memmove to a
few stores under certain conditions.

llvm-svn: 25777
2006-01-29 06:48:25 +00:00
Chris Lattner 35d20a4c00 remove now-dead code, the legalizer takes care of this for us
llvm-svn: 25776
2006-01-29 06:45:31 +00:00
Chris Lattner 132177e103 The FP stack doesn't support UNDEF, ask the legalizer to legalize it
instead of lying and saying we have it.

llvm-svn: 25775
2006-01-29 06:44:22 +00:00
Chris Lattner 61c9a8e942 Targets all now request ConstantFP to be legalized into TargetConstantFP.
'fpimm' in .td files is now TargetConstantFP.

llvm-svn: 25771
2006-01-29 06:26:08 +00:00
Jeff Cohen 4ab39e43e8 Fix typo.
llvm-svn: 25760
2006-01-29 03:45:35 +00:00
Jeff Cohen 8643ea67b1 Flesh out AMD family/models.
llvm-svn: 25755
2006-01-28 20:30:18 +00:00
Jeff Cohen 58ca0be9af Correctly determine CPU vendor.
llvm-svn: 25754
2006-01-28 19:48:34 +00:00
Jeff Cohen 71287085a1 Use union instead of reinterpret_cast.
llvm-svn: 25751
2006-01-28 18:47:32 +00:00
Jeff Cohen b5de47cd9a Fix recognition of Intel CPUs.
llvm-svn: 25750
2006-01-28 18:38:20 +00:00
Chris Lattner b3ab2d3a42 Is64Bit reflects the capability of the chip, not an aspect of the target os
llvm-svn: 25749
2006-01-28 18:23:48 +00:00
Chris Lattner be08957dc5 Fix a bunch of JIT failures with the new isel
llvm-svn: 25748
2006-01-28 18:19:37 +00:00
Jeff Cohen e128d5f724 Improve X86 subtarget support for Windows and AMD.
llvm-svn: 25747
2006-01-28 18:09:06 +00:00
Chris Lattner ccd2a20c4b silence a warning
llvm-svn: 25745
2006-01-28 10:34:47 +00:00
Chris Lattner dc8bbb6527 make this work on non-native hosts
llvm-svn: 25734
2006-01-28 06:05:41 +00:00
Evan Cheng 18243826fd A bit of wisdom from Chris on the last entry.
llvm-svn: 25715
2006-01-27 22:54:32 +00:00
Evan Cheng 63045d221b AT&T assembly convention: registers are in lower case.
llvm-svn: 25714
2006-01-27 22:53:29 +00:00
Chris Lattner dbfc299915 initialize all instance vars
llvm-svn: 25711
2006-01-27 22:37:09 +00:00
Evan Cheng 9857d075b5 Added notes about a x86 isel deficiency.
llvm-svn: 25706
2006-01-27 22:11:01 +00:00
Evan Cheng 1073ae07b0 Added a temporary option -enable-x86-sse to enable sse support. It is used by
llc-beta.

llvm-svn: 25701
2006-01-27 21:49:34 +00:00
Evan Cheng a814f0b31c Bye bye Pattern ISel, hello DAG ISel.
llvm-svn: 25700
2006-01-27 21:26:54 +00:00
Nate Begeman 8c47c3a3b1 Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality.  This addresses another piece of bug 680.  Next,
on to fixing Alpha VAARG, which I broke last time.

llvm-svn: 25696
2006-01-27 21:09:22 +00:00
Evan Cheng afab7aa8f2 A better workaround
llvm-svn: 25692
2006-01-27 19:30:30 +00:00
Chris Lattner 4be147f456 force sse/3dnow off until they work. This fixes all the x86 failures last night
llvm-svn: 25690
2006-01-27 18:30:50 +00:00
Chris Lattner ed2bb8562f Unbreak the JIT with SSE
llvm-svn: 25688
2006-01-27 18:27:18 +00:00
Evan Cheng cde9e30bc6 x86 CPU detection and proper subtarget support
llvm-svn: 25679
2006-01-27 08:10:46 +00:00
Chris Lattner 1240574609 PHI and INLINEASM are now built-in instructions provided by Target.td
llvm-svn: 25674
2006-01-27 01:46:15 +00:00
Jeff Cohen 15a8c15a1f Improve compatibility with VC2005, patch by Morten Ofstad!
llvm-svn: 25661
2006-01-26 20:41:32 +00:00
Chris Lattner ebbfb386a5 Improve compatibility with VC2005, patch by Morten Ofstad!
llvm-svn: 25653
2006-01-26 19:55:20 +00:00
Evan Cheng 54c13da29c Added preliminary x86 subtarget support.
llvm-svn: 25645
2006-01-26 09:53:06 +00:00
Evan Cheng fcdce6d26f Work around some x86 Darwin assembler bugs
llvm-svn: 25638
2006-01-26 02:27:43 +00:00
Evan Cheng 944d1e91ea When trying to fold X86::SETCC into a Select, make a copy if it has more than
one use. This allows more CMOV instructions.

llvm-svn: 25634
2006-01-26 02:13:10 +00:00
Evan Cheng 97c68f0f5c Remove the uses of STATUS flag register. Rely on node property SDNPInFlag,
SDNPOutFlag, and SDNPOptInFlag instead.

llvm-svn: 25629
2006-01-26 00:29:36 +00:00
Nate Begeman e74795cd70 First part of bug 680:
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.

llvm-svn: 25606
2006-01-25 18:21:52 +00:00
Evan Cheng 83eeefbbd1 X86 prefer scheduling for reduced register pressure.
llvm-svn: 25602
2006-01-25 09:15:17 +00:00
Evan Cheng aff0800fd1 Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it.
llvm-svn: 25596
2006-01-25 09:05:09 +00:00
Chris Lattner bc7226a7cc Loosen up these checks to allow direct uses of ESP
llvm-svn: 25595
2006-01-25 08:00:36 +00:00
Chris Lattner 27d30a5f42 use ESP directly, not a copy of ESP into some other register for fastcc calls
llvm-svn: 25584
2006-01-24 06:14:44 +00:00
Chris Lattner 6f33eaeb81 Emit the copies out of call return registers *after* the ISD::CALLSEQ_END
node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.

llvm-svn: 25580
2006-01-24 05:17:12 +00:00
Chris Lattner 68e62a5184 Allow jit-beta to work
llvm-svn: 25578
2006-01-24 04:50:48 +00:00
Chris Lattner de02d7727f Add explicit #includes of <iostream>
llvm-svn: 25515
2006-01-22 23:41:00 +00:00
Evan Cheng 468fecdc99 Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual).
Some assemblers can't recognize the aliases.

llvm-svn: 25494
2006-01-21 02:55:41 +00:00
Chris Lattner 335b46dd20 LowerReturn now doesn't have to handle f32 returns.
llvm-svn: 25484
2006-01-20 18:41:25 +00:00
Evan Cheng 0c5de2864f Stop doing that accidental commit.
llvm-svn: 25474
2006-01-20 01:14:05 +00:00
Evan Cheng cce748d316 A few more SH{L|R}D peepholes.
llvm-svn: 25473
2006-01-20 01:13:30 +00:00
Evan Cheng 9c30bd5e25 Didn't mean to commit the last one.
llvm-svn: 25469
2006-01-19 23:27:08 +00:00
Evan Cheng 8591b9f254 Added i16 SH{L|R}D patterns.
llvm-svn: 25468
2006-01-19 23:26:24 +00:00
Evan Cheng 3d2cc7e2e9 Avoid generating a redundant setcc.
llvm-svn: 25457
2006-01-19 08:52:46 +00:00
Evan Cheng 91007126c2 adc and sbb need an incoming flag to ensure it reads the carry flag
from add / sub.

llvm-svn: 25444
2006-01-19 06:53:20 +00:00
Evan Cheng a7bfbe996e Two peepholes:
(or (x >> c) | (y << (32 - c))) ==> (shrd x, y, c)
(or (x << c) | (y >> (32 - c))) ==> (shld x, y, c)

llvm-svn: 25438
2006-01-19 01:56:29 +00:00
Evan Cheng 6135a7a546 Didn't mean to check that in.
llvm-svn: 25436
2006-01-19 01:52:56 +00:00
Evan Cheng 267ba5965e A obvious typo
llvm-svn: 25435
2006-01-19 01:46:14 +00:00
Evan Cheng 621674a19d SRA shift amount must be in i8
llvm-svn: 25416
2006-01-18 09:26:46 +00:00
Evan Cheng 4b3774e0a2 If a call return type is i1, insert a truncate from X86::AL to i1.
llvm-svn: 25415
2006-01-18 08:08:38 +00:00
Evan Cheng feaed4d107 Fix lowering of calls which return f32 values.
llvm-svn: 25413
2006-01-17 21:58:21 +00:00
Evan Cheng 14417ed99c Zero extending load from i1 to i8.
llvm-svn: 25391
2006-01-17 07:02:46 +00:00
Evan Cheng 0d5b69f734 SSE does not support i64 SINT_TO_FP (FP stack doesn't either, but we custom
expand it), so ask legalizer to expand i32 UINT_TO_FP.

llvm-svn: 25386
2006-01-17 02:32:49 +00:00
Evan Cheng 561881f30a Added a FIXME comment about why FST is currently flagged to fpGETRESULT.
llvm-svn: 25381
2006-01-17 00:37:42 +00:00
Evan Cheng bec9d720b0 Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should
read a flag.

llvm-svn: 25378
2006-01-17 00:19:47 +00:00
Evan Cheng c14bb1026b More typo's
llvm-svn: 25375
2006-01-16 23:26:53 +00:00
Evan Cheng 64eeed27d9 Some typo's
llvm-svn: 25374
2006-01-16 22:48:46 +00:00
Evan Cheng 911c68d7a8 Fix FP_TO_INT**_IN_MEM lowering.
llvm-svn: 25368
2006-01-16 21:21:29 +00:00
Chris Lattner b2eacf48aa transfer some notes from my email to somewhere useful.
llvm-svn: 25361
2006-01-16 17:53:00 +00:00
Evan Cheng 2494ce49f0 Added patterns for 8-bit multiply
llvm-svn: 25338
2006-01-15 10:05:20 +00:00
Chris Lattner 78c358d1ad Use the default lowering of ISD::DYNAMIC_STACKALLOC, delete now dead code.
llvm-svn: 25333
2006-01-15 09:00:21 +00:00
Chris Lattner 8869c6f782 silence a warning
llvm-svn: 25322
2006-01-14 20:11:13 +00:00
Nate Begeman 2fba8a3aaa bswap implementation
llvm-svn: 25312
2006-01-14 03:14:10 +00:00
Evan Cheng 3bc25e8a54 A typo.
llvm-svn: 25307
2006-01-14 01:18:49 +00:00
Evan Cheng 392c7d2779 Add truncstore i1 patterns.
llvm-svn: 25296
2006-01-13 21:45:19 +00:00
Chris Lattner 5f9c134bac Fix a bug in my last X86 checkin, pointed out by cozmic
llvm-svn: 25293
2006-01-13 20:19:44 +00:00
Evan Cheng dba84bbc1e LHS = X86ISD::CMOVcc LHS, RHS means LHS = RHS if cc. So the operands must be
flipped around.

llvm-svn: 25290
2006-01-13 19:51:46 +00:00
Chris Lattner 1a8d918ef1 Enable X86 support for savestack/restorestack
llvm-svn: 25278
2006-01-13 18:00:54 +00:00
Chris Lattner 8e2f52e645 expand unsupported stacksave/stackrestore nodes
llvm-svn: 25272
2006-01-13 02:42:53 +00:00
Evan Cheng f00374e4a8 Minor update.
llvm-svn: 25263
2006-01-13 01:20:42 +00:00
Evan Cheng d7faa4bae1 More typo's. I need new eye glasses...
llvm-svn: 25261
2006-01-13 01:17:24 +00:00
Evan Cheng 731423f36a Oops. Typo.
llvm-svn: 25260
2006-01-13 01:06:49 +00:00
Evan Cheng fb22e86c4d Fix a SETCC / BRCOND folding bug.
llvm-svn: 25259
2006-01-13 01:03:02 +00:00
Evan Cheng 6305e50ee1 Fix sint_to_fp (fild*) support.
llvm-svn: 25257
2006-01-12 22:54:21 +00:00
Evan Cheng c993d4522d Specify transformation from GlobalAddress to TargetGlobalAddress and
ExternalSymbol to TargetExternalSymbol.

llvm-svn: 25253
2006-01-12 19:36:31 +00:00
Evan Cheng 84dc9b55f0 X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be
linked together).

llvm-svn: 25247
2006-01-12 08:27:59 +00:00
Evan Cheng b94db9e9a4 * Materialize GlobalAddress and ExternalSym with MOV32ri rather than
LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.

llvm-svn: 25246
2006-01-12 07:56:47 +00:00
Evan Cheng 6d2ab04463 Added ROTL and ROTR.
llvm-svn: 25232
2006-01-11 23:20:05 +00:00
Evan Cheng ae986f1f1e Support for MEMCPY and MEMSET.
llvm-svn: 25226
2006-01-11 22:15:48 +00:00
Evan Cheng 2ae799aff0 Select DYNAMIC_STACKALLOC
llvm-svn: 25225
2006-01-11 22:15:18 +00:00
Nate Begeman 1b8121b227 Add bswap, rotl, and rotr nodes
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them

llvm-svn: 25222
2006-01-11 21:21:00 +00:00
Evan Cheng bc7a0f44bd * Add special entry code main() (to set x87 to 64-bit precision).
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
  call parmater passing.

llvm-svn: 25207
2006-01-11 06:09:51 +00:00
Chris Lattner 7c551268d0 implement FP_REG_KILL insertion for the dag-dag instruction selector
llvm-svn: 25192
2006-01-11 01:15:34 +00:00
Chris Lattner 29852a58b0 Fit into 80 cols
llvm-svn: 25191
2006-01-11 00:46:55 +00:00
Evan Cheng 339edad775 SSE cmov support.
llvm-svn: 25190
2006-01-11 00:33:36 +00:00
Evan Cheng efaf5c56fd * fp to sint patterns.
* fiadd, fisub, etc.

llvm-svn: 25189
2006-01-10 22:22:02 +00:00
Evan Cheng 73a1ad975e FP_TO_INT*_IN_MEM and x87 FP Select support.
llvm-svn: 25188
2006-01-10 20:26:56 +00:00
Evan Cheng 7c4486215f * Added undef patterns.
* Some reorg.

llvm-svn: 25163
2006-01-09 23:10:28 +00:00
Evan Cheng 12181af0c7 More typos
llvm-svn: 25162
2006-01-09 22:29:54 +00:00
Evan Cheng 77fa9195cd typo
llvm-svn: 25160
2006-01-09 20:49:21 +00:00
Evan Cheng 9c249c37f8 Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
llvm-svn: 25158
2006-01-09 18:33:28 +00:00
Evan Cheng 92e2797ce2 * Added integer div / rem.
* Fixed a load folding bug.

llvm-svn: 25136
2006-01-06 23:19:29 +00:00
Evan Cheng 10d2790d50 ISEL code for MULHU, MULHS, and UNDEF.
llvm-svn: 25132
2006-01-06 20:36:21 +00:00
Chris Lattner efbb8da3f5 silence a bogus gcc warning
llvm-svn: 25129
2006-01-06 17:56:38 +00:00
Evan Cheng 53dd0ac226 Addd (shl x, 1) ==> (shl x, x) peepholes.
llvm-svn: 25123
2006-01-06 02:31:59 +00:00
Evan Cheng b03f9b32d2 fold (shl x, 1) -> (add x, x)
llvm-svn: 25120
2006-01-06 01:06:31 +00:00
Evan Cheng 172fce7050 * Fast call support.
* FP cmp, setcc, etc.

llvm-svn: 25117
2006-01-06 00:43:03 +00:00
Evan Cheng a5ae6e8320 Added ConstantFP patterns.
llvm-svn: 25108
2006-01-05 02:08:37 +00:00
Jim Laskey deeafa0f00 Had expand logic backward.
llvm-svn: 25105
2006-01-05 01:47:43 +00:00
Jim Laskey 762e9ec06c Added initial support for DEBUG_LABEL allowing debug specific labels to be
inserted in the code.

llvm-svn: 25104
2006-01-05 01:25:28 +00:00
Evan Cheng 45e19098a6 DAG based isel call support.
llvm-svn: 25103
2006-01-05 00:27:02 +00:00
Chris Lattner 8258489ca4 Fix a problem duraid pointed out to me compiling kc++ with -enable-x86-fastcc
llvm-svn: 25024
2005-12-27 03:02:18 +00:00
Evan Cheng 14c53b45f5 Added field noResults to Instruction.
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
2005-12-26 09:11:45 +00:00
Evan Cheng 782b654e6f Let the helper functions know about X86::FR32RegClass and X86::FR64RegClass.
llvm-svn: 25004
2005-12-24 09:48:35 +00:00
Evan Cheng 9ae486047e * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997
2005-12-23 22:14:32 +00:00
Evan Cheng 5c59d49630 More X86 floating point patterns.
llvm-svn: 24990
2005-12-23 07:31:11 +00:00
Chris Lattner 30107e65c8 make sure bit_convert's are expanded
llvm-svn: 24979
2005-12-23 05:15:23 +00:00
Evan Cheng dfad8ed54e Bye bye HACKTROCITY.
llvm-svn: 24935
2005-12-22 02:26:21 +00:00
Evan Cheng 9cdc16c6d3 * Fix a GlobalAddress lowering bug.
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921
2005-12-21 23:05:39 +00:00
Evan Cheng 02767195bb Oops. Accidentally deleted RET pattern. It's still needed for return void;
llvm-svn: 24920
2005-12-21 22:22:16 +00:00
Jim Laskey 9e296bee9a Disengage DEBUG_LOC from non-PPC targets.
llvm-svn: 24919
2005-12-21 20:51:37 +00:00
Evan Cheng c1583dbd63 * Added support for X86 RET with an additional operand to specify number of
bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917
2005-12-21 20:21:51 +00:00
Chris Lattner 0dcdd83c0e This was meant to go in
llvm-svn: 24900
2005-12-21 07:50:26 +00:00
Chris Lattner f431ad4477 Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns
that were overloaded to work before and after the stackifier runs.  With the
new clean world, it is possible to write patterns for these instructions: woo!

This also adds a few simple patterns here and there, though there are a lot
still missing.  These should be easy to add though. :)

See the comments under "Floating Point Stack Support" for more details on
the new world order.

This patch as absolutely no effect on the generated code, woo!

llvm-svn: 24899
2005-12-21 07:47:04 +00:00
Chris Lattner 988827a482 Wrap some long lines: no functionality change
llvm-svn: 24898
2005-12-21 05:34:58 +00:00
Evan Cheng a2f308fc3e Remove ISD::RET select code. Now tblgen'd.
llvm-svn: 24889
2005-12-21 02:41:57 +00:00
Evan Cheng a74ce62746 * Added lowering hook for external weak global address. It inserts a load
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888
2005-12-21 02:39:21 +00:00
Evan Cheng 5c0b4df483 SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns.
llvm-svn: 24886
2005-12-20 22:59:51 +00:00
Evan Cheng 5815a6e455 Added X86 readport patterns.
llvm-svn: 24879
2005-12-20 07:38:38 +00:00
Evan Cheng 6af02635a7 Added a hook to print out names of target specific DAG nodes.
llvm-svn: 24877
2005-12-20 06:22:03 +00:00
Evan Cheng 6fc31046aa X86 conditional branch support.
llvm-svn: 24870
2005-12-19 23:12:38 +00:00
Evan Cheng 1d9b671de0 It's essential we clear CodeGenMap after isel every basic block!
llvm-svn: 24867
2005-12-19 22:36:02 +00:00
Chris Lattner db8e888fb5 eliminate some redundancy
llvm-svn: 24781
2005-12-17 19:47:05 +00:00
Evan Cheng 1d71248392 Darwin API issue: indirect load of external and weak symbols.
llvm-svn: 24775
2005-12-17 09:13:43 +00:00
Evan Cheng f3b16bc5a0 Remove a few lines of dead code.
llvm-svn: 24768
2005-12-17 07:18:44 +00:00
Evan Cheng 7087cd275b Added an idea about any_extend for performance tuning.
llvm-svn: 24763
2005-12-17 06:54:43 +00:00
Evan Cheng bc7708c0e8 Added truncate.
llvm-svn: 24760
2005-12-17 02:02:50 +00:00
Evan Cheng b06925d1dd Added anyext, modelled as zext on X86.
llvm-svn: 24759
2005-12-17 01:47:57 +00:00
Evan Cheng 6b76009393 Added some isel ideas.
llvm-svn: 24757
2005-12-17 01:25:19 +00:00
Evan Cheng cb19390ead Added support for cmp, test, and conditional move instructions.
llvm-svn: 24756
2005-12-17 01:24:02 +00:00
Evan Cheng 0f68322992 Only lower SELECT when using DAG based isel.
llvm-svn: 24755
2005-12-17 01:22:13 +00:00
Evan Cheng 225a4d0d6d X86 lowers SELECT to a cmp / test followed by a conditional move.
llvm-svn: 24754
2005-12-17 01:21:05 +00:00
Chris Lattner 9f62a2a51d Don't globalize internal functions
llvm-svn: 24727
2005-12-16 00:07:30 +00:00
Evan Cheng 74151ba279 * Promote all 1 bit entities to 8 bit.
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726
2005-12-15 19:49:23 +00:00
Evan Cheng 305c6a73b5 Added frameindex, constpool, globaladdr, and externalsym as root nodes of
leaaddr.

llvm-svn: 24724
2005-12-15 08:31:04 +00:00
Evan Cheng 00fcb0017e Handling zero extension of 1 bit value.
llvm-svn: 24722
2005-12-15 01:02:48 +00:00
Evan Cheng bc9344477e Use MOV8rm to load 1 bit value.
llvm-svn: 24721
2005-12-15 00:59:17 +00:00
Evan Cheng 023aef2f31 Fixed a typo: line 2323: MOVSX16rm8 -> MOVZX16rm8. This was the cause fo 12/14/2005 hbd failure.
llvm-svn: 24717
2005-12-14 22:28:18 +00:00
Evan Cheng c273900dd8 Added sext and zext patterns.
llvm-svn: 24705
2005-12-14 02:22:27 +00:00
Evan Cheng 229f0ee6d7 Add load + store folding srl and sra patterns.
llvm-svn: 24696
2005-12-13 07:24:22 +00:00
Chris Lattner 87079884d1 Use the shared asmprinter code for printing special llvm globals
llvm-svn: 24695
2005-12-13 06:32:50 +00:00
Chris Lattner 4d80f6e52e Add ELF and darwin support for static ctors and dtors
llvm-svn: 24693
2005-12-13 04:53:51 +00:00
Evan Cheng acec857b1a Beautify a few patterns.
llvm-svn: 24690
2005-12-13 02:40:18 +00:00
Evan Cheng 89c6db4baf Some shl patterns which do load + store folding.
llvm-svn: 24689
2005-12-13 02:34:51 +00:00
Evan Cheng 108beceb0f A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility.
llvm-svn: 24688
2005-12-13 01:57:51 +00:00
Evan Cheng ddd5ae5a22 Add and, or, and xor patterns which fold load + stores.
llvm-svn: 24687
2005-12-13 01:41:36 +00:00
Evan Cheng e5a94a03e2 Add inc + dec patterns which fold load + stores.
llvm-svn: 24686
2005-12-13 01:02:47 +00:00
Evan Cheng bde9e6fca6 Add neg and not patterns which fold load + stores.
llvm-svn: 24685
2005-12-13 00:54:44 +00:00
Evan Cheng c414d563f0 Missed a couple redundant explicit type casts.
llvm-svn: 24684
2005-12-13 00:25:07 +00:00
Evan Cheng 62e6808aa5 Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc.
llvm-svn: 24683
2005-12-13 00:14:11 +00:00
Evan Cheng 86b2cf22d2 * Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands.
This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.

llvm-svn: 24682
2005-12-13 00:01:09 +00:00
Evan Cheng 3e52756928 Add some integer mul patterns.
llvm-svn: 24681
2005-12-12 23:47:46 +00:00
Evan Cheng af3fe8217a Add some sub patterns.
llvm-svn: 24675
2005-12-12 21:54:05 +00:00
Evan Cheng 67ed58e22b When SelectLEAAddr() fails, it shouldn't cause the side effect of having the
base or index operands being selected.

llvm-svn: 24674
2005-12-12 21:49:40 +00:00
Evan Cheng bfd259a2b7 For ISD::RET, if # of operands >= 2, try selection the real data dep. operand
first before the chain.
e.g.
int X;

int foo(int x)
{
  x += X + 37;
  return x;
}

If chain operand is selected first, we would generate:
	movl X, %eax
	movl 4(%esp), %ecx
	leal 37(%ecx,%eax), %eax

rather than
	movl $37, %eax
	addl 4(%esp), %eax
	addl X, %eax

which does not require %ecx. (Due to ADD32rm not matching.)

llvm-svn: 24673
2005-12-12 20:32:18 +00:00
Chris Lattner d6b17765e4 remove some never-completed and now-obsolete code.
llvm-svn: 24671
2005-12-12 20:12:20 +00:00
Evan Cheng e80248b378 Add a few more add / store patterns. e.g. ADD32mi8.
llvm-svn: 24670
2005-12-12 19:45:23 +00:00
Evan Cheng 0d6cfee704 * Added X86 store patterns.
* Added X86 dec patterns.

llvm-svn: 24654
2005-12-10 00:48:20 +00:00
Evan Cheng 275a3ed80c Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al
llvm-svn: 24648
2005-12-09 22:48:48 +00:00
Evan Cheng f039648614 Added explicit type field to ComplexPattern.
llvm-svn: 24637
2005-12-08 02:15:07 +00:00
Evan Cheng c9fab31098 * Added intelligence to X86 LEA addressing mode matching routine so it returns
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.

llvm-svn: 24635
2005-12-08 02:01:35 +00:00
Chris Lattner 3225733e65 X86 doesn't support sextinreg for 8-bit things either.
llvm-svn: 24631
2005-12-07 17:59:14 +00:00
Evan Cheng c0c190239d Remove unnecessary let hasCtrlDep=1 now it can be inferred.
llvm-svn: 24611
2005-12-05 23:09:43 +00:00
Chris Lattner 3c0b8f577d Several things:
1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly.  The port number really
   *is* a 16-bit value, but the patterns should only match if the number
   is 0-255.  Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
   i8, not an i16 as they were believed to be before.  This previous fib
   stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.

llvm-svn: 24599
2005-12-05 02:40:25 +00:00
Evan Cheng 95cb763818 Added isel patterns for RET, JMP, and WRITEPORT.
llvm-svn: 24588
2005-12-04 08:19:43 +00:00
Chris Lattner 7e79292fef Fix PR672 another way which should be more robust
llvm-svn: 24585
2005-12-04 06:03:50 +00:00
Chris Lattner ecfc7e56c5 Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672.
This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on.  Given a clean nightly tester run, we should be able to turn it
on by default!

llvm-svn: 24578
2005-12-03 07:15:55 +00:00
Chris Lattner 986cb40953 add a note
llvm-svn: 24572
2005-12-02 00:11:20 +00:00
Nate Begeman 006bb04f3a Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.

llvm-svn: 24563
2005-12-01 04:51:06 +00:00
Evan Cheng 4b02426130 Proper support for shifts with register shift value.
llvm-svn: 24559
2005-12-01 00:43:55 +00:00
Chris Lattner af2e0373dd SelectNodeTo now returns its result, we must pay attention to it.
llvm-svn: 24550
2005-11-30 22:59:19 +00:00
Nate Begeman 11695c0537 Fix a typo in my latest change
llvm-svn: 24542
2005-11-30 18:57:39 +00:00
Nate Begeman 6f8c1ace6e No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.

llvm-svn: 24541
2005-11-30 18:54:35 +00:00
Chris Lattner 9c7af08bc9 Fix a bug in a recent patch that broke shifts
llvm-svn: 24526
2005-11-30 05:11:18 +00:00
Evan Cheng 4eb7af9bc9 Added support to STORE and shifts to DAG to DAG isel.
llvm-svn: 24525
2005-11-30 02:51:20 +00:00
Evan Cheng d2cb70513d Fixed a minor bug: - -offset != offset iff offset == MININT
llvm-svn: 24522
2005-11-30 01:59:00 +00:00
Evan Cheng 72ab335858 Add more X86 ISel patterns.
llvm-svn: 24520
2005-11-29 19:38:52 +00:00
Chris Lattner 9c415364cf No targets support line number info yet.
llvm-svn: 24513
2005-11-29 06:16:21 +00:00
Chris Lattner 820c94e467 Add a missed optimization
llvm-svn: 24495
2005-11-28 04:52:39 +00:00
Chris Lattner ac6cb46429 Use HasDotTypeDotSizeDirective instead of forELF
llvm-svn: 24481
2005-11-21 23:06:54 +00:00
Chris Lattner 78161dbc84 Remove a level of indentation by using a continue.
llvm-svn: 24479
2005-11-21 22:48:18 +00:00
Chris Lattner 40f8c8450d Simplify the subtarget info, allow the asmwriter to do some target sensing
based on TargetType.

llvm-svn: 24478
2005-11-21 22:43:58 +00:00
Chris Lattner 99be8f766f Use subtarget information computed by X86Subtarget instead of rolling our own.
llvm-svn: 24477
2005-11-21 22:39:40 +00:00
Chris Lattner 3eb876117a Make the X86 subtarget compute the basic target type: ELF, Cygwin, Darwin,
or native Win32

llvm-svn: 24476
2005-11-21 22:31:58 +00:00
Chris Lattner ebc39f5a9c Add a forELF flag, allowing the removal of forCygwin and simplification of
conditionals.

llvm-svn: 24475
2005-11-21 22:19:48 +00:00
Chris Lattner 7df25ab429 simplify and genericize this code
llvm-svn: 24473
2005-11-21 19:50:31 +00:00
Chris Lattner 4a7eb5132b prune #include
llvm-svn: 24468
2005-11-21 08:33:17 +00:00
Chris Lattner 8a5f3c1b68 Switch to using the shared constant pool printer, along with using shorter
CPI ids

llvm-svn: 24467
2005-11-21 08:32:23 +00:00
Chris Lattner 99946fb63f Adjust to capitalized AsmPrinter method names
llvm-svn: 24456
2005-11-21 07:51:23 +00:00
Chris Lattner d365627d3e Use PrivateGlobalPrefix for basic block labels. This allows the x86 darwin
port to properly use L for the bb prefix instead of .

llvm-svn: 24454
2005-11-21 07:43:59 +00:00
Chris Lattner 050bf2faf8 convert the rest of this over to use SwitchSection
llvm-svn: 24448
2005-11-21 07:16:34 +00:00
Chris Lattner 024e32e118 Start using the AsmPrinter shared SwitchSection code. This allows the X86
backend to implement global variables in sections.

llvm-svn: 24447
2005-11-21 07:11:11 +00:00
Chris Lattner 2c0b435ba6 Rename SwitchSection -> switchSection to avoid conflicting with a future
change.

llvm-svn: 24443
2005-11-21 06:55:27 +00:00
Chris Lattner 618981fd03 Naturally align doubles in the constant pool, set PrivateGlobalPrefix on
darwin, use it when printing the constant pool indices so the labels are
appropriately private, emit cp entries to .const instead of .data on darwin
and only emit a single .section for the constant pool, not one for each
entry.

llvm-svn: 24440
2005-11-21 06:46:22 +00:00
Chris Lattner 6c1ca888d4 Lower READCYCLECOUNTER correctly, preserving the chain result
llvm-svn: 24438
2005-11-20 22:57:19 +00:00
Chris Lattner d1061ac8d1 encode rdtsc correctly
llvm-svn: 24435
2005-11-20 22:13:18 +00:00
Chris Lattner 6df9e11989 use chain operands to ensure the copies don't wander from the rdtsc instruction.
llvm-svn: 24434
2005-11-20 22:01:40 +00:00
Andrew Lenharth 0bf68ae434 The second patch of X86 support for read cycle counter.
llvm-svn: 24430
2005-11-20 21:41:10 +00:00
Chris Lattner d7102c4980 Teach the x86 backend about the register constraints of its addressing mode.
Patch by Evan Cheng

llvm-svn: 24423
2005-11-19 07:01:30 +00:00
Chris Lattner 3f0f71b92b Add load and other support to the dag-dag isel. Patch contributed by Evan
Cheng!

llvm-svn: 24419
2005-11-19 02:11:08 +00:00
Chris Lattner 57ce97862d add more patterns, patch by Evan Cheng.
llvm-svn: 24406
2005-11-18 01:04:42 +00:00
Chris Lattner 2bf458af92 Add patterns for some 16-bit immediate instructions, patch contributed by
Evan Cheng.

llvm-svn: 24384
2005-11-17 02:01:55 +00:00
Chris Lattner 5930d3df3d Add patterns for several simple instructions that take i32 immediates.
Patch contributed by Evan Cheng!

llvm-svn: 24382
2005-11-16 22:59:19 +00:00
Chris Lattner 655e7dfd0d initial step at adding a dag-to-dag isel for X86 backend. Patch contributed
by Evan Cheng!

llvm-svn: 24371
2005-11-16 01:54:32 +00:00